FAD7191M1X

Automotive Gate Driver IC, High and Low Side 600 V, 4.5 A FAN7191-F085, FAD7191 Description The FAN7191 / FAD7191 is a monolithic high− and low−side gate−driver IC, which can drive high speed MOSFETs and IGBTs that operate up to +600 V. It has a buffered output stage with all NMOS transistors designed for high pulse driving capability and minimum cross−conduction. ON Semiconductor’s high−voltage process and common−mode noise canceling technique provide stable operation of high−drivers under high dV/dt noise circumstances. An advanced level−shift circuit allows high−side gate driver operation up to VS = −9.8 V (typical) for VBS = 15 V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. The high current and low output voltage drop features make this device suitable for controlling direct injection actuators and for use in many automotive DC−DC converter and motor control applications. www.onsemi.com SOIC8 CASE 751EB Features • • • • • • • • • • • • Floating Channel for Bootstrap Operation to +600 V 4.5 A Sourcing and 4.5 A Sinking Current Driving Capability Common−Mode dV/dt Noise Cancelling Circuit Built−in Under−Voltage Lockout for Both Channels Matched Propagation Delay for Both Channels 3.3 V and 5 V Input Logic Compatible Output In−phase with Input Enable Pin (For 14−SOP Package Only) 14−SOP with Separate Signal and Power Ground for Enhanced Noise Immunity 14−SOP with Increased Clearance for High Voltage Applications Automotive Applications, AEC Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant SOIC14 CASE 751EF ORDERING INFORMATION Part Number Package FAN7191MX−F085 8−SOP (751EB) FAD7191M1X Shipping 2500 / Tape & Reel 14−SOP (751EF) 2500 / Tape & Reel Applications • • • • • • • • Electric and Hybrid Electric Vehicles 48 V Mild Hybrid Vehicles Automotive High Voltage DC−DC converters Motor Control (Fans, Pumps, Compressors) Advanced Fuel Injection Systems Starter/Alternator Electric Power Steering MOSFET and IGBT Driver Applications © Semiconductor Components Industries, LLC, 2016 June, 2021 − Rev. 6 1 Publication Order Number: FAN7191−F085/D FAN7191−F085, FAD7191 Typical Application Circuit Figure 1. Half−Bridge Application Circuit (8−SOP) 15 V 1 HIN NC 14 2 LIN VB 13 3 Controller VSS HO 12 4 EN FAD7191* VS 11 5 COM NC 10 6 LO NC 9 7 VDD NC 8 CBOOT C1 Figure 2. Half−Bridge Application Circuit (14−SOP) www.onsemi.com 2 FAN7191−F085, FAD7191 INTERNAL BLOCK DIAGRAM Figure 3. Functional Block Diagram (8−SOP) Figure 4. Functional Block Diagram (14−SOP) www.onsemi.com 3 FAN7191−F085, FAD7191 Pin Assignment FAN7191* FAD7191* Figure 5. Pin Assignments (Top View) Table 1. PIN DEFINITIONS 8−Pin 14−Pin Name 1 1 HIN Logic Input for High−Side Gate Driver Output 2 2 LIN Logic Input for Low−Side Gate Driver Output 3 3 VSS Logic Ground, Power ground for 8−SOP 4 EN Enable Input (Internal Pull Up) 5 COM 4 6 LO Low−Side Driver Output 5 7 VDD Low−Side and Logic Power Supply Voltage 6 11 VS High−Side Floating Supply Return 7 12 HO High−Side Driver Output 13 VB High−Side Floating Supply 8, 9, 10, 14 NC No Connect 8 Description Power Ground for 14−SOP, Low−side Driver Return www.onsemi.com 4 FAN7191−F085, FAD7191 Table 2. ABSOLUTE MAXIMUM RATINGS (TA = −40°C to 125°C, unless otherwise specified. VB, VDD and VIN are referenced to VSS) Parameter Symbol VS High−side offset voltage VS VB High−side floating supply voltage VB VHO High−side floating output voltage VDD Low−side and logic−fixed supply voltage COM Power Ground (14−SOP) Min. Max. Unit VB − 25 VB + 0.3 V −0.3 625 V VS − 0.3 VB + 0.3 V −0.3 25 V VDD − 25 VDD + 0.3 V −0.3 VDD + 0.3 V VIN Logic Input voltage (HIN, LIN, EN) VLO Low−Side Output Voltage LO (8−SOP) VSS − 0.3 VDD + 0.3 V Low−Side Output Voltage LO (14−SOP) COM − 0.3 VDD + 0.3 V Tpulse (Note 4) dVS/dt PD (Note 1, 2, 3) θJA (Note 1, 2) Minimum Pulse Width 80 ns Allowable offset voltage slew rate Power Dissipation, TA = 25°C Thermal Resistance, junction−to−ambient TJ Junction temperature TS Storage temperature ESD Electrostatic Discharge Capability V/ns 8−SOP 0.625 W 14−SOP 0.80 W 8−SOP 200 °C/W 14−SOP 156 °C/W +150 °C +150 °C 8−SOP 2500 V 14−SOP 2000 −55 Human Body Model, JESD22−A114 50 Charged Device Model, JESD22−C101 2000 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted on 76.2 × 114.3 × 1.6 mm PCB (FR−4 glass epoxy material). 2. Refer to the following standards: JESD51−2: Integral circuits thermal test method environmental conditions – natural convection. JESD51−3: Low effective thermal conductivity test board for leaded surface mount packages. 3. PD is the power that raises TJ to 150°C for TA = 25°C. PD to be derated at higher ambient temperature. 4. Minimum input pulse width that guarantee to produce an output pulse. Valid for turn on and turn off pulse width. Table 3. RECOMMENDED OPERATING CONDITIONS (VS, VDD and VIN are referenced to VSS) Symbol Parameter Min. Max. Unit VB High−side floating supply voltage VS + 10 VS + 22 V VS High−side Floating Supply Offset Voltage 6 − VBS 600 V VHO High−side Output Voltage VS VB V VDD Low−side and Logic Supply voltage 10 22 V Low−side output voltage (8−SOP) 0 VDD V Low−side output voltage (14−SOP) COM VDD V Logic input voltage (HIN, LIN, EN) 0 VDD V VLO VIN COM TA Power Ground (14−SOP) VDD − 22 VDD V −40 +125 °C Ambient Temperature Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 5 FAN7191−F085, FAD7191 Table 4. ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS) = 15.0 V, VS = VSS = COM, TA = −40°C to 125°C, unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VSS and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are referenced to COM (or VSS in case of 8−SOP). VS and COM (VSS for 8−SOP) are applicable to the respective outputs HO and LO) Symbol Characteristic Condition Min. Typ. Max. Unit V POWER SUPPLY SECTION (VDD AND VBS) VDDUV+ VBSUV+ VDD and VBS Supply Under−Voltage Positive−going Threshold 7.8 8.8 9.8 VDDUV− VBSUV− VDD and VBS Supply Under−Voltage Negative Going Threshold 7.2 8.3 9.1 VDDHYS VDD supply under−voltage lockout hysteresis 0.5 ILK Offset Supply Leakage Current VB = VS = 600 V 50 IQBS Quiescent VBS Supply Current VIN = 0 V or 5 V 45 110 IQDD Quiescent VDD Supply Current VIN = 0 V or 5 V 75 150 IPBS Operating VBS Supply Current fIN = 20 kHz, RMS value (See Figure 26) 400 800 IPDD Operating VDD Supply Current fIN = 20 kHz, RMS value (See Figure 26) 400 800 μA μA LOGIC INPUT SECTION (HIN, LIN, EN) VIH Logic “1” Input Voltage VIL Logic “0” Input Voltage IIN+ Logic “1” Input Bias Current (HIN/LIN) VIN = 5 V V 2.5 1.2 25 50 IIN− Logic “0” Input Bias Current (HIN/LIN) VIN = 0 V 1.0 2.0 IEN+ Enable High Input Bias Current EN = 5 V −100 −50 −10 IEN− Enable Low Input Bias Current EN = 0 V −140 −75 −20 RIN Input Pull−down Resistance 100 200 μA kΩ GATE DRIVER OUTPUT SECTION (HO, LO) VOH High−level Output Voltage, VBIAS−VO VOL Low−level Output Voltage, VO IO+ Output HIGH, Short−circuit Pulsed Current VO = 0 V, VIN = 5 V with PW < 10μs 3.5 4.5 IO− Output LOW Short−circuit Pulsed Current VO = 15 V, VIN = 0 V with PW < 10 μs 3.5 4.5 VS Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO (Note 5) (Note 5) COM−VSS (Note 5) Allowable COM−VSS ground offset No Load No Load VBS = 15V 14−SOP, VDD = 15 V, VSS = 0 V −9.8 −7.0 1.35 V 35 mV A −9.0 V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Parameters guaranteed by design. www.onsemi.com 6 FAN7191−F085, FAD7191 Table 5. DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS) = 15.0 V, VS = VSS = COM = 0 V, TA = −40°C to 125°C, CLOAD = 1000 pF unless otherwise specified) Symbol Characteristic Condition Min. Typ. Max. Unit ton Turn−on Propagation Delay VS = 0 V 140 200 ns toff Turn−off Propagation Delay VS = 0 V 140 200 ns MT Delay Matching 55 ns tr Turn−on Rise Time 25 50 ns tf Turn−off Fall Time 25 50 ns www.onsemi.com 7 FAN7191−F085, FAD7191 Typical Characteristics 200 Turn−off Delay Time (ns) Turn−on Delay Time (ns) 200 150 100 50 Typ Max 0 −50 −25 0 25 50 75 100 150 100 50 0 125 Typ Max −50 −25 0 Temperature (°C) Turn−off Fall Time (ns) Turn−on Rise Time (ns) 125 30 20 10 Typ Max −25 0 25 50 75 100 40 30 20 10 0 125 Typ Max −50 −25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) Figure 8. Turn−on Rise Time vs. Temperature Figure 9. Turn−off Fall Time vs. Temperature 60 60 Delay Matching of turn off (ns) Delay Matching of turn on (ns) 100 50 40 50 40 30 20 Typ 10 0 75 Figure 7. Turn−off Propagation Delay vs. Temperature 50 −50 50 Temperature (°C) Figure 6. Turn−on Propagation Delay vs. Temperature 0 25 Max −50 −25 0 25 50 75 100 125 50 40 30 20 Typ 10 0 Max −50 Temperature (°C) −25 0 25 50 75 100 125 Temperature (°C) Figure 10. Turn-on Delay Matching vs. Temperature Figure 11. Turn-off Delay Matching vs. Temperature www.onsemi.com 8 FAN7191−F085, FAD7191 Quiescent VBS Supply Current (μA) Quiescent VDD Supply Current (μA) Typical Characteristics (continued) 150 120 90 60 30 0 Typ Max −50 −25 0 25 50 75 100 125 Temperature (°C) 150 120 90 60 30 Typ 0 Max −50 800 600 400 200 Typ Max 0 −50 −25 0 25 50 75 100 125 Temperature (°C) VDD Negative going UVLO threshold (V) VDD Positive going UVLO threshold (V) Temperature (°C) 75 100 125 600 400 200 0 Typ Max −50 −25 0 25 50 75 100 125 Temperature (°C) 10 9 8 Min Typ Max −50 −25 0 25 50 75 100 Min Typ Max 9 8 7 125 −50 −25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure 16. VDD UVLO+ vs. Temperature Figure 17. VDD UVLO− vs. Temperature 10 10 VBS Negative going UVLO threshold (V) VBS Positive going UVLO threshold (V) 50 Figure 15. Operating VBS Supply Current vs. Temperature 10 9 8 Min Typ Max 7 25 800 Figure 14. Operating VDD Supply Current vs. Temperature 7 0 Figure 13. Quiescent VBS Supply Current vs. Temperature Operating VBS Supply Current (μA) Operating VDD Supply Current (μA) Figure 12. Quiescent VDD Supply Current vs. Temperature −25 9 8 7 −50 −25 0 25 50 75 100 Min Typ Max 125 −50 −25 0 25 50 75 100 125 Temperature (°C) Temperature (°C) Figure 18. VBS UVLO+ vs. Temperature Figure 19. VBS UVLO− vs. Temperature www.onsemi.com 9 FAN7191−F085, FAD7191 1,4 1,2 1 0,8 0,6 0,4 Max Typ 0,2 0 −50 −25 0 25 50 75 100 125 Low Level Output Voltage (mV) High Level Output Voltage (V) Typical Characteristics (continued) 30 25 20 15 10 5 0 Typ Max −50 −25 0 Temperature (°C) Logic Low Input Voltage (V) Logic High Input Voltage (V) 2,5 2 1,5 Typ Max −25 0 25 50 75 100 125 2 1,5 1 Typ Max −50 −25 0 Allowable negative Vs voltage (V) High Input bias current (μA) 40 30 20 10 Typ Max 25 50 50 75 100 125 Figure 23. Logic Low Input Voltage vs. Temperature 50 0 25 Temperature (°C) 60 −25 125 2,5 Figure 22. Logic High Input Voltage vs. Temperature −50 100 3 Temperature (°C) 0 75 Figure 21. Low−Level Output Voltage vs. Temperature 3 −50 50 Temperature (°C) Figure 20. High−Level Output Voltage vs. Temperature 1 25 75 100 125 −6 −7 −8 −9 −10 −11 −12 Typ Max −50 Temperature (°C) −25 0 25 50 75 100 Temperature (°C) Figure 24. Logic “1” Input Bias Current vs. Temperature Figure 25. Allowable Negative VS Voltage vs. Temperature www.onsemi.com 10 125 FAN7191−F085, FAD7191 Switching Time Definitions 15 V HIN 1 HIN VB LIN 2 LIN HO 7 8 10 μF 1 nF 3 VSS VS 4 LO NC 14 2 LIN VB 13 3 VSS HO 12 100 nF 6 5 COM NC 10 6 LO NC 9 7 VDD NC 8 1 nF VDD 5 100 nF 10 μF 100 nF 15 V 10 μF Figure 26. Switching Time Test Circuit EN HIN LIN HIN LIN HO LO HO LO Figure 27. Input / Output Timing Diagram HIN LIN 50% tON 50% tR tOFF 90% 90% HO LO tF 10% 10% Figure 28. Switching Time Waveform Definitions HIN LIN 50% 50% MT LO HO 90% 10% LO HO MT Figure 29. Delay Matching Waveform Definition www.onsemi.com 11 15 V 10 μF 1 nF 4 EN FAD7191* VS 11 15 V 1 nF 1 HIN 100 nF MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 CASE 751EB ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13735G SOIC8 DATE 24 AUG 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC14 CASE 751EF ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13739G SOIC14 DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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