3-Phase Half-Bridge
Gate-Drive IC
FAN73896
Description
The FAN73896 is a monolithic three−phase half−bridge gate−drive
IC designed for high−voltage, high−speed, driving MOSFETs and
IGBTs operating up to +600 V.
ON Semiconductor’s high−voltage process and common−mode
noise−canceling technique provide stable operation of high−side
drivers under high−dv/dt noise circumstances.
An advanced level−shift circuit allows high−side gate driver
operation up to VS = −9.8 V (typical) for VBS = 15 V.
The protection functions include under−voltage lockout and inverter
over−current trip with an automatic fault−clear function. Over−current
protection that terminates all six outputs can be derived from an
external current−sense resistor. An open−drain fault signal is provided
to indicate that an over−current or under−voltage shutdown has
occurred. The UVLO circuits prevent malfunction when VDD and VBS
are lower than the threshold voltage.
Output drivers typically source and sink 350 mA and 650 mA,
respectively; which is suitable for three−phase half−bridge
applications in motor drive systems.
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SOIC−28, 300 mils
CASE 751BM−01
MARKING DIAGRAM
$Y&Z&2&K
FAN73896
Pin 1
Features
FAN73896
$Y
&Z
&2
&K
• Floating Channel for Bootstrap Operation to +600 V
• Typically 350 mA/650 mA Sourcing/Sinking Current−Driving
•
•
•
•
•
•
•
•
•
•
•
•
Capability for All Channels
Extended Allowable Negative VS Swing to −9.8 V for Signal
Propagation at VDD = VBS = 15 V
Output In−Phase with Input Signal
Over−Current Shutdown Turns Off All Six Drivers
Matched Propagation Delay for All Channels
3.3 V and 5.0 V Input Logic Compatible
Adjustable Fault−Clear Timing
Built−in Advanced Input Filter
Built−in Shoot−Through Prevention Logic
Built−in Soft Turn−Off Function
Common−Mode dv/dt Noise−Canceling Circuit
Built−in UVLO Functions for All Channels
This is a Pb−Free Device
= Specific Device Code
= ON Semiconductor Logo
= Assembly Plant Code
= 2−Digit Date Code Format
= 2−Digits Lot Run Traceability Code
Applications
• 3−Phase Motor Inverter Driver
• Air Conditioner, Washing Machine,
Refrigerator, Dish Washer
• Industrial Inverter – Sewing Machine,
•
Power Tool
General−Purpose Three−Phase Inverter
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
Table 1. COMPARISION TABLE
Part
FAN73893MX
FAN73894MX
FAN73895MX
FAN73896MX
INPUT Type
Inverted
Inverted
Non−inverted
Non−inverted
VDDUV+ / VBSUV+ (Min / Typ / Max)
7.5 / 8.5 / 9.3 [V]
10.2 / 11.2 / 12 [V]
7.5 / 8.5 / 9.3 [V]
10.2 / 11.2 / 12 [V]
VDDUV− / VBSUV− (Min / Typ / Max)
7 / 8 / 8.7 [V]
9.7 / 10.7 / 11.4 [V]
7 / 8 / 8.7 [V]
9.7 / 10.7 / 11.4 [V]
Note
(Replacement for
FAN73892MX)
−
(Replacement for
FAN7389MX1)
−
© Semiconductor Components Industries, LLC, 2015
November, 2019 − Rev. 2
1
Publication Order Number:
FAN73896/D
FAN73896
TYPICAL APPLICATION DIAGRAM
VDD
5 V line
1
VDD
VB1 28
UU
2
HIN1
HO1 27
Uup
VU
3
HIN2
VS1 26
VS1
WU
4
HIN3
VB2 24
UL
5
LIN1
VL
6
LIN2
WL
7
LIN3
CONTROL
CRCIN
FAN73896MX
3−Phase
BLDC Motor
Controller
VMOTOR
Uup
HO2 23
Vup
VS2 22
VS2
Wup
VS3 18
VS3
10 EN
LO1 16
Udn
11
LO2 15
Vdn
LO3 14
Wdn
FO
CS
Wup
VS1
VB3 20
HO3 19
8
9
Vup
RCIN
12 VSS
3−Phase Inverter
VS2
VS3
Udn
Vdn
Wdn
13 COM
RCS
Figure 1. 3−Phase BLDC Motor Drive Application
INTERNAL BLOCK DIAGRAM
10 kW
10 kW
50 kW
HIN3
10 kW
50 kW
LIN2
10 kW
10 kW
50 kW
HO1
VS1
VDD
VDD
UVLO
SHOOT THOUGH
PREVENTION
ULIN
VSS−COM
LEVELSHIFTER
DELAY
LO1
COM
DEAD−TIME
U Phase Driver
UVLO
{DT = 320 ns}
50 kW
LIN3
S
Q
{T FLTIN = 250 ns}
10 kW
50 kW
LIN1
INPUT NOISE
FILTER
R R
NOISE
CANCELLER
DRIVER
HIN2
UHIN
PULSE
GENERATOR
UVLO
50 kW
DRIVER
VB1
HIN1
ISOFT
VB2
VDD
ENABLE INPUT
FILTER
VHIN
VH
V Phase Driver
VLIN
{T FLTEN = 250 ns}
VS2
LO2
FO
VSS
EN
COM
ISOFT
VB3
VDD
LEB
WHIN
WLIN
ENABLE
HO3
W Phase Driver
VS3
LO3
150 kW
COM
VDD_UVLO
ISOFT
SOFT−OFF
VREF
CS
i RCIN
VRCIN,TH = 3.3 V
VRCIN,HYS = 0.7 V
RCIN
Q
LATCH
R
S
CS_COMP
LEB
100 kW
0.5 V
3.3 V
Protection Circuit
Figure 2. Functional Block Diagram
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2
FAN73896
18 VS3
17 NC
16 LO1
10
11
12
13
14
EN
RCIN
VSS
COM
LO3
15 LO2
19 HO3
9
CS
21 NC
20 VB3
8
FO
22 VS2
7
LIN3
23 HO2
6
LIN2
24 VB2
5
LIN1
25 NC
26 VS1
27 HO1
28 VB1
PIN CONFIGURATION
1
2
3
4
VDD
HIN1
HIN2
HIN3
FAN73896MX
Figure 3. Pin Assignments
PIN DEFINITIONS
Pin
Symbol
1
VDD
Logic and low−side gate driver power supply voltage
Description
2
HIN1
Logic Input 1 for high−side gate 1 driver
3
HIN2
Logic Input 2 for high−side gate 2 driver
4
HIN3
Logic Input 3 for high−side gate 3 driver
5
LIN1
Logic Input 1 for low−side gate 1 driver
6
LIN2
Logic Input 2 for low−side gate 2 driver
7
LIN3
Logic Input 3 for low−side gate 3 driver
8
FO
Fault output with open drain (indicates over−current and low−side under−voltage)
9
CS
Analog input for over−current shutdown
10
EN
Logic input for shutdown functionality
11
RCIN
An external RC network input used to define the fault−clear delay
12
VSS
Logic ground
13
COM
Low−side driver return
14
LO3
Low−side gate driver 3 output
15
LO2
Low−side gate driver 2 output
16
LO1
Low−side gate driver 1 output
17, 21, 25
NC
No connect
18
VS3
High−side driver 3 floating supply offset voltage
19
HO3
High−side driver 3 gate driver output
20
VB3
High−side driver 3 floating supply
22
VS2
High−side driver 2 floating supply offset voltage
23
HO2
High−side driver 2 gate driver output
24
VB2
High−side driver 2 floating supply
26
VS1
High−side driver 1 floating supply offset voltage
27
HO1
High−side driver 1 gate driver output
28
VB1
High−side driver 1 floating supply
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3
FAN73896
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Symbol
Min
Max
Unit
VS
High−Side Floating Offset Voltage
VB1,2,3 − 25
VB1,2,3 + 0.3
V
VB
High−Side Floating Supply Voltage
−0.3
625.0
V
VDD
Low−Side and Logic−Fixed supply voltage
−0.3
25.0
V
VHO
High−Side Floating Output Voltage VHO1,2,3
VS1,2,3 − 0.3
VB1,2,3 + 0.3
V
VLO
Low−Side Floating Output Voltage VLO1,2,3
−0.3
VDD + 0.3
V
VIN
Input Voltage (HINx, LINx, CS, and EN) (Note 1)
−0.3
5.5
V
VFO
Fault Output Voltage (FO)
−0.3
VDD + 0.3
V
Allowable Offset Voltage Slew Rate
−
±50
V/ns
PD
Power Dissipation (Note 2, 3)
−
1.4
W
qJA
Thermal Resistance
−
70
°C/W
TJ
Junction Temperature
−
150
°C
TSTG
Storage Temperature
−55
150
°C
dVS/dt
Parameter
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All input voltage (HINx, LINx, CS, and EN) are referenced to VSS and do not exceed maximum voltage rating.
2. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material). Refer to the following standards:
JESD51−2: Integral circuit’s thermal test method environmental conditions, natural convection;
JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages.
3. Do not exceed maximum power dissipation (PD) under any circumstances.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VS1,2,3 + 10
VS1,2,3 + 20
V
VB1,2,3
High−Side Floating Supply Voltage
VS1,2,3
High−Side Floating Supply Offset Voltage
6 − VDD
600
V
VDD
Low−Side and Logic Fixed Supply Voltage
12
20
V
VHO1,2,3
High−Side Output Voltage
VS1,2,3
VB1,2,3
V
VLO1,2,3
Low−Side Output Voltage
COM
VDD
V
VFO
Fault Output Voltage (FO)
VSS
VDD
V
VCS
Current−Sense Pin Input Voltage
VSS
5
V
VIN
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
COM
TA
VSS
5
V
Low−Side Driver Return
−5
5
V
Ambient Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
FAN73896
ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN
parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM
and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to VSS. The VBSUV
parameters are referenced to VS1,2,3.)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
LOW−SIDE POWER SUPPLY SECTION
IQDD
Quiescent VDD Supply Current
VLIN1,2,3 = 0 V or 5 V, EN = 0 V
−
250
400
mA
IPDD
Operating VDD Supply Current
CLOAD = 1 nF, fLIN1,2,3 = 20 kHz,
rms Value
−
550
750
mA
VDDUV+
VDD Supply Under−Voltage Positive−Going Threshold
VDD = Sweep
9.7
11.0
12.0
V
VDDUV−
VDD Supply Under−Voltage Negative−Going Threshold
VDD = Sweep
9.2
10.5
11.4
V
VDDHYS
VDD Supply Under−Voltage Lockout Hysteresis
VDD = Sweep
−
0.5
−
V
BOOTSTRAPPED POWER SUPPLY SECTION
VBSUV+
VBS Supply Under−Voltage Positive−Going Threshold
VBS1,2,3 = Sweep
9.7
11.0
12.0
V
VBSUV−
VBS Supply Under−Voltage Negative−Going Threshold
VBS1,2,3 = Sweep
9.2
10.5
11.4
V
VBSHYS
VBS Supply Under−Voltage Lockout Hysteresis
VBS1,2,3 = Sweep
−
0.5
−
V
ILK
Offset Supply Leakage Current
VB1,2,3 = VS1,2,3 = 600 V
−
−
10
mA
IQBS
Quiescent VBS Supply Current
VHIN1,2,3 = 0 V or 5 V, EN = 0 V
10
50
80
mA
IPBS
Operating VBS Supply Current
CLOAD = 1 nF, fHIN1,2,3 = 20 kHz,
rms Value
200
320
480
mA
GATE DRIVER OUTPUT SECTION
VOH
High−Level Output Voltage, VBIAS − VO
IO = 0 mA (No Load)
−
−
100
mV
VOL
Low−Level Output Voltage, VO
IO = 0 mA (No Load)
−
−
100
mV
IO+
Output HIGH Short−Circuit Pulse Current (Note 4)
VO = 15 V, VIN = 0 V with
PW ≤ 10 ms
250
350
−
mA
IO−
Output LOW Short−Circuit Pulsed Current (Note 4)
VO = 0 V, VIN = 5 V with PW ≤ 10 ms
500
650
−
mA
VS
Allowable Negative VS Pin Voltage for HIN Signal
Propagation to HO
−
−9.8
−9.0
V
LOGIC INPUT SECTION
VIH
Logic “1” Input Voltage HIN1,2,3, LIN1,2,3
2.5
−
−
V
VIL
Logic “0” Input Voltage HIN1,2,3, LIN1,2,3
−
−
0.8
V
IIN+
Logic Input Bias Current (HO = LO = HIGH)
VIN = 5 V
77
100
143
mA
IIN−
Logic Input Bias Current (HO = LO = LOW)
VIN = 0 V
−
−
2
mA
RIN
Logic Input Pull−Up Resistance
35
50
65
kW
Enable Positive−Going Threshold Voltage
2.5
−
−
V
VEN−
Enable Negative−Going Threshold Voltage
−
−
0.8
V
IEN+
Logic Enable “1” Input Bias Current
VEN = 5 V (Pull−Down = 150 kW)
15
33
50
mA
IEN−
Logic Enable “0” Input Bias Current
VEN = 0 V
−
−
2
mA
REN
Logic Input Pull−Down Resistance
100
150
333
kW
Over−Current Detect Positive Threshold
450
500
550
mV
Over−Current Detect Negative Threshold
−
440
−
mV
Over−Current Detect Hysteresis
−
60
−
mV
5
10
15
mA
25
40
55
mA
ENABLE CONTROL SECTION (EN)
VEN+
OVER−CURRENT PROTECTION SECTION
VCSTH+
VCSTH−
VCSHYS
ICSIN
Short−Circuit Input Current
ISOFT
Soft Turn−Off Sink Current
VCSIN = 1 V
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FAN73896
ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN
parameters are referenced to VSS and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM
and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to VSS. The VBSUV
parameters are referenced to VS1,2,3.) (continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
2.7
3.3
3.9
V
FAULT OUTPUT SECTION
VRCINTH+
RCIN Positive−Going Threshold Voltage
VRCINTH−
RCIN Negative−Going Threshold Voltage (Note 4)
−
2.6
−
V
VRCINHYS
RCIN Hysteresis Voltage (Note 4)
−
0.7
−
V
IRCIN
RCIN Internal Current Source
CRCIN = 2 nF
3
5
7
mA
VFOL
Fault Output Low Level Voltage
VCS = 1 V, IFO = 1.5 mA
−
0.2
0.5
V
RCIN On Resistance
IRCIN = 1.5 mA
50
75
100
W
Fault Output On Resistance
IFO = 1.5 mA
90
130
170
W
RDSRCIN
RDSFO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. These parameters are guaranteed by design.
DYNAMIC ELECTRICAL CHARACTERISTICS (TA = 25°C, VBIAS (VDD, VBS1,2,3) = 15.0 V, VS1,2,3 = COM, CRCIN = 2 nF, and
CLoad = 1000 pF unless otherwise specified.)
Condition
Min
Typ
Max
Unit
tON
Turn−On Propagation Delay
Parameter
VLIN1,2,3 = VHIN1,2,3 = 5 V, VS1,2,3 = 0 V
350
500
650
ns
tOFF
Turn−Off Propagation Delay
VLIN1,2,3 = VHIN1,2,3 = 0 V, VS1,2,3 = 0 V
350
500
650
ns
tR
Turn−On Rise Time
VLIN1,2,3 = VHIN1,2,3 = 5 V
20
50
100
ns
tF
Turn−Off Fall Time
VLIN1,2,3 = VHIN1,2,3 = 0 V
10
30
80
ns
400
500
600
ns
Symbol
tEN
tCSBLT
CS Pin Leading−Edge Blanking Time
400
650
850
ns
tCSFO
Time from CS Triggering to FO
From VCSC = 1 V to FO Turn−Off
−
850
1300
ns
tCSOFF
Time from CS Triggering to Low−Side Gate
Outputs Turn−Off
From VCSC = 1 V to Starting Gate
Turn−Off
−
850
1300
ns
tFLTIN
Input Filtering Time (Note 5) (HINx, LINx, EN)
170
250
330
ns
−
1.30
2.35
ms
230
320
400
ns
Dead−Time Matching (All Six Channels) (Note 6)
−
−
50
ns
MT
Delay Matching (All Six Channels) (Note 7)
−
−
50
ns
PM
Output Pulse−Width Matching (Note 8)
−
50
100
ns
tFLTCLR
DT
MDT
5.
6.
7.
8.
Enable LOW to Output Shutdown Delay
Fault−Clear Time
Dead Time
PWIN > 1 ms
The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.
MDT is defined as | DT1-DT2 | referenced to 0.
MT is defined as an absolute value of matching delay time between High−side and Low−side.
PM is defined as an absolute value of matching pulse−width between Input and Output.
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FAN73896
650
650
600
600
550
550
tOFF [ns]
tON [ns]
TYPICAL CHARACTERISTICS
500
450
500
450
High−Side
Low−Side
400
350
−40
−20
0
20
40
60
80
Temperature [°C]
100
350
−40
120
−20
0
100
80
90
70
80
60
70
50
60
50
120
30
20
High−Side
Low−Side
30
−20
0
20
40
60
80
100
High−Side
Low−Side
10
0
−40
120
−20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 6. Turn−On Rise Time vs. Temperature
Figure 7. Turn−Off Fall Time vs. Temperature
2.0
600
1.8
tFLTCLR [ms]
550
tEN [ns]
100
40
40
500
450
400
−40
20
40
60
80
Temperature [°C]
Figure 5. Turn−Off Propagation Delay
vs. Temperature
tF [ns]
tR [ns]
Figure 4. Turn−On Propagation Delay
vs. Temperature
20
−40
High−Side
Low−Side
400
1.6
1.4
1.2
−20
0
20
40
60
80
Temperature [°C]
100
1.0
−40
120
Figure 8. Enable LOW to Output Shutdown Delay
vs. Temperature
−20
0
20
40
60
80
Temperature [°C]
100
120
Figure 9. Fault−Clear Time vs. Temperature
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FAN73896
400
50
350
25
MDT [ns]
DT [ns]
TYPICAL CHARACTERISTICS (continued)
300
0
−25
250
200
−40
DT1
DT2
−20
0
20
40
60
80
100
−50
−40
120
−20
0
Temperature [°C]
40
60
80
100
120
Figure 11. Dead−Time Matching vs. Temperature
−7
−8
−9
VS [V]
Delay Matching [ns]
Figure 10. Dead Time vs. Temperature
50
40
30
20
10
0
−10
−20
−30
−40
−50
−40
20
Temperature [°C]
−10
−11
−12
MTON
MTOFF
−20
0
20
40
60
80
100
−13
−40
120
−20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 13. Allowable Negative VS Voltage
vs. Temperature
Figure 12. Delay Matching vs. Temperature
100
400
350
80
IQBS [mA]
IQDD [mA]
300
250
200
60
40
150
20
100
50
−40
−20
0
20
40
60
80
100
0
−40
120
Temperature [°C]
−20
0
20
40
60
80
100
120
Temperature [°C]
Figure 14. Quiescent VDD Supply Current
vs. Temperature
Figure 15. Quiescent VBS Supply Current
vs. Temperature
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FAN73896
700
700
600
600
500
500
IPBS [mA]
IPDD [mA]
TYPICAL CHARACTERISTICS (continued)
400
400
300
300
200
200
100
−40
−20
0
20
40
60
80
100
100
120
−40
−20
0
Temperature [°C]
40
60
80
100
120
Figure 17. Operating VBS Supply Current
vs. Temperature
12.0
11.5
11.5
11.0
VDDUV− [V]
VDDUV+ [V]
Figure 16. Operating VDD Supply Current
vs. Temperature
11.0
10.5
10.5
10.0
10.0
−40 −20
0
20
40
60
80
9.5
−40 −20
100 120
0
Temperature [°C]
20
40
60
80
100 120
Temperature [°C]
Figure 18. VDD UVLO+ vs. Temperature
Figure 19. VDD UVLO− vs. Temperature
12.0
11.5
11.5
11.0
VBSUV− [V]
VBSUV+ [V]
20
Temperature [°C]
11.0
10.5
10.5
10.0
10.0
−40 −20
0
20
40
60
80
9.5
100 120
Temperature [°C]
−40 −20
0
20
40
60
80
100 120
Temperature [°C]
Figure 20. VBS UVLO+ vs. Temperature
Figure 21. VBS UVLO− vs. Temperature
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FAN73896
TYPICAL CHARACTERISTICS (continued)
20
16
High−Side
Low−Side
16
12
12
VOL [mV]
VOH [mV]
20
High−Side
Low−Side
8
8
4
4
0
−40
−20
0
20
40
60
80
100
0
−40
120
−20
0
Temperature [°C]
60
80
100
120
Figure 23. Low−Level Output Voltage
vs. Temperature
3.0
3.0
2.5
VIL [V]
2.5
VIH [V]
40
Temperature [°C]
Figure 22. High−Level Output Voltage
vs. Temperature
2.0
1.5
2.0
1.5
1.0
1.0
−40
−20
0
20
40
60
80
100
0.5
−40
120
−20
0
Temperature [°C]
40
60
80
100
120
Figure 25. Logic LOW Input Voltage
vs. Temperature
160
2.0
140
1.5
IIN− [mA]
120
100
1.0
0.5
80
60
−40
20
Temperature [°C]
Figure 24. Logic HIGH Input Voltage
vs. Temperature
IIN+ [mA]
20
−20
0
20
40
60
80
100
0.0
−40
120
Temperature [°C]
−20
0
20
40
60
80
100
Temperature [°C]
Figure 26. Logic Input HIGH Bias Current
vs. Temperature
Figure 27. Logic Input LOW Bias Current
vs. Temperature
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10
120
FAN73896
100
200
80
180
60
160
REN [kW]
RIN [kW]
TYPICAL CHARACTERISTICS (continued)
40
20
0
10
140
120
12
14
16
18
100
10
20
12
Supply Voltage [V]
14
16
18
20
Supply Voltage [V]
Figure 28. Input Pull−Down Resistance
vs. Supply Voltage
Figure 29. Enable Pin Pull−Down Resistance
vs. Supply Voltage
100
400
350
80
60
IIQBS [mA]
IIQDD [mA]
300
250
200
40
150
20
100
50
10
12
14
16
18
0
10
20
12
Supply Voltage [V]
18
20
Figure 31. Quiescent VBS Supply Current
vs. Supply Voltage
700
700
600
600
500
500
IPBS [mA]
IPDD [mA]
16
Supply Voltage [V]
Figure 30. Quiescent VDD Supply Current
vs. Supply Voltage
400
300
200
100
12
14
400
300
200
14
16
18
100
12
20
Supply Voltage [V]
14
16
18
Supply Voltage [V]
Figure 32. Operating VDD Supply Current
vs. Supply Voltage
Figure 33. Operating VBS Supply Current
vs. Supply Voltage
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11
20
FAN73896
SWITCHING TIME DEFINITIONS
HINx
50%
(LINx)
t ON
50%
tR
t OFF
tF
90%
90%
HOx
(LOx)
10%
10%
Figure 34. Switching Time Waveform Definitions
A
B
C
D
E
F
HINx
LINx
EN
Shutdown
CS
Shutdown
FO
VRCIN
HOx
Shoot−Through
Prevent
Shoot−Through
Prevent
Over−Current
Protection
LOx
Figure 35. Input / Output Timing Diagram
Interval B
CS
VCS,TH+
Interval C
VCS,TH+
50%
FO
50%
t CSFO
VRCIN,TH
VRCIN
t FLTCLR
90%
Any
Output
t CSOFF
Figure 36. Detailed View of B and C Intervals During Over−Current Protection
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12
FAN73896
APPLICATIONS INFORMATION
Dead Time
Shoot−Through Protection
The shoot−through protection circuitry prevents both
high− and low−side switches from conducting at the same
time, as shown Figure 39.
Dead time is automatically inserted whenever the dead
time of the external two input signals (between HINx and
LINx signals) is shorter than internal fixed dead times (DT1
and DT2). Otherwise, external dead times larger than
internal dead times are not modified by the gate driver and
internal dead−time waveform definition is shown in
Figure 37.
HINx
LINx
Shoot−Through
Prevent
LINx
50%
50%
HINx
HOx
50%
50%
After DT
LOx
After DT
LOx
Example A
DT2
DT1
HOx
50%
50%
HINx
Figure 37. Internal Dead−Time Definitions
LINx
Shoot−Through
Prevent
Protection Function
Fault Out (FO) and Under−Voltage Lockout
The high− and low−side drivers include under−voltage
lockout (UVLO) protection circuitry that monitors the
supply voltage for VDD and VBS independently. It can be
designed to prevent malfunction when VDD and VBS are
lower than the specified threshold voltage. The UVLO
hysteresis prevents chattering during power−supply
transitions. Moreover, the fault signal (power supply voltage
FO) goes to LOW state to operate reliably during power−on
events when the power supply (VDD) is below the
under−voltage lockout high threshold voltage for the circuit
(during t1~t2). The UVLO circuit is not otherwise activated;
shown Figure 38.
HOx
LOx
Example B
Figure 39. Shoot−Through Protection
An interlock function is a device used to prevent both
high− and low−side switches from conducting at the same
time as shown in Figure 40. In most applications an interlock
is used to help prevent a device from harming its operator or
damaging itself by when two input signals of a same leg are
activated simultaneously, only one output is activated.
UVLO+
UVLO−
VDD < 3.5 V
VDD
HINx
Lower Voltage
FO
LINx
Lower Voltage
VRCINTH+
RCIN
HOx
LO
t0 t1
t2
t3
t4
LOx
Figure 38. Waveforms for Under−Voltage Lockout
S1
S2
S3
S4
S1 : High−side first → First input output mode
S2 : Low−side noise → No LOx output mode
S3 : High−side noise→ No HOx output mode
S4 : Low−side first → First input output mode
S5 : In−phase mode → No HOx output
Figure 40. Interlock Function
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13
S5
FAN73896
Enable Input
When the EN pin is in HIGH state, the gate driver operates
normally. When a condition occurs that should shut down
the gate driver, the EN pin should be LOW. The enable
circuitry has an input filter; the minimum input duration is
specified by tFLTIN (typically 250 ns).
EN
VDD
LEB
RFO
Input
Stage ON
150 kW
FO
To low side output
ISOFT
Fault
SOFT−OFF
VREF
RCIN
CS_COMP
Q
R
Latch
S
HOx
LOx
Figure 41. Output Enable Timing Waveform
Fault−Out (FO) and Over−Current Protection
FAN73896 provides an integrated fault output (FO) and
an adjustable fault−clear timer (tFLTCLR). There are two
situations that cause the gate driver to report a fault via the
FO pin. The first is an under−voltage condition of low−side
gate driver supply voltage (VDD) and the second is when the
current−sense pin (CS) recognizes a fault. If a fault condition
occurs, the FO pin is internally pulled to COM, the
fault−clear timer is activated, and all outputs (HO1, 2, 3 and
LO1, 2, 3) of the gate driver are turned off. The fault output
stays LOW until the fault condition has been removed and
the fault−clear timer expires. Once the fault−clear timer
expires, the voltage on the FO pin returns to pull−up voltage.
The fault−clear time (tFLTCLR) is determined by an
internal current source (IRCIN = 5 mA) and an external CRCIN
at the RCIN pin, as shown as:
V RCIN,TH
I RCIN
[s]
Protection Circuit
Figure 43 shows the waveform definitions of RCIN, FO,
and the low−side driver; which uses a soft turn−off method
when an under−voltage condition of the low−side gate driver
supply voltage (VDD) or the current−sense pin (CS)
recognizes a fault. If a fault condition occurs, the FO Pin is
internally pulled to COM and all outputs (HO1, 2, 3 and
LO1, 2, 3) of the gate driver are turned off. Low−side outputs
decline linearly by the internal sink current source
(ISOFT = 40 mA) for soft turn−off, as shown in Figure 43.
90%
C RCIN
100 kW
Figure 42. Over−Current Protection
50%
t EN
t FLTCLR +
CS
LEB
0.5 V
3.3 V
CRCIN
VSS
EN
To COM
VDD_UVLO
VRCIN,TH = 3.3 V
i RCIN VRCIN,HYS = 0.7 V
LINx
Leading Edge
Branking Time
VCSC
440 mV
500 mV
t CSBLT
FO
t CSFO
t FLTCLR
VRCINTH+
VRCIN
LO
90%
t CSOFF
Figure 43. RCIN and Fault−Clear Waveform Definition
(eq. 1)
Noise Filter
The RDSRCIN of the MOSFET is a characteristic discharge
curve with respect to the external capacitor CRCIN. The time
constant is defined by the external capacitor CRCIN and the
RDSRCIN of the MOSFET.
The output of current−sense comparator (CS_COMP)
passes a noise filter, which inhibits an over−current
shutdown caused by parasitic voltage spikes of VCS.
This corresponds to a voltage level at the comparator of
VCSTH+ − VCSHYS = 500 mV − 60 mV = 440 mV, where
VCSHYS = 60 mV is the hysteresis of the current comparator
(CS_COMP), as shown in Figure 42.
Input Noise Filter
Figure 44 shows the input noise filter method, which has
symmetry duration between the input signal (tINPUT) and the
output signal (tOUTPUT) and helps to reject noise spikes and
short pulses. This input filter is applied to the HINx, LINx,
and EN inputs. The upper pair of waveforms (Example A)
shows input signal duration (tINPUT) much longer than input
filter time (tFLTIN); it is approximately the same duration
between the input signal time (tINPUT) and the output signal
time (tOUTPUT). The lower pair of waveforms (Example B)
shows an input signal time (tINPUT) slightly longer than
input filter time (tFLTIN); it is approximately the same
duration between input signal time (tINPUT) and the output
signal time (tOUTPUT).
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14
FAN73896
Figure 46 shows the characteristics of the input filters
while receiving narrow ON and OFF pulses. If input signal
pulse duration, PWIN, is less than input filter time, tFLTIN;
the output pulse, PWOUT, is zero. The input signal is rejected
by input filter. Once the input signal pulse duration, PWIN,
exceeds input filter time, tFLTIN, the output pulse durations,
PWOUT, matches the input pulse durations, PWIN.
FAN73896 input filter time, tFLTIN, is about 250 ns for the
high− and low−side outputs.
t FLTIN
Example A
INx
t INPUT
t OUTPUT
OUTx
INx
t FLTIN
1000
Example B
t INPUT
Input Pulse
Output Pulse
900
OUTx
Output duration is
same as input duration
800
700
Output Pulse Width [ns]
t OUTPUT
Figure 44. Input Noise Filter Definition
Short−Pulsed Input Noise Rejection Method
The input filter circuitry provides protection against
short−pulsed input signals (HINx, LINx and EN) on the
input signal lines by applied noise signal.
If the input signal duration is less than input filter time
(tFLTIN), the output does not change states.
Example A and B of the Figure 45 show the input and
output waveforms with short−pulsed noise spikes with a
duration less than input filter time; the output does not
change states.
600
500
400
300
200
100
0
100 200 300 400 500 600 700 800 900 1000
Input Pulse Width [ns]
Example B
Example A
Figure 46. Input Filter Characteristic of Narrow ON
INx
t FLTIN
t FLTIN
t FLTIN
t FLTIN
t FLTIN
t FLTIN
OUTx
(LOW)
INx
OUTx
(HIGH)
Figure 45. Noise Rejecting Input Filter Definition
ORDERING INFORMATION
Part Number
FAN73896MX (Note 9)
Package
Operating Temperature
Shipping†
28−Lead, Small Outline
Integrated Circuit, (SOIC)
(Pb−Free)
−40 to +125°C
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
9. These devices passed wave−soldering test by JESD22A−111.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−28, 300 mils
CASE 751BM−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
17.78
18.03
E
10.11
10.51
E1
7.34
E
NOM
7.60
1.27 BSC
e
b
e
PIN #1
IDENTIFICATION
MAX
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2 A
A1
h
q1
q
q1 c
L
E1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34296E
SOIC−28, 300 MILS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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