FAN9672
Two-Channel Interleaved
CCM PFC Controller
Description
The FAN9672 is an interleaved two−channel Continuous
Conduction Mode (CCM) Power Factor Correction (PFC) controller
IC intended for PFC pre−regulators. Incorporating circuits for leading
edge, average current, and “boost”−type power factor correction; the
FAN9672 enables the design of a power supply that fully complies
with the IEC1000−3−2 specification. Interleaved operation provides
substantial reduction in the input and output ripple currents and the
conducted EMI filtering becomes simpler and cost effective.
An innovative channel−management function allows slave channels
to be loaded and unloaded smoothly in lower power−level conditions
according to setting voltage on the CM pin, improving the PFC
converter’s load transient response.
The FAN9672 also incorporates a variety of protection functions,
including: peak current limiting, input voltage brownout protection,
and TriFault Detect function.
www.onsemi.com
LQFP−32
FT SUFFIX
CASE 561AB
Typical Applications
•
•
•
•
•
•
High Power AC−DC Power Supply
DC Motor Power Supply
White Goods; e.g. Air Conditioner Power Supply
Server and Telecom Power Supply
UPS
Industrial Welding and Power Supply
© Semiconductor Components Industries, LLC, 2016
June, 2019 − Rev. 4
NC
LS
17
26
OPFC1
27
28
VDD
ON
VIR
NC
CM2
CM1
NC
IEA2
IEA1
RDY
29
FAN9672
TM
Z
X
Y
TT
T
M
5
6
7
8
ILIMIT2
LPK
4
RLPK
3
RI
2
GC
1
ILIMIT
IAC
PVO
SS
31
30
FBPFC
ZXYTT
16
NC
18
15
CS2−
19
14
CS2+
20
13
CS1−
21
12
CS1+
22
11
GND
23
10
OPFC2
VEA
24
25
NC
32
•
•
•
•
•
•
•
•
Continuous Conduction Mode Control
Two−Channel PFC Control (Maximum)
Average Current−Mode Control
PFC Slave Channel Management Function
Programmable Operation Frequency Range: 18 kHz ∼ 40 kHz
or 55 kHz ∼ 75 kHz
Programmable PFC Output Voltage
Dual Current Limit Functions
TriFault Detect Protects Against Feedback Loop Failure
Sag Protection
Programmable Soft−Start
Under−Voltage Lockout (UVLO)
Differential Current Sensing
Available in 32−Pin LQFP Package
BIBO
•
•
•
•
•
9
MARKING DIAGRAM
Features
= Assembly Plant Code
= Year Code
= Work Code
= Die Run Code
= Package Type (Q:LQFP)
= Manufacture Flow Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
Publication Order Number:
FAN9672/D
FAN9672
ORDERING INFORMATION
Part Number
Operating
Temperature Range
FAN9672Q
−40°C to 105°C
Package
Packing Method
32−Lead, Low Quad Flat Package (LQFP), JEDEC
MS−026, Variation BBA, 7 mm Square
Tray
TYPICAL APPLICATION
* D BP
RB 1
VIN
L PFC1
DPFC1
L PFC2
DPFC2
V PFC
CB+
AC Line
In
RFB1
EMI
Filter
RFB2
RB1
S PFC1
RA1
SPFC2
R A2
RSEN2
C FB3 RFB3
Driver Circuit
RB2
Driver Circuit
RSEN1
RF
CF1
CF2
RB3
IAC
OPFC1
CS1−
CS1+
OPFC2
CS2+
CS2−
FBPFC
BIBO
CB1
C B2
CSS
RB4
SS
C ILIMIT2
R ILIMIT2
ILIMIT2
MCU
RDY
MCU signal (DC)
PVO
RLS
C GC
R GC
VEA
IEA1
FAN9672
IEA2
LS
CM1
CM2
GND
RLPK
RI
ILIMIT
RRI
MCU
RLPK
C LPK
CVC1
CIC12
RIC1
CIC11
CVI22
RIC2
CIC21
VDD
GC
LPK
CVC2
R VC1
CRLPK
CVIR RVIR
C ILIMIT
* About DBP please reference System Design Precautions
Figure 1. Typical Application Diagram for Two−Channel PFC Converter
www.onsemi.com
2
C VDD
Standby Power
R ILIMIT
RRLPK
Channel Enable
VIR
COUT
FAN9672
BLOCK DIAGRAM
PVO
FBPFC
GC
29
4
ILIMIT ILIMIT2
VDD
VIR
SS
28
16
31
7
3
SS
2
10 A
VEA
30
GMV
1/4X
B
LPK
8
RLPK
6
IAC
32
IEA1
10
C
Peak Detector
Imo
V FBPFC
PFC UVP
2.75V/2.5V
PFC OVP
V BIBO−UVP − V BIBO−UVP
VBIBO
Brownout,
Protection
60 A
VEA
VVEA > VSS
AC UVP
S SETQ
R CLR Q
GMI1
CM1
27 OPFC1
S SETQ
LPT1
CS1− 22
R CLR Q
IEA_SAW1
ILIMIT2
CS2
Dead1
11
S SETQ
R CLR Q
GMI2
CM2
CS2+ 21
26 OPFC2
S SETQ
LPT2
CS2− 20
LS
VEA LPD
ILIMIT2
CS1
CS1+ 23
IEA2
VVIR < 1.5V, FR
VVIR > 3.5V, HV
VDD OVP
0.3V
VVEA
0.5V
RM
A
Ratio
VDD
24V/23V
1.2V / RRI
2.5V
20 A
R CLR Q
5V
IEA_SAW2
17
Dead2
13
14
CM1
CM2
55 A
55 A
UVLO
VDD
Brown−In /Out
FR: 1.05V/1.9V
HV: 1.05V/1.75V
Oscillator
V GMV−
FR: 2.4V/1.25V
HV: 2.4/1.55V
5
1
24
RI
BIBO
GND
* FR: Full Range AC Input, AC85 V~264 V
HV: High Voltage Range AC Input, AC180 ~ 264 V
Figure 2. Functional Block Diagram
LS
27
OPFC1
28
VDD
29
TM
31
6
RLPK
7
8
LPK
5
ILIMIT2
4
RI
3
GC
2
ILIMIT
1
PVO
32
IAC
NC
CM2
CM1
NC
IEA2
IEA1
RDY
FAN9672
BIBO
SS
ZXYTT
30
FBPFC
VEA
ON
16
26
OPFC2
VIR
15
17
14
18
13
19
12
NC
20
11
NC
21
10
CS2−
22
9
CS2+
23
25
CS1−
24
CS1+
GND
PIN CONFIGURATION
NC
Figure 3. Pin Layout (Top View)
www.onsemi.com
3
9
Brown out
RDY
FAN9672
Table 1. PIN DEFINITIONS
Pin #
Name
1
BIBO
Brown−In/Out Level Setting: This pin is used for brown in/out setting.
2
PVO
Programmable Output Voltage: DC voltage from a microcontroller (MCU) can be applied to this pin to
program the output voltage level. The operation range is 3.5 V ∼ 0.5 V. If VPO < 0.5 V, the PVO function
is disabled.
3
ILIMIT
4
GC
Input Voltage Gain Control: Connecting a resistor on this pin to set a gain on the input−voltage signal to
match FBPFC. The signal here is used for the LPT function. A small capacitor connecting from GC to
GND is recommended for noise filtering.
5
RI
Oscillator Setting: There are two oscillator frequency ranges: 18 ∼ 40 kHz and 50 ∼ 75 kHz. A resistor
connected from RI to ground determines the switching frequency. A resistor value between
10.6 k ∼44.4 k is recommended.
6
RLPK
Ratio of VLPK and VIN: Connect a resistor and a capacitor to this pin to adjust the ratio of VIN peak to
VLPK. Typical value is 12.4 k (1:100 of VLPK and VIN peak). The accuracy of VLPK is primarily determined by the tolerance of RRLPK at this pin.
7
ILIMIT2
Peak Current Limit Setting: Connect a resistor and a capacitor to this pin to set the over−current limit
threshold and to protect power devices from damage due to inductor saturation. This pin sets the over−
current threshold for cycle−by−cycle current limit.
8
LPK
Peak of Line Voltage: This pin can be used to provide information about the peak amplitude od the line
voltage to an MCU.
9
RDY
Output Ready Signal: When the feedback voltage on FBPFC teaches 2.4 V, the RDY pin outputs a
high−state VRDY signal to inform the MCU the downstream power stage can start normal operation.
If AC brownout is detected, the VRDY signal is LOW to signal the MCU the PFC is not ready.
10
IEA1
Output 1 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth signal to determine the pulse width for PFC gate drive 1.
11
IEA2
Output 2 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth signal to determine the pulse width for PFC gate drive 2.
12
NC
13
CM1
Channel 1 Management Setting: This pin is used to configure the characteristics of PFC enable/
disable. Pull voltage on this pin LOW (= 0 V) to enable and HIGH (> 4 V) to disable the whole PFC
system.
14
CM2
Channel 2 Management Setting: There are two control methods for channel 2. The first uses an external signal to enable/disable channel 2 (VCM2 = 0 V/VCM2 > 4 V). The second is linear increase/decrease loading of channel 2 when VVEA, proportional to power level, meets the setting level on VCM2.
15
NC
No connection.
16
VIR
Input Voltage Range Setting: A capacitor and a resistor are connected in parallel from this pin to GND.
When VVIR > 3.5 V, the PFC controller only works for the high−voltage input range (180 VAC ∼264 VAC)
and RIAC must be 12 M. When VVIR < 1.5 V, the PFC controller works for the Universal Input voltage
range (90 VAC ∼264 VAC) and RIAC must be 6 M. Voltage between 1.5 V and 3.5 V is not allowed.
17
LS
Setting for Current Predict Function: A resistor, connected from this pin to ground, is used to adjust the
compensation of linear predict function (LPT). A small capacitor connected from this pin to GND is
recommended for noise filtering.
18
NC
No connection.
19
NC
No connection.
20
CS2−
Channel 2 Negative PFC Current Sense Input
21
CS2+
Channel 2 Positive PFC Current Sense Input
22
CS1−
Channel 1 Negative PFC Current Sense Input
23
CS1+
Channel 1 Positive PFC Current Sense Input
24
GND
Ground Reference and Return
25
NC
26
OPFC2
Description
Current Command Clamp Setting: Average current mode is to control the average value of inductor
current by a current command. Connecting a resistor and a capacitor to this pin can determine a limit
value of the current command.
No connection.
No connection.
Channel 2 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
www.onsemi.com
4
FAN9672
Table 1. PIN DEFINITIONS (continued)
Pin #
Name
Description
27
OPFC1
Channel 1 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
28
VDD
External Bias Supply for the IC: The typical turn−on and turn−off threshold voltages are 12.8 V and
10.8 V respectively.
29
FBPFC
30
VEA
Output of PFC Voltage−Loop Amplifier: An error−amplifier output for the PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
31
SS
Soft−Start: Connect a capacitor to this pin to set the soft−start time. Pulling this pin to ground can disable the gate drive outputs OPFC1 and OPFC2.
32
IAC
Input AC Current: During normal operation, this input provides a current reference for an internal gain
modulator. The recommended maximum current on IAC is 65 A.
Voltage Feedback Input for PFC: Inverting input of the PFC error amplifier. This pin is connected to the
PFC output through a resistor−divider network.
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
VDD
VOPFC
VL
Parameter
DC Supply Voltage
V
V
Voltage on IAC, BIBO, LPK RLPK, FBPFC, VEA, CS1+, CS2+, CS1−,
CS2−, CM1, CM2, ILIMIT, ILIMIT2, RI, PVO, GC, LS, VIR Pins
−0.3
7.0
V
0
8
V
1
mA
0.5
A
Input AC Current
TJ
30
VDD + 0.3 V
IIAC
PD
Unit
−0.3
Voltage on IEA1, IEA2, SS Pins
RJ−A
Max
Voltage on OPFC1, OPFC2 Pins
VIEA
IPFC−OPFC
Min
Peak PFC OPFC Current, Source or Sink
Power Dissipation, TA < 50 °C
Thermal Resistance (Junction−to−Air)
1640
mW
77
°C/W
Operating Junction Temperature
−40
150
°C
TSTG
Storage Temperature Range
−55
150
°C
TL
Lead temperature (Soldering)
260
°C
Human Body Model,
ANSI/ESDA/JEDEC JS−001−2012
4
kV
Charged Device Model,
JESD22−C101
2
ESD
Electrostatic Discharge Capability
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD−OP
LMISMATCH
Parameter
Min
Operating Voltage
Typ
Max
15
Boost Inductor Mismatch
−5
Unit
V
+5
%
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
www.onsemi.com
5
FAN9672
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Parameter
Symbol
Condition
Min
Typ
Max
Unit
30
80
A
4
6
7
mA
11.7
12.8
13.9
V
3
V
25
V
VDD SECTION
IDD ST
Startup Current
VDD = VTH−ON - 0.1 V
IDD−OP
Operating Current
VDD = 14 V, Output Not Switching, RRI =
25 k
VTH−ON
Turn−On Threshold Voltage
VDD Rising
ΔVTH
UVLO Hysteresis
VDD−OVP
VDD OVP Threshold
ΔVDD−OVP
VDD OVP Hysteresis
tD−OVP
2
OPFC1~2 Disabled, IEA1~2 and SS Pull
Low
23
24
1
VDD OVP Debounce Time
V
80
s
OSCILLATOR (Note 3)
Sourcing Voltage on RI
RRI = 25 k
1.15
1.20
1.25
V
fOSC1
PFC Frequency Test Case 1
RRI = 25 k
30
32
34
kHz
fOSC2
PFC Frequency Test Case 2
RRI = 12.5 k
58
62
66
kHz
fDV
Voltage Stability
13 V ≤ VDD ≤ 22 V
2
%
fDT
Temperature Stability
2
%
VRI
ΔVIEA−SAW32
VIEA−SAW of PFC Frequency 32 kHz
RRI = 25 k
ΔVIEA−SAW64
VIEA−SAW of PFC Frequency 64 kHz
RRI = 12.5 k
DPFC−MAX
Maximum Duty Cycle
VIEA > 7 V
DPFC−MIN
Minimum Duty Cycle
VIEA < 1 V
94
5
V
5.15
V
97
%
0
%
fRANGE1
Frequency Range 1 (Notes 3, 4)
18
40
kHz
fRANGE2
Frequency Range 2 (Notes 3, 4)
55
75
kHz
tDEAD−MIN
Minimum Dead Time
600
RRI = 10.7 k
ns
INPUT−RANGE SETTING (VIR)
VVIR−H
HIGH Setting Level for High Voltage Input Range
RVIR = 500 k (VVIR = 5 V)
VVIR−L
LOW Setting Level for Low Voltage Input
Range or Full Voltage Input Range
VVIR = 0 V
IVIR
Sourcing Current of VIR Pin
3.5
7
V
10
1.5
V
13
A
PFC Soft−Start
ISS
Constant Current Output for Soft−Start
VSS
Maximum Voltage on SS
ISS−Discharge
Discharge Current of SS Pin
System Brown−in
22
A
6.8
Brownout, SAG, VCM1>4 V, RRI Open /
Short, OTP
V
60
A
VOLTAGE ERROR AMPLIFIER
VREF
AV
Gmv
Reference Voltage
PVO = GND, TJ = 25°C
Open-Loop Gain (Note 3)
Transconductance
VNONINV − VINV = 0.5 V, TJ = 25°C
IFBPFC−L
Maximum Source Current
VFBPFC = 2 V, VVEA = 3 V
IFBPFC−H
Maximum Sink Current
VFBPFC = 3 V, VVEA = 3 V
IBS
Input Bias Current Range
2.45
2.50
42
65
dB
100
S
40
50
−50
−1
IFBPFC−FL
Pull High Current for FBPFC
FBPFC Floating
VVEA-H
Output High Voltage on VVEA
VFBPFC = 2 V
VVEA-L
Output Low Voltage on VVEA
VFBPFC = 3 V
www.onsemi.com
6
5.7
2.55
V
A
−40
A
1
A
500
nA
6.0
V
0
0.15
V
FAN9672
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VOLTAGE ERROR AMPLIFIER
IVEA−DIS
Discharge Current
Brownout, RRI Open /Short, OTP, SAG
10
A
VVEA-OFF
Threshold Voltage for Low−Power Detection
When VVEA < VVEA−OFF, VOPFC1~2 are
Off & VIEA1~2 are Pulled Low
0.3
V
CURRENT ERROR AMPLIFIERS
Gmi
Transconductance
VNONINV = VINV, VIEA = 4 V,
VILIMIT > 0.6 V, TJ = 25°C
88
S
VOFFSET
Input Offset Voltage
VVEA = 0.45 V, RIAC=12 M,
VIAC = 311 V, VFBPFC = 2 V,
VVIR = 5 V, TJ = 25°C
0
mV
VIEA−H
Output High Voltage
VIEA−L
Output Low Voltage
6.8
0
IL
Sourcing Current
VNONINV − VINV, = +0.6 V,
VIEA = 1 V, VILIMIT >0.6 V
IH
Sinking Current
VNONINV − VINV, = -0.6 V,
VIEA = 6.5 V, VILIMIT > 0.6 V
AI
Open−Loop Gain (Note 3)
IIEA−LOW
IEA Pin Pull−Low Capability
7.0
35
50
−50
40
VIEA w 5 V
V
0.4
V
A
−35
50
A
dB
500
A
GAIN MODULATOR (Current Command Generator)
IAC
Input for AC Current (Notes 3, 5)
Multiplier Linear Range
BW
Bandwidth (Notes 3, 5)
IAC = 40 A
VRM
Gain Modulator Output (IMO* RM) Test
Cases
RM
Resistor of Gain Modulator Output
0
65
A
2
kHz
VIAC = 106.07 V, RIAC = 6 M,
VFBPFC = 2.25 V, VBIBO = 2 V,
VCM2 > 4.5 V, TJ = 25°C
0.490
V
VIAC = 120.21 V, RIAC = 6 M,
VFBPFC = 2.25 V, VBIBO = 2 V,
VCM2 > 4.5 V, TJ = 25°C
0.430
VIAC = 155.56 V, RIAC = 6 M,
VFBPFC = 2.25 V, VBIBO = 2 V,
VCM2 > 4.5 V, TJ = 25°C
0.327
VIAC = 311.13 V, RIAC = 12 M,
VFBPFC = 2.25 V, VBIBO = 2 V,
VCM2 > 4.5 V, VVIR > 3.5 V, TJ = 25°C
0.320
VIAC = 373.35 V, RIAC = 12 M,
VFBPFC = 2.25 V, VBIBO = 2 V,
VCM2 > 4.5 V, VVIR > 3.5 V, TJ = 25°C
0.260
RM = VRM /IMO
7.5
k
ILIMIT (Current Command Limit)
VRM−R
VRM−ILIMIT
IILIMIT
Range of Peak Value in Current Command (VILIMIT/4)
Current Command Limit Test Case
RILIMIT = 42 k, RRI = 25 k,
VRM−LIMIT = RILIMIT * IILIMIT/4
Sourcing Current of ILIMIT Pin
RRI = 25 k
0.2
0.8
V
0.504
V
49
A
RILIMIT2 = 30 k, RRI = 25 k,
CS1~2 > VILIMIT2
OPFC1 Disables, VIEA1~2 Pull Low
1.48
V
1.48
V
Sourcing Current for ILIMIT2 Pin
RRI = 25 k, TJ = 25°C
49.5
A
Leading−Edge Blanking Time of ILIMIT
of Each Channel
VDD = 15 V, OPFC Drops to 9 V
250
ns
250
ns
ILIMIT2 (CS1/CS2, Pulse−by−Pulse Current Limit)
VILIMIT2−CS1
Peak Current Limit Voltage Test Case
VILIMIT2−CS2
IILIMIT2
tPFC−BNK1
tPFC−BNK2
www.onsemi.com
7
FAN9672
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
200
400
ns
200
400
ns
3.8
4.0
4.2
V
V
ILIMIT2 (CS1/CS2, Pulse−by−Pulse Current Limit)
tPD1
tPD2
Propagation Delay to Output of Each
Channel
VILIMIT2−OPEN Threshold of ILIMIT2 Open−Circuit Protection
OPFC1~2 Disabled and VIEA1~3 Pull
Low
TriFault Detect™
VPFC−UVP
FBPFC Under−Voltage Protection
0.4
0.5
0.6
VPFC−OVP
FBPFC Over−Voltage Protection (OVP)
2.70
2.75
2.80
V
ΔVPFC−OVP
FBPFC OVP
200
250
300
mV
tFBPFC-OPEN
FBPFC Open Delay (Note 3)
tFBPFC−UVP
Under−Voltage Protection Debounce Time
VFBPFC = VPFC−UVP to FBPFC Open,
470 pF from FBPFC to GND
2
ms
50
s
PVO
VPVO
VPVO_DIS
Programmable Output Setting Range on PVO Pin
PVO Disable Voltage
0.3
3.5
V
PVO< VPVO_DIS
0.2
V
FBPFC Connected to VEA,
VPVO = 4 V
1.6
V
FBPFC Connected to VEA,
VPVO = 0.3 V
2.425
V
FBPFC Connected to VEA,
VPVO = 3.5 V
1.625
V
1
A
VVIR = 0 V, VIAC = 127.28 V,
RIAC = 6 M,
20.71
A
IGC−L2
VVIR = 0 V, VIAC = 311.13 V,
RIAC = 6 M,
51.86
A
IGC−HV
VVIR = 5 V, VIAC = 311.13 V,
RIAC = 12 M.
51.86
A
100
nA
VPVO−CLAMPH Low−clamp of FBPFC based on PVO
VFBPFC1
FBPFC Voltage Test Cases
VFBPFC2
IPVO−Discharge PVO Discharge Current
PVO Open
GAIN COMPENSATION (GC) SECTION (Note 6)
IGC−L1
Test Cases of Mirror Current of IAC on
GC Pin
IGC−OPEN
Pull High Current for GC−Pin Open
VGC−OPEN
GC−Pin Open Voltage
VGC > VGC−OPEN VIEA,
OPFC1&2 Blanking
2.85
3.00
3.15
V
87
k
INDUCTANCE SETTING (LS) Section (Note 6)
RLS
Acceptable Range of Inductance Setting
VLS−MIN
Voltage Difference between VFBPFC and
VGC on LS Pin
12
50
VFBPFC – VGC ≥ 0 V
mV
BROWN IN /OUT
VBIBO−FL
Threshold of Brown−out at VIR = LOW
Setting (Full AC−Input Range)
VVIR < 1.5 V, RIAC = 6 M
ΔVBIBO−F
Hysteresis
VBIBO > VBIBO−FL + △VBIBO−F,
Brown−in, Start SS
VBIBO−HL
Threshold of BO at VIR=HIGH Setting
(High AC−Input Range)
VVIR > 3.5 V, RIAC = 12 M
ΔVBIBO−H
Hysteresis
VBIBO > VBIBO−HL + △VBIBO−H,
Brown−in, Start SS
tUVP
Under−Voltage Protection Delay Time
www.onsemi.com
8
1.00
1.05
1.10
850
1.00
1.05
V
mV
1.10
V
700
mV
450
ms
FAN9672
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
SAG PROTECTION SECTION
VSAG
SAG Voltage of BIBO
1. VBIBO < VSAG & VRDY High for 33 ms,
or
2. VBIBO < VSAG & VRDY Low, Brownout,
tSAG−DT
SAG Debounce Time
VBIBO < VSAG & VRDY High
0.85
V
33
ms
100
nA
RLPK, VOLTAGE−SETTING RESISTANCE FOR PEAK DETECTOR
IRLPK−OPEN
Pull High Current for RLPK Open
VRLPK−OPEN
RLPK Open Voltage
RLPK Open
2.28
2.40
2.52
V
LPK, PEAK−DETECTOR OUTPUT (Note 7)
VLPK Output Test Cases
VIAC = 311 V, RIAC = 1 2M,
VVIR > 3.5 V, RLPK = 12.4 k,
TJ = 25°C
3.168
V
VLPK−H2
VIAC = 373 V, RIAC = 12 M,
VVIR > 3.5 V, RLPK = 12.4 k,
TJ = 25°C
3.80
V
VLPK−L1
VIAC = 127 V, RIAC = 6 M,
VVIR < 1.5 V, RLPK = 12.4 k,
TJ = 25°C
1.29
V
VLPK−L2
VIAC = 373 V, RIAC = 6 M,
VVIR < 1.5 V, RLPK = 12.4 k,
TJ = 25°C
3.80
V
VLPK−H1
VAC−OFF
AC OFF Threshold Voltage Test Case
VIAC = 373 V, RIAC = 12 M,
VVIR > 3.5V
After tAC−OFF VIEA Pull Low
32
V
VAC−ON
AC ON Threshold Voltage Test Case
VIAC = 373 V, RIAC = 12 M,
VVIR > 3.5 V
VAC−OFF
+26
V
CM1 SECTION
55
A
PFC Disable Voltage
ICM1 * RCM1 > 4 V
OPFC1~2 Disabled and IEA1~2 Pull
Low and SS Pull Low
4
V
1
Phase of OPFC1
When ICM1 * RCM1 < 4 V or Short
0
°
2
Phase of OPFC2 (Note 8)
ICM1
VCM1−disable
CM1 Sourcing Current
170
180
190
°
CM2 SECTION
ICM2
CM2 Sourcing Current
VCM2−disable
Channel−2 Disable Voltage
VCM2−range
Set VEA Unload Voltage
ICM2 * RCM2 > 4 V or CM2 Floating
OPFC2 Disables and IEA2 PulIs Low
55
A
4
V
0
3.8
V
2.5
V
RDY SECTION
Level of VFBPFC to Pull RDY High
VPVO = 0 V, Brown−in,
VFBPFC > VFB−RD
ΔVFB−RD−L
Hysteresis
VPVO = 0 V, VIR < 1.5 V
1.15
V
ΔVFB−RD−H
Hysteresis
VPVO = 0 V, VIR > 3.5 V
0.85
V
Pull High Input Impedance
TJ = 25°C
100
k
5.0
V
VFB−RD
ZRDY
VRDY−High
High Voltage of RDY
VRDY−Low
Low Voltage of RDY
2.3
4.8
2.4
Pull High Current = 1 mA
0.5
V
17
V
PFC OUTPUT DRIVER 1~2
VGATE−CLAMP Gate Output Clamping Voltage
VDD = 22 V
www.onsemi.com
9
13
15
FAN9672
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1.5
V
PFC OUTPUT DRIVER 1~2
VGATE−L
Gate Low Voltage
VDD = 15 V, IO = 100 mA
VGATE−H
Gate High Voltage
VDD = 13 V, IO = 100 mA
tr
Gate Rising Time
VDD = 15 V, CL = 4.7 nF,
VOPFC from 2 V to 9 V
70
ns
tf
Gate Falling Time
VDD = 15 V, CL = 4.7 nF,
VOPFC from 9 V to 2 V
60
ns
Over−Temperature Protection (Note 3)
140
°C
Hysteresis (Note 3)
30
°C
8
V
OTP
TOTP−ON
ΔTOTP
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This parameter, although guaranteed by design, is not 100% production tested.
4. The setting range of resistance at the RI pin is between 53.3 k and 10.7 k.
5. Frequency of AC input should be 3.5V respectively.
The current signal, IMO, is in the form of a full−wave
rectified sinusoid at twice of the line frequency. The gain
modulator forms the reference for the current loop and
ultimately controls the instantaneous current drawn from the
power line.
www.onsemi.com
11
FAN9672
acting as changing relative weighting, for the current
command. The relationship of CM and the gain of the slave
channel is shown in Figure 10. The level of CM set the
threshold of power level, representing by VVEA, for
reducing the current command for the slave PFC. The
FAN9672 starts to reduce the current command (IMO × RM)
for channel 2 by Gain2 from one to zero when the VVEA level
is lower than its CM level, as Figure 11 and Figure 12 show.
The output power of the slave channel is reduced in response
to reduction in current command. For example, when CM2
is set at 3 V and VVEA is less than the CM2 voltage, the
channel management block reduces the command for
channel 2 as:
High−power applications implies current values are high,
so the distance of layout trace between the current sense
resistors and the controller or power ground (negative of
output capacitor) to IC ground is important, as shown in
Figure 9. The longer trace and large current make the offset
voltage and ground bounce differ significantly for different
channels. Decreasing the deviation help balancing different
channels. Please check the layout guidance in application
notes AN−4164 or AN−4165.
VIN
VO
V gmi2) + I MO
Gate2
Gate1
VCS1
V
RCS1
RCS2
Differential
Sense Filter
Differential
Sense Filter
RM
G ain2
(eq. 2)
V IN
Gate2
ISENSE2
Close
CS1−
CS1+
CS2−
VO
Gate1
ISENSE1
CS2+
FAN9672
Command
Generator
GND
VO
Filter Ground
IC GND to Power ground
Voltage
Loop
V VEA
Current
Command
Gain1
100%
CM
Block
Gain2
0~100%
Current
Loop 1
Gate1
Current
Loop 2
Gate2
V
Figure 9. Current Balance Factors
Figure 10. Current Balance Factors
Interleaving
The FAN9672 controller is used to control two−channel
boost converters connected in parallel. The controller
operates in average−current mode and supports Continuous
Conduction Mode (CCM). Each channel affords
one−second the power when the system operates close to full
load or when channel management is disabled.
Parallel power processing increases the number of power
components, but the current rating of independent channels
is reduced, allowing power semiconductors with lower
current ratings to be applied.
The switches of the two boost converters are operated at
a 180° out−of−phase. The interleaving controller can reduce
the total ripple current of input. Simultaneously, the output
current ripple of each channel is evenly distributed and
sequentially rippled on the output capacitor, which can
extend the life of the capacitor.
V gmi+
Channel
Management
Without Channel
Management
0
V EA
VCM
V AC
I L1
time
V AC
I L2
Gain2 = 0
Channel Management/CM Control
0< Gain2 4 V, the
channel is disabled. To enable the channel, make VCM = 0 V,
as shown in Figure 15.
The CM pin of the slave should be connected with a switch
S2 to ground. One pin of MCU must read the VVEA signal to
determine when to turn on/off the slave channel. For
example, as shown in Figure 16, two thresholds, VP2−OFF−L
and VP2−OFF−H, are set in MCU program. When
VVEA < VP2−OFF−L, the slave PFC turns off. If
VVEA > VP2−OFF−H, the slave PFC turns on.
VCM−LIMIT (4V)
V VEA
time
0
V AC
IL
time
Figure 15. Channel Management by MCU
VAC
CS+ CS−
I L1
Channel
enable
signal
from MCU
Sample
& Hold
CM
gmi
I L2
PO
CM
V VEA
S
55uA
OSC
V P2−OFF−H
V P2−OFF−L
Gain
Modulator
MCUà S2
MCU Turn−Off Slaver
Figure 14. Channel Management by MCU
Figure 16. Channel Management by
External Signal from MCU
www.onsemi.com
13
FAN9672
When CM is accessed this way, behavior of each phase
will be as illustrated in Table 3 and Figure 17. When the
MCU disables channel 2 at mid−load ~ light load, only
channel 1 will be operated. Gain2 under this control method
switches between 100% and 0%.
Full load, all channel operation
I L2
I L1
Light load, only operation by channel 1
I L2
I L1
0°
180°
Figure 17. Phase Change under
External Signal Control
Table 3. PHASE CHANGE OF EXTERNAL SIGNAL CONTROL
Phase
(Disable Channel: VCM > 4 V, Enable Channel: VCM = 0 V)
External Signal Control
Channel 1
Channel 2
Heavy Load (All Channels Enabled)
0°
180°
Light Load (Channel 2)
0°
Disable (VCM2 > 4 V)
Disable All System
VCM1 > 4 V, All Channels Disabled
FUNCTIONAL DESCRIPTION
Internal Oscillator (RI)
VIN
VPFC
The Frequency of an internal oscillator is determined by
an external resistor, RRI, on the RI pin. The frequency of the
oscillator is given by eq. 3. The frequency can be freely set
in two ranges, 18 kHz ~ 40 kHz and 55 kHz~75 kHz. Setting
frequency between 40 kHz and 55 kHz is not allowed in
FAN9672.
f osc +
8
10 8
R RI
IL
RCS
(eq. 3)
Current−Control Loop of Boost Stage
RM
G ain2 + K
I AC
V EA
V LPK
2
RM
CM
C I2
Drive
Logic
Peak
Detecter
VEA
RV1
CV2
G ain2
(eq. 4)
Average value of sensed current, IL × RCS, is regulated to
the current command, IMO × RM. Gain2 is a gain between
0 ~ 1 when the channel management block is engaged for
the slave channels. Gain2 term is equal to one for channel 1.
CV1
C I1
IMO
IAC
LPK
IEA
R I1
RM
CM
RIAC
As shown in Figure 18, the two control loops for power
factor correction are a current−control loop and a
voltage−control loop. Based on the reference signal
obtained at the IAC pin, the error amplifier in
current−control loop regulates current signal as:
R CS + I MO
gmi
LPT
GC
IL
CS−
CS+
LS
OSC
OPFC
RI
R FB1+FB2
gmv
2.5V
PVO
FBPFC
R FB3
Figure 18. Gain Modulation Block
TriFault Detect
Voltage−Control Loop of Boost Stage
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN9672 brings TriFault Detect
technology. This feature monitors FBPFC for certain PFC
fault conditions.
In the case of a feedback path failure, the output of the PFC
can exceed operating limits. Should FBPFC go too low, too
The voltage−control loop regulates PFC output voltage by
using the internal error amplifier, Gmv, making voltage on
FBPFC same as the internal reference voltage, 2.5 V. It
stabilizes PFC output voltage and decreases 120−Hz ripple
on PFC output voltage.
www.onsemi.com
14
FAN9672
Differential Current Sensing (CS+, CS−)
high, or open, the TriFault Detect senses the fault and
terminates the PFC output drive.
TriFault Detect is an entirely internal circuit. It requires no
external components to perform its function.
Switching noise problems in interleaved PFC control is
more critical than on a single channel, especially for current
sensing. The FAN9672 uses a differential amplifier to
eliminate switching noise from other channels. The
FAN9672 has two groups of differential current−sensing
pins. The CSn+ and CSn− are the inputs of the internal
differential amplifiers. This makes the PFC more stable in
higher−power applications and eliminates switching noise
from other channels. As Figure 21 shows, ground bounce
can be decreased by a differential sense function.
PFC Over−Voltage Protection (OVP)
FAN9672 has an auto−restart OVP function. When the
feedback level, VFBPFC, reaches 2.75 V (reference level is
2.5 V), the PFC gate signal stops. The PFC gate signal
resumes when VFBPFC returns to 2.5 V.
PFC Brown In/Out (BIBO)
An internal AC Under−Voltage Protection (UVP)
comparator monitors the AC input information from VIN, as
shown in Figure 19. The OPFC is disabled when the VBIBO
is less than 1.05 V for 410 ms. If VBIBO is larger than 1.9 V
(VVIR < 1.5 V) or 1.75 V (VVIR > 3.5 V), the PFC stage is
enabled. The VIR pin is used to set the AC input range
according to Table 4.
Differential
Current Sense
Period
Period
Figure 21. Gate Drive Circuit
Table 4. BIBO SETTING OF VARIOUS AC INPUT
AC (V)
RVIR
Setting
(kW)
RIAC
Setting
(MW)
BIBO Level (V)
Full−Range
85 ∼ 264
10
6
85/75
HV−Single
180 ∼ 264
470
12
170/160
Input
Range
Linear Predict Function (GC & LC)
Current sense signal reflects inductor current only when
OPFC is on. The linear predict function is used to emulate
the behavior of inductor current when the OPFC is off.
Resistor on the LS pin is used to set equivalent inductance
value for the internal emulator. Resistor on the GC pin is
used to align sensed input voltage (IAC) and output voltage
(FBPFC) signals. Values of those resistors can be
determined by:
1.9V/1.7V (PFC brown−in threshold)
VIN
VBIBO
L PFC
R LS +
1.5
10 *9
R CS
(R FB1)R FB2)R FB3)
R FB3
(eq. 5)
1.05V (brownout protection trip point)
PFC runs
R GC +
Figure 19. VBIBO According to the PFC Operation
6 10 6
R FB1)R FB2)R FB3
(
)
R FB3
(eq. 6)
Care must be taken that RLS value need to be within
12~87 k.
PFC Gate Driver
For high−power applications, the switch device of the
system requires high driving current. The totem−pole circuit
shown in Figure 20 is recommended.
Current−Limit Protection
The FAN9672 includes three factors that limits current to
manage OCP and inductor saturation: VVEA limit, VILIMIT,
and VILIMIT2. The current-limit thresholds, VILIMIT1 and
VILIMIT2, are configurable through ILIMIT and ILIMIT2
pins.
VDD
SPFC
Power (Normal State)
In the normal case, average input power is controlled by
the command VVEA. When VVEA rises to 5.6 V, it is
internally clamped. Input power can’t increase further.
RCS
Figure 20. Gate Drive Circuit
www.onsemi.com
15
FAN9672
Current Limit 1 (Abnormal State)
The current command from the gain modulator is
K × IAC ×VVEA/VLPK2. In abnormal state, such as AC cycle
miss and recover in a short period, the VLPK has a delay
before returning to the original level. This delay makes the
current command increased. If the command is greater than
the limit clamp level, VILIMIT, current command will be
clamped, as shown in Figure 22 and Figure 23. The peak
current of this state can be used as the maximum current for
inductor design, assuring inductor is not saturated.
Non−Saturation
PFC
Command
Gmi+
5
A
C
VRM
B
Gain Modulator
I × RILIMIT
4
3
VILIMIT /4
Right design,
max power
limited by
VVEA
1.2V
RI
VCS.PK
VCS
Case1:
Max. Power (Normal),
VVEA−MAX “B” = 6 V
I
VILIMIT2 = Saturation Protection
V
Case2:
> Max. Power (Abnormal),
VVEA−MAX “B” = 6 V
AC cycle drop
VVEA = 6V, but “C” abnormal
short time, clamp by VILIMIT
Case3:
> Max. Power (Abnormal),
AC cycle drop, as left case,
but user uses wrong choke
can not afford current at Max.
mommand.
Right design at
abnormal test,
command from
Multiplier clamp
by V ILIMIT
Wrong design at
abnormal test, but
protect by V ILIMIT2
Figure 23. ILIMIT and ILIMIT2 Setting
ILIMIT
Programmable PFC Output Voltage (PVO)
RILIMIT
In some cases, decreasing the PFC output voltage can
improve efficiency of the PFC stage. The PVO pin is used
to program output voltage, as shown in Figure 24. This
function is controlled by an external voltage signal on PVO
pin from MCU or other source.
VPVO should be over 0.5 V and the relationship for VPVO
and VFBPFC is given by:
Figure 22. Current Command Limit by ILIMIT
Current Limit 2 (Saturation State)
Use 80% ~ 90% of the maximum current of the switch
device to serve as the saturation protection. VLIMIT2 is a
cycle−by−cycle limit.
V FBPFC + 2.5 V *
ƪ ƫ
V PVO
4
(eq. 7)
For instance, if PVO input is 1 V, RFB1+RFB2 = 3.7 M,
and RFB3 = 23.7 k, VFBPFB will be regulated to 2.25 V,
making PFC VO = 354 V.
www.onsemi.com
16
FAN9672
VPFC
VAC
VO
IL
IL
393V
External
Signal
(MCU)
PVO
gmv
FBPFC
2.5V
VIN−OFF = 1.25V (FR) /
354V
RCS
AC OFF
(AC Long Time Drop)
VIN−OK = 2.4V
1.55V (HV)
VFBPFC
RFB1
Brownout & PFC Soft
RDY Pull−Low Start
PFC Soft Start
VSS
VFBPFC
2.5V
VVEA
RFB2
2.25V
VRDY à MCU
VFBPFC
PVO
RFB3
1V
Second Power Stage working
Figure 26. When AC Drops for a Long Time
0V
Voltage Protection
VAC
Figure 24. Programmable PFC Output Voltage
IL
VIN−OK = 2.4V
RDY Function and AC Line Off/AC “SAG”
V IN−OFF = 1.25V (FR) /
The ready (RDY) function is used to signal the MCU that
the PFC stage is ready and the downstream power stage can
start to operate. When the feedback voltage on FBPFC rises
above 2.4 V, VRDY signal pulls HIGH as shown in Figure 25.
If the AC line is OFF (or AC signal drops for a long time),
the FAN9672 enters brown−out and VRDY pulls LOW to
indicate to the MCU that the power stage should stop, as
shown in Figure 26.
When the AC signal drops for only a short time (i.e. 1~1.5
AC cycles), brown−out is not triggered and VFBPFC may not
drop too much. In this case, RDY will not go LOW as shown
in Figure 27.
AC “sag” means the AC drops to a low level, such as
110 V / 220 V → 40 V. AC “missing” means the AC drops
to 0 V. If AC drops, the PFC attempts to transfer energy to
VO before VO drops to the 50% level. If AC is 0 V, the PFC
cannot transfer energy. If the level reaches 50%, the PFC
stops, and FAN9672 resets and waits for AC to return.
1.55V (HV)
VFBPFC
VSS
VVEA
VRDY à MCU
Soft−Start
Soft−start is combined with RDY pin operation, as
Figure 26 and Figure 27 show. During startup, the RDY pin
remains LOW until the PFC output voltage reaches 96% of
its nominal value. When the supply voltage of the
downstream converter is controlled by the RDY pin, the
PFC stage always starts with no load because the
downstream converter does not operate until the PFC output
voltage reaches the required level for the design.
Usually, the error amplifier output, VVEA, is saturated to
HIGH during startup because the actual output voltage is
less than the target value. VVEA remains saturated to HIGH
until the PFC output voltage reaches its target value. Once
the PFC output reaches its target value, the error amplifier
comes out of saturation. However, it takes several line cycles
for VVEA to drop to its proper value for output regulation,
which delivers more power to the load than required and
causes output voltage overshoot. To prevent output voltage
overshoot during startup caused by the saturation of error
amplifier, the FAN9672 clamps the error amplifier output
voltage (VEA) by the VSS value until PFC output reaches
96% of its nominal value.
IL
VREF
FBPFC
RDY
Second Power Stage working
Figure 27. When AC Drops Only Briefly
V PFC
R FB1 + FB2
AC Short Time Drop
PFC Soft Start
MCU
R FB3
FR: 2.4V/1.25V
HV: 2.4V/1.55V
Brown out
Figure 25. RDY Function to MCU
www.onsemi.com
17
FAN9672
Input Voltage Peak Detection
The relationship of VIN.PK to VLPK is shown in Figure 29.
The peak detection circuits recognizes the VIN information
from IAC. When recommended design values in Table 4 are
followed, RLPK pin sets the ratio of VIN to VLPK via a
resistor RRLPK as described in eq. 8. The target value of
VLPK is usually set as one percent (1%) of VIN_pk. The
maximum VLPK should not exceed 3.8 V when system
operation is at maximum AC input.
As in the below design example, assume the maximum
VIN.PK at 373 V (264 VAC), the relationship of
VIN.PK/ VLPK is 100, and VLPK = 3.73 V < 3.8 V.
The input AC peak voltage is sensed at the IAC pin.
Ideally, RMS value of the input voltage should be used for
feed−forward control in the gain modulator circuit. Since the
RMS value of the AC input voltage is directly proportional
to its peak, it is sufficient to find the peak instead of the
more−complicated and slower method of integrating the
input voltage over a half line cycle. The internal circuit of the
IAC pin works with peak detection on the input AC
waveform and output to the LPK pin for MCU use, as shown
in Figure 28.
One of the important benefits of this approach is that the
peak indicates the correct RMS value even at no load. At no
load, the HF filter capacitor at the input side of the boost
converter is not discharged around the zero−crossing of the
line waveform. Another notable benefit is that, during line
transients, when the peak exceeds the previously measured
value, the input−voltage feed−forward circuit can react
immediately without waiting for a valid integral value at the
end of the half−line period.
VIN / 100>VLPK +0.2V
Step−up tracking
V IN.PK
100
V LPK +
RIAC
IAC
t BLANK = 5 ms
No update after AC−OFF
RLPK
t BLANK = 5ms
RLPK
VLPK
VLPK
95%
tAC−OFF = 2.5 ms
IEA pull low
(eq. 8)
VIN
VIN /100
tUPDATE = 3.5ms
R RLPK
12.4k
LPK
Ratio
Peak
Detector
tAC −OFF =2 .5 ms
IEA pull low
VAC −OFF =10%*V LPK
Figure 29. Relationship of VIN.PK to VLPK
VAC−ON =20%*VLPK
Figure 28. Waveform of LPK Function
www.onsemi.com
18
FAN9672
Typical Performance Characteristics
Typical characteristics are provided at VDD = 15 V unless otherwise noted.
Figure 30. IDD−OP vs. Temperature
Figure 31. VDD−OVP vs. Temperature
Figure 32. fosc vs. Temperature
Figure 33. VRI vs. Temperature
Figure 35. VBIBO−FH vs. Temperature
Figure 34. VBIBO−FL vs. Temperature
Figure 36. VBIBO−HL vs. Temperature
Figure 37. VBIBO−HH vs. Temperature
www.onsemi.com
19
FAN9672
Typical Performance Characteristics (continued)
Typical characteristics are provided at VDD = 15 V unless otherwise noted.
Figure 38. VFBPFC−RD vs. Temperature
Figure 39. GmV−MAX vs. Temperature
Figure 40. VOFFSET vs. Temperature
Figure 41. GMI vs. Temperature
Figure 42. VPFC−OVP vs. Temperature
Figure 43. VREF vs. Temperature
Figure 44. ILIMIT vs. Temperature
Figure 45. VLIMIT vs. Temperature
www.onsemi.com
20
FAN9672
Typical Performance Characteristics (continued)
Typical characteristics are provided at VDD = 15 V unless otherwise noted.
Figure 46. ILIMIT2 vs. Temperature
Figure 47. VILIMIT2−CS1 vs. Temperature
Figure 48. tPFC−BNK vs. Temperature
Figure 49. VRLPK−OPEN vs. Temperature
Figure 50. VLPK−H1 vs. Temperature
Figure 51. VLPK−H2 vs. Temperature
www.onsemi.com
21
FAN9672
Table 5. TYPICAL APPLICATION CIRCUIT
Application
Output Power
Input Voltage
Output Voltage/Output Current
Single−Stage, Two−Channel PFC
3400 W
180 ∼ 264 VAC
393 V/8.48 A
Features
• 180 VAC ~264 V, Two−Channel PFC Using FAN9672
• Switch−Charge Technique of Gain Modulator for Better
PF and Lower THD
• 40 kHz Low Switching Frequency Operation with IGBT
• Over−Voltage Protection (OVP), Under−Voltage
Protection (UVP), Over−Current Protection (ILIMIT),
Inductor Saturation Protection (ILIMIT2)
* D BP1, 2
1N5406
RB1
CB
1 F
LPFC1
100 H
DPFC1
FFH30S60STU
LPFC2
100 H
DPFC2
FFH30S60STU
VPFC
RFB1
2.2 M
SPFC1~2
FGH40N60SMDF
RFB2
1.5 M
RA1
6 M
RB1
1 M
VDD
VDD
RA2
6 M
RB2
1 M
CFB
470 pF
Rsen2
15 m
Rsen1
15 m
RFB3
23.7 k
RF1~2
470
CF1
2.2 nF
CF2
2.2 nF
RB3
200 k
OPFC1 CS1− CS1+
IAC
OPFC2 CS2− CS2+
FBPFC
BIBO
CB1
CB2
47 nF 0.47 F
RB4
16.2 k
CSS 0.47 F
CRLPK10 nF
VEA
SS
RLPK
IEA1
LS
IEA2
CIC12
CIC122
RIC21
FAN9672
RLS 43 k
CGC 470 pF
RVC1
RIC11
RLPK12.1 k
CLS 470 pF
CVC2 100 nF
GC
CVC1
1 F
75 k
100 pF
CIC11
17.4 k 1 nF
CIC21
17.4 k 1 nF
VDD
CVDD 22 F
RGC 38.2 k
10 nF
CILIMIT2
ILIMIT2
VIR
CVIR 1 nF
RILIMIT2 10 k
RVIR
LPK
MCU
CLPK
0.1 F
CM1
CM2
PVO
RDY
GND
RI
RLPK
4.7 k
DC Setting Level MCU signal
(DC)
MCU/
Sec. Stage
(PFC Ready)
Figure 52. Schematic of Design Example
www.onsemi.com
22
ILIMIT
RRI
CILIMIT RILIMIT
20 k 10 nF 30 k
470
Standby
Power
COUT
2040 F
FAN9672
• Switching Frequency: 40 kHz
• VFBPFC for RDY: 2.4 V/1.55 V (96% / 62%)
• RIAC: 12 M
Specification
•
•
•
•
•
•
VDD Maximum Rating: 20 V
VDD OVP: 24 V
VCC UVLO: 10.3 V/12.8 V
PVO: 0 V ∼ 1 V
PFC Soft−Start: CSS = 0.47 F
Brown−In/Out: 170 V/160 V
Inductor Schematic Diagram
• Switching Frequency: 40 kHz
• Bobbin: 7 Pins
Figure 53. Inductor Schematic Diagram
Table 6. WINDING SPECIFICATION
No.
Winding
Pin (S " F)
Wire
Turns
Winding Method
N1
1 → 6, 7
0.2 × 35 *1
25
Solenoid Winding
1
2
Insulation: Polyester Tape t = 0.025 mm, 2 Layer
3
Copper−Foil 1.2T to PIN4, 5
Table 7. MOSFET AND DIODE REFERENCE SPECIFICATION
IGBT’s
Voltage Rating
600 V (IGBT)
FGH40N60SMDF
Boost Diodes
600 V
FFH30S60STU
Typical Performance
Table 8. EFFICIENCY
25% Load
50% Load
75% Load
100% Load
180 V/50 Hz
96.31
96.93
96.60
96.41
220 V/50 Hz
97.01
97.34
97.33
97.17
264 V/50 Hz
97.76
97.92
97.92
97.77
25% Load
50% Load
75% Load
100% Load
180 V/50 Hz
0.9546
0.9856
0.9917
0.9955
220 V/50 Hz
0.9397
0.9694
0.9780
0.9879
264 V/50 Hz
0.8402
0.9158
0.9337
0.9500
Table 9. POWER FACTOR
www.onsemi.com
23
FAN9672
Table 10. TOTAL HARMONIC DISTORTION
25% Load
50% Load
75% Load
100% Load
180 V/50 Hz
14.51
10.98
8.87
6.96
220 V/50 Hz
20.12
17.24
15.30
11.87
264 V/50 Hz
50.52
36.86
33.11
29.26
System Design Precautions
• Pay attention to the inrush current when AC input is first
•
•
connected to the boost PFC convertor. It is recommended
to use NTC and a parallel connected relay circuit to reduce
inrush current.
Add bypass diode to provide a path for inrush current
when PFC start up.
The PFC stage is normally used to provide power to a
downstream DC−DC or inverter. It’s recommend that
•
downstream power stage is enabled to operate at full load
once the PFC output voltage has reaches a level close to
the specified steady−state value.
The PVO function is used to change the output voltage of
PFC, VPFC. The VPFC should be kept at least 25 V higher
than VIN.
www.onsemi.com
24
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LQFP−32, 7x7
CASE 561AB−01
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON30893E
32 LEAD LQFP, 7X7
DATE 19 JUN 2008
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
www.onsemi.com
1
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
