ON Semiconductor
Is Now
To learn more about onsemi™, please visit our website at
www.onsemi.com
onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
N-Channel PowerTrench® MOSFET
100V, 61A, 16mΩ
Applications
• DC/DC Converters and Off-line UPS
Features
• Distributed Power Architectures and VRMs
• r DS(ON) = 14mΩ (Typ.), VGS = 10V, ID = 61A
• Primary Switch for 24V and 48V Systems
• Qg(tot) = 41nC (Typ.), VGS = 10V
• High Voltage Synchronous Rectifier
• Low Miller Charge
• Direct Injection / Diesel Injection Systems
• Low QRR Body Diode
• 42V Automotive Load Control
• UIS Capability (Single Pulse and Repetitive Pulse)
• Electronic Valve Train Systems
• Qualified to AEC Q101
• RoHS Compliant
Formerly developmental type 82769
DRAIN
(FLANGE)
D
GATE
G
SOURCE
S
TO-263AB
FDB SERIES
MOSFET Maximum Ratings TC = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
61
A
Continuous (TC = 100oC, VGS = 10V)
43
A
9
A
Continuous (Tamb = 25oC, VGS = 10V) with RθJA = 43oC/W)
Pulsed
E AS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
182
mJ
Power dissipation
150
W
Derate above 25oC
1.0
W/oC
Operating and Storage Temperature
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-263
RθJA
Thermal Resistance Junction to Ambient TO-263
RθJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
(Note 2)
1.0
o
C/W
62
o
C/W
43
o
C/W
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/
All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
©2008 Semiconductor Components Industries, LLC.
September-2017, Rev 1
Publication Order Number:
FDB3652-F085/D
FDB3652-F085 N-Channel PowerTrench® MOSFET
FDB3652-F085
Device Marking
FDB3652
Device
FDB3652-F085
Package
TO-263AB
Reel Size
330mm
Tape Width
24mm
Quantity
800 units
Electrical Characteristics TC = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
100
-
-
-
V
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 80V
VGS = 0V
TC= 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 61A, VGS = 10V
-
0.014
0.016
ID = 30A, VGS = 6V
-
0.018
0.026
ID = 61A, VGS = 10V,
TJ = 175oC
-
0.035
0.043
-
2880
-
pF
-
390
-
pF
-
100
-
pF
41
53
nC
-
5
6.5
nC
-
15
-
nC
-
10
-
nC
-
10
-
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
VGS = 0V to 2V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 50V
ID = 61A
Ig = 1.0mA
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
146
ns
td(ON)
Turn-On Delay Time
-
12
-
ns
-
85
-
ns
-
26
-
ns
tr
Rise Time
td(OFF)
Turn-Off Delay Time
tf
Fall Time
-
45
-
ns
tOFF
Turn-Off Time
-
-
107
ns
V
VDD = 50V, ID = 61A
VGS = 10V, RGS = 6.8Ω
Drain-Source Diode Characteristics
ISD = 61A
-
-
1.25
ISD = 30A
-
-
1.0
V
Reverse Recovery Time
ISD = 61A, dISD/dt = 100A/µs
-
-
62
ns
Reverse Recovered Charge
ISD = 61A, dISD/dt = 100A/µs
-
-
45
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting T J = 25°C, L = 0.228mH, IAS = 40A.
2: Pulse Width = 100s
www.onsemi.com
2
FDB3652-F085 N-Channel PowerTrench® MOSFET
Package Marking and Ordering Information
1.2
75
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
50
25
0.2
0
0
0
25
50
75
100
150
125
175
25
50
75
TC , CASE TEMPERATURE (o C)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TC = 25oC
IDM, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
50
10-5
10-4
10-3
10-2
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
www.onsemi.com
3
10-1
100
101
FDB3652-F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1000
500
If R = 0
tAV = (L)(I AS)/(1.3*RATED BVDSS - VDD)
If R ¼ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
10µs
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
DC
0.1
1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
200
0.1
1
tAV, TIME IN AVALANCHE (ms)
0.01
10
NOTE: Refer to ON Semiconductor Application Notes AN7514 and
AN7515
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching
Capability
125
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
75
TJ = 175o C
50
o
o
TJ = 25 C
VGS = 7V
100
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
100
125
TJ = -55 C
VGS = 6V
75
TC = 25oC
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25
25
VGS = 5V
0
0
3
4
5
6
VGS , GATE TO SOURCE VOLTAGE (V)
7
0
Figure 7. Transfer Characteristics
4
Figure 8. Saturation Characteristics
20
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE(mΩ)
1
2
3
VDS , DRAIN TO SOURCE VOLTAGE (V)
18
VGS = 6V
16
14
VGS = 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
1.0
0.5
VGS = 10V, I D = 61A
12
0
0
20
40
ID, DRAIN CURRENT (A)
60
Figure 9. Drain to Source On Resistance vs Drain
Current
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
www.onsemi.com
4
200
FDB3652-F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
1.4
1.2
VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
1.0
0.8
0.6
0.4
-80
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
-80
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
10
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
C, CAPACITANCE (pF)
-40
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
5000
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 61A
ID = 30A
2
0
40
0.1
1.0
0.9
-40
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
1000
1.1
100
0
10
20
30
Qg, GATE CHARGE (nC)
40
50
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
www.onsemi.com
5
FDB3652-F085 N-Channel PowerTrench® MOSFET
Typical Characteristics TC = 25°C unless otherwise noted
VDS
BVDSS
tP
L
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDD
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
+
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
10%
Figure 20. Switching Time Waveforms
www.onsemi.com
6
FDB3652-F085 N-Channel PowerTrench® MOSFET
Test Circuits and Waveforms
RθJA = 26.51+ 19.84/(0.262+Area) EQ.2
RθJA = 26.51+ 128/(1.69+Area) EQ.3
60
RθJA (o C/W)
(T
–T )
JM
A
P D M = ----------------------------R θ JA
80
40
(EQ. 1)
In using surface mount devices such as the TO-263
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
20
0.1
1
10
(0.645)
(6.45)
AREA, TOP COPPER AREA in2 (cm2 )
(64.5)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
ON Semiconductor provides thermal information to assist
the designer’s preliminary application evaluation. Figure
21 defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000
seconds of steady state power with no air flow. This graph
provides the necessary information for calculation of the
steady state junction temperature or power dissipation.
Pulse applications can be evaluated using the ON
Semiconductor device Spice thermal model or manually
utilizing the normalized maximum transient thermal
impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area
defined in inches square and equation 3 is for area in
centimeter square. The area, in square inches or square
centimeters is the top copper area including the gate and
source pads.
R
θ JA
19.84
( 0.262 + Area )
= 26.51 + -------------------------------------
(EQ. 2)
Area in Iches Squared
R
θ JA
128
( 1.69 + Area )
= 26.51 + ----------------------------------
(EQ. 3)
Area in Centimeter Squared
www.onsemi.com
7
FDB3652-F085 N-Channel PowerTrench® MOSFET
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
Ebreak 11 7 17 18 108.2
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
DRAIN
2
5
EVTEMP
RGATE + 18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
Lgate 1 9 7.16e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 2.29e-9
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
RLgate 1 9 71.6
RLdrain 2 5 10
RLsource 3 7 22.9
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
17
18
RVTEMP
S2B
13
CB
6
8
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.7e-3
Rgate 9 20 1.06
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 6.5e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
15
14
13
S1B
CA
RBREAK
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*150),7))}
.MODEL DbodyMOD D (IS=1.5E-11 N=1.06 RS=2.5e-3 TRS1=2.4e-3 TRS2=1.1e-6
+ CJO=1.9e-9 M=5.8e-1 TT=2.5e-8 XTI=3.9)
.MODEL DbreakMOD D (RS=2.7e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=7e-10 IS=1e-30 N=10 M=0.58)
.MODEL MmedMOD NMOS (VTO=3.6 KP=5.5 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06)
.MODEL MstroMOD NMOS (VTO=4.3 KP=110 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.06e1 RS=.1)
.MODEL RbreakMOD RES (TC1=1.05e-3 TC2=1e-6)
.MODEL RdrainMOD RES (TC1=1.7e-2 TC2=3.2e-5)
.MODEL RSLCMOD RES (TC1=1e-3 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-5.3e-3 TC2=-1.2e-5)
.MODEL RvtempMOD RES (TC1=-3.3e-3 TC2=1.3e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-8 VOFF=-5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5 VOFF=-8)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1 VOFF=0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.5 VOFF=-1)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
www.onsemi.com
8
FDB3652-F085 N-Channel PowerTrench® MOSFET
PSPICE Electrical Model
.SUBCKT FDP3652 2 1 3 rev March 2002
Ca 12 8 1.1e-9
Cb 15 14 1.1e-9
Cin 6 8 2.8e-9
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
spe.ebreak n11 n7 n17 n18 = 108.2
spe.eds n14 n8 n5 n8 = 1
GATE
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LGATE
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
LSOURCE
7
RSOURCE
i.it n8 n17 = 1
RLSOURCE
S1A
l.lgate n1 n9 = 7.16e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 2.29e-9
res.rlgate n1 n9 = 71.6
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 22.9
DBREAK
50
-
12
S2A
13
8
CA
15
14
13
S1B
RBREAK
17
18
RVTEMP
S2B
13
CB
6
8
VBAT
5
8
EDS
-
IT
14
+
+
EGS
19
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.05e-3,tc2=1e-6
res.rdrain n50 n16 = 5.7e-3, tc1=1.7e-2,tc2=3.2e-5
res.rgate n9 n20 = 1.06
res.rslc1 n5 n51 = 1e-6, tc1=1e-3,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 6.5e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-5.3e-3,tc2=-1.2e-5
res.rvtemp n18 n19 = 1, tc1=-3.3e-3,tc2=1.3e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/150))** 7))
}
}
www.onsemi.com
9
SOURCE
3
FDB3652-F085 N-Channel PowerTrench® MOSFET
SABER Electrical Model
REV March 2002
template FDP3652 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=1.5e-11,nl=1.06,rs=2.5e-3,trs1=2.4e-3,trs2=1.1e-6,cjo=1.9e-9,m=5.8e-1,tt=2.5e-8,xti=3.9)
dp..model dbreakmod = (rs=2.7e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=7e-10,isl=10e-30,nl=10,m=0.58)
m..model mmedmod = (type=_n,vto=3.6,kp=5.5,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=110,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3,kp=0.03,is=1e-30, tox=1,rs=.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-8,voff=-5)
LDRAIN
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-5,voff=-8)
DRAIN
2
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1,voff=0.5)
10
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.5,voff=-1)
RLDRAIN
RSLC1
c.ca n12 n8 = 1.1e-9
51
c.cb n15 n14 = 1.1e-9
RSLC2
c.cin n6 n8 = 2.8e-9
ISCL
th
JUNCTION
FDP3652
CTHERM1 TH 6 1e-2
CTHERM2 6 5 1.5e-2
CTHERM3 5 4 2e-2
CTHERM4 4 3 2.1e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 TL 9e-2
RTHERM1
CTHERM1
6
RTHERM1 TH 6 2.7e-2
RTHERM2 6 5 2.8e-2
RTHERM3 5 4 7.8e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 2.7e-1
RTHERM6 2 TL 2.87e-1
CTHERM2
RTHERM2
5
SABER Thermal Model
SABER thermal model FDP3652
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =1e-2
ctherm.ctherm2 6 5 =1.5e-2
ctherm.ctherm3 5 4 =2e-2
ctherm.ctherm4 4 3 =2.1e-2
ctherm.ctherm5 3 2 =2.2e-2
ctherm.ctherm6 2 tl =9e-2
CTHERM3
RTHERM3
4
CTHERM4
RTHERM4
3
rtherm.rtherm1 th 6 =2.7e-2
rtherm.rtherm2 6 5 =2.8e-2
rtherm.rtherm3 5 4 =7.8e-2
rtherm.rtherm4 4 3 =9e-2
rtherm.rtherm5 3 2 =2.7e-1
rtherm.rtherm6 2 tl =2.87e-1
}
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
www.onsemi.com
10
CASE
FDB3652-F085 N-Channel PowerTrench® MOSFET
SPICE Thermal Model
REV 23 March 2002
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
❖
© Semiconductor Components Industries, LLC
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
www.onsemi.com
工商网监
湘ICP备2023018690号
