FDH038AN08A1

MOSFET – N-Channel, POWERTRENCH 75 V, 80 A, 3.8 mW FDH038AN08A1 Features • • • • • • www.onsemi.com RDS(ON) = 3.5 mW (Typ.), VGS = 10 V, ID = 80 A Qg (tot) = 125 nC (Typ.), VGS = 10 V Low Miller Charge Low Qrr Body Diode UIS Capability (Single Pulse and Repetitive Pulse) This Device is Pb−Free and is RoHS Compliant VDSS RDS(ON) MAX ID MAX 75 V 3.8 mW 80 A D Applications • Synchronous Rectification for ATX / Server / Telecom PSU • Battery Protection Circuit • Motor Drives and Uninterruptible Power Supplies G S G D S TO−247−3 CASE 340CK MARKING DIAGRAM $Y&Z&3&K FDH 038AN08A1 $Y &Z &3 &K FDH038AN08A1 = ON Semiconductor Logo = Assembly Plant Code = Data Code (Year & Week) = Lot = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2003 December, 2019 − Rev. 3 1 Publication Order Number: FDH038AN08A1/D FDH038AN08A1 MOSFET MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted) Symbol Value Unit VDSS Drain to Source Voltage 75 V VGS Gate to Source Voltage ±20 V − Continuous (TC < 158°C, VGS = 10 V) 80 A − Continuous (TA = 25°C, VGS = 10 V, RqJA = 30 °C/W) 22 ID ID Parameter Drain Current Drain Current − Pulsed Figure 4 A EAS Single Pulse Avalanche Energy (Note 1) 1.17 J PD Power Dissipation 450 W 3.0 W/°C −55 to +175 °C (TC = 25°C) − Derate Above 25°C TJ, TSTG Operating and Storage Temperature Range Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 0.65 mH, IAS = 60 A. THERMAL CHARACTERISTICS Symbol Parameter RqJC Thermal Resistance, Junction to Case, Max. TO−247 RqJA Thermal Resistance, Junction to Ambient, Max. TO−247 Value Unit 0.33 _C/W 30 _C/W PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity FDH038AN08A1 FDH038AN08A1 TO−247 Tube N/A 30 Units www.onsemi.com 2 FDH038AN08A1 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V IDSS Zero Gate Voltage Drain Current VDS = 60 V, VGS = 0 V IGSS Gate to Source Leakage Current BVDSS 75 V 1 mA VDS = 60 V, VGS = 0 V, TC = 150_C 250 VGS = ±20 V ±100 nA 4.0 V W ON CHARACTERISTICS VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA 2.0 RDS(ON) Drain to Source On Resistance ID = 80 A, VGS = 10 V 0.0035 0.0038 ID = 40 V, VGS = 6 V 0.0047 0.0071 ID = 80 A, VGS = 10 V, Tj = 175 °C 0.0074 0.008 VDS = 25 V, VGS = 0 V, f = 1 MHz 8665 pF DYNAMIC CHARACTERISTICS CISS Input Capacitance COSS Output Capacitance 1320 pF CRSS Reverse Transfer Capacitance 340 pF Qg(TOT) Total Gate Charge at 10 V VGS = 0 V to 10 V, VDD = 40 V, ID = 80 A, Ig = 1.0 mA 125 160 nC Qg(TH) Threshold Gate Charge VGS = 0 V to 2 V, VDD = 40 V, ID = 80 A, Ig = 1.0 mA 17 22 nC Qgs Gate to Source Gate Charge VDD = 40 V, ID = 80 A, Ig = 1.0 mA 57 nC Qgs2 Gate Charge Threshold to Plateau 42 nC Qgd Gate to Drain “Miller” Charge 30 nC SWITCHING CHARACTERISTICS (VGS = 10 V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time VDD = 40 V, ID = 80 A, VGS = 10 V, RGS = 2.4 W 345 ns 88 ns Rise Time 141 ns Turn-Off Delay Time 232 ns Fall Time 126 ns Turn-Off Time 530 ns ISD = 80 A 1.25 V ISD = 40 A 1 V Reverse Recovery Time ISD = 75 A, dlSD/dt = 100 A/ms 50 ns Reverse Recovered Charge ISD = 75 A, dlSD/dt = 100 A/ms 65 nC DRAIN−SOURCE DIODE CHARACTERISTICS VSD trr QRR Source to Drain Diode Voltage Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 FDH038AN08A1 TYPICAL CHARACTERISTICS 280 1.0 240 ID, DRAIN CURRENT (A) 1.2 0.8 0.6 0.4 0.2 CURRENT LIMITED BY PACKAGE 200 160 120 80 40 VGS = 10V 0 0 0 25 50 75 100 125 150 175 25 50 75 100 125 150 TC, CASE TEMPERATURE (oC) TC , CASE TEMPERATURE ( oC) ZQJC, NORMALIZED THERMAL IMPEDANCE Figure 1. Normalized Power Dissipation vs. Ambient Temperature 2 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature RQJA = 30C/W DUTY CYCLE − DESCENDING ORDER 1 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: 1/t 2 D=t T =P PEAK J DM x ZQJC x RQJC + TC SINGLE PULSE 0.01 10−5 10−4 10−3 10−2 10−1 t, RECTANGULAR PULSE DURATION (s) 100 101 Figure 3. Normalized Maximum Transient Thermal Impedance 3000 IDM, PEAK CURRENT (A) POWER DISSIPATION MULTIPLIER (TC = 25°C unless otherwise noted) TC = 25oC FOR TEMPERATURES ABOVE 25o C DERATE PEAK TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1000 CURRENT AS FOLLOWS: I = I25 VGS = 10V 175 − TC 150 100 50 10−5 10−4 10−3 10−2 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.onsemi.com 4 10−1 100 101 FDH038AN08A1 TYPICAL CHARACTERISTICS (Continued) (TC = 25°C unless otherwise noted) NOTE: 2000 500 IAS, AVALANCHE CURRENT (A) 10 ms 1000 ID, DRAIN CURRENT (A) 100 ms 100 1ms 10ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) 1 DC SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 0.1 Refer to ON Semiconductor Application Notes AN−7514 and AN−7515 If R = 0 tAV = (L)(I AS)/(1.3*RATED BVDSS − VDD) If R  0 tAV = (L/R)ln[(I AS*R)/(1.3*RATED BV DSS − VDD) +1] 100 STARTING TJ = 25oC 10 STARTING TJ = 150oC 1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.01 100 Figure 5. Forward Bias Safe Operating Area 160 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX VDD = 15V VGS = 10V 120 o TJ = 175 C 80 TJ = −55oC TJ = 25oC 40 0 VGS = 7V 120 VGS = 6V VGS = 5V 80 40 TC = 25oC PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics 2.5 6 VGS = 6V 5 4 VGS = 10V 3 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 2.0 1.5 1.0 VGS = 10V, ID = 80A 0.5 2 0 20 40 60 1.5 Figure 8. Saturation Characteristics NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (mW) 100 Figure 6. Unclamped Inductive Switching Capability ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 160 0.1 1 10 tAV, TIME IN AVALANCHE (ms) −80 80 ID, DRAIN CURRENT (A) Figure 9. Drain to Source On Resistance vs Drain Current −40 0 40 80 120 160 T J, JUNCTION TEMPERATURE (oC) 200 Figure 10. Normalized Drain to Source On Resistance vs. Junction Temperature www.onsemi.com 5 FDH038AN08A1 TYPICAL CHARACTERISTICS (Continued) (TC = 25°C unless otherwise noted) 1.4 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250 mA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 0.4 0.2 ID = 250 mA 1.1 1.0 0.9 −80 −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (o C) 200 −80 Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) CISS = CGS + C GD C, CAPACITANCE (pF) 10000 COSS^ CDS + CGD 1000 CRSS = CGD VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 20000 −40 VDD = 40V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A 2 0 0 75 Figure 13. Capacitance vs. Drain to Source Voltage 25 50 75 Qg, GATE CHARGE (nC) 100 Figure 14. Gate Charge Waveforms for Constant Gate Currents www.onsemi.com 6 125 FDH038AN08A1 TEST CIRCUITS AND WAVEFORMS VDS L VARY tp TO OBTAIN REQUIRED PEAK IAS RG + DUT VGS 0V tp − VDD IAS 0.01 W Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS L VGS + DUT − VDD Ig(REF) Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS RL + VGS − VDD DUT RGS VGS Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms www.onsemi.com 7 FDH038AN08A1 PSPICE Electrical Model .SUBCKT FDH038AN08A1 2 1 3 ; rev January 2003 CA 12 8 1.0e−9 Cb 15 14 3.1e−9 Cin 6 8 8.22e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 84.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 4.81e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 4.63e−9 RLgate 1 9 48.1 RLdrain 2 5 10 RLsource 3 7 46.3 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2.0e−4 Rgate 9 20 20 RSLC1 5 51 RSLCMOD 1.0e−6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 2.6e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*300),10))} .MODEL DbodyMOD D (IS=2.4E−11 N=1.02 RS=1.65e−3 TRS1=3.2e−3 TRS2=2.0e−7 + CJO=6.0e−9 M=5.6e−1 TT=2.38e−8 XTI=3.9) .MODEL DbreakMOD D (RS=1.5e−1 TRS1=1.0e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=1.5e−9 IS=1.0e−30 N=10 M=0.47) .MODEL MmedMOD NMOS (VTO=3.2 KP=1.5 IS=1.0e−30 N=10 TOX=1 L=1u W=1u RG=20) .MODEL MstroMOD NMOS (VTO=3.95 KP=235 IS=1.0e−30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.73 KP=0.02 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=200 RS=.01) .MODEL RbreakMOD RES (TC1=1.05e−3 TC2=−9.0e−7) .MODEL RdrainMOD RES (TC1=1.8e−2 TC2=2.2e−4) .MODEL RSLCMOD RES (TC1=2.0e−3 TC2=1.0e−5) www.onsemi.com 8 FDH038AN08A1 .MODEL RsourceMOD RES (TC1=5.0e−3 TC2=1.0e−6) .MODEL RvthresMOD RES (TC1=−4.2e−3 TC2=−1.8e−5) .MODEL RvtempMOD RES (TC1=−4.5e−3 TC2=2.0e−6) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4 VOFF=−1.5) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.5 VOFF=−4) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−0.5 VOFF=0.5) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=0.5 VOFF=−0.5) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. Figure 21. PSPICE Electrical Model www.onsemi.com 9 FDH038AN08A1 SABER Electrical Model REV January 2003 template FDH038AN08A1 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=2.4e−11,nl=1.02,rs=1.65e−3,trs1=3.2e−3,trs2=2.0e−7,cjo=6.0e−9,m=5.6e−1,tt=2.38e−8,xti=3.9) dp..model dbreakmod = (rs=1.5e−1,trs1=1.0e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=1.5e−9,isl=10e−30,nl=10,m=0.47) m..model mmedmod = (type=_n,vto=3.2,kp=1.5,is=1e−30, tox=1) m..model mstrongmod = (type=_n,vto=3.95,kp=235,is=1.0e−30, tox=1) m..model mweakmod = (type=_n,vto=2.73,kp=0.02,is=1.0e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−4,voff=−1.5) sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−1.5,voff=−4) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−0.5,voff=0.5) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=0.5,voff=−0.5) c.ca n12 n8 = 1.0e−9 c.cb n15 n14 = 3.1e−9 c.cin n6 n8 = 8.22e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 84.9 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 4.81e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 4.63e−9 res.rlgate n1 n9 = 48.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 46.3 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.05e−3,tc2=−9.0e−7 res.rdrain n50 n16 = 2.0e−4, tc1=1.8e−2,tc2=2.2e−4 res.rgate n9 n20 = 20 res.rslc1 n5 n51 = 1e−6, tc1=2.0e−3,tc2=1.0e−5 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 2.6e−3, tc1=5.0e−3,tc2=1.0e−6 res.rvthres n22 n8 = 1, tc1=−4.2e−3,tc2=−1.8e−5 res.rvtemp n18 n19 = 1, tc1=−4.5e−3,tc2=2.0e−6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod www.onsemi.com 10 FDH038AN08A1 v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/300))** 10)) } } Figure 22. SABER Electrical Model www.onsemi.com 11 FDH038AN08A1 SPICE Thermal Model th JUNCTION REV 23 January 2003 FDH038AN08A1T CTHERM1 TH 6 5.5e−3 CTHERM2 6 5 6.0e−3 CTHERM3 5 4 7.4e−3 CTHERM4 4 3 7.65e−3 CTHERM5 3 2 5.85e−2 CTHERM6 2 TL 6.0e−1 RTHERM1 RTHERM1 TH 6 9.0e−3 RTHERM2 6 5 2.08e−2 RTHERM3 5 4 2.28e−2 RTHERM4 4 3 7.0e−2 RTHERM5 3 2 7.5e−2 RTHERM6 2 TL 8.5e−2 RTHERM2 SABER Thermal Model RTHERM3 CTHERM1 6 CTHERM2 5 SABER thermal model FDH038AN08A1T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =5.5e−3 ctherm.ctherm2 6 5 =6.0e−3 ctherm.ctherm3 5 4 =7.4e−3 ctherm.ctherm4 4 3 =7.65e−3 ctherm.ctherm5 3 2 =5.85e−2 ctherm.ctherm6 2 tl =6.0e−1 CTHERM3 4 CTHERM4 RTHERM4 3 rtherm.rtherm1 th 6 =9.0e−3 rtherm.rtherm2 6 5 =2.08e−2 rtherm.rtherm3 5 4 =2.28e−2 rtherm.rtherm4 4 3 =7.0e−2 rtherm.rtherm5 3 2 =7.5e−2 rtherm.rtherm6 2 tl =8.5e−2 } CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl CASE Figure 23. Thermal Model POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−247−3LD SHORT LEAD CASE 340CK ISSUE A A DATE 31 JAN 2019 A E P1 P A2 D2 Q E2 S B D 1 2 D1 E1 2 3 L1 A1 L b4 c (3X) b 0.25 M (2X) b2 B A M DIM (2X) e GENERIC MARKING DIAGRAM* AYWWZZ XXXXXXX XXXXXXX XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week ZZ = Assembly Lot Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON13851G TO−247−3LD SHORT LEAD A A1 A2 b b2 b4 c D D1 D2 E E1 E2 e L L1 P P1 Q S MILLIMETERS MIN NOM MAX 4.58 4.70 4.82 2.20 2.40 2.60 1.40 1.50 1.60 1.17 1.26 1.35 1.53 1.65 1.77 2.42 2.54 2.66 0.51 0.61 0.71 20.32 20.57 20.82 13.08 ~ ~ 0.51 0.93 1.35 15.37 15.62 15.87 12.81 ~ ~ 4.96 5.08 5.20 ~ 5.56 ~ 15.75 16.00 16.25 3.69 3.81 3.93 3.51 3.58 3.65 6.60 6.80 7.00 5.34 5.46 5.58 5.34 5.46 5.58 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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