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FDMD8560L
Dual N-Channel PowerTrench® MOSFET
Q1: 60 V, 22 A, 3.2 mΩ Q2: 60 V, 22 A, 3.2 mΩ
Features
General Description
Q1: N-Channel
This device includes two 60V N-Channel MOSFETs in a dual
power (5 mm X 6 mm) package. HS source and LS drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Max rDS(on) = 3.2 mΩ at VGS = 10 V, ID = 22 A
Max rDS(on) = 5.4 mΩ at VGS = 4.5 V, ID = 18 A
Q2: N-Channel
Applications
Max rDS(on) = 3.2 mΩ at VGS = 10 V, ID = 22 A
Synchronous Buck: Primary Switch of Half / Full Bridge
Converter for Telecom
Max rDS(on) = 5.4 mΩ at VGS = 4.5 V, ID = 18 A
Ideal for Flexible Layout in Primary Side of Bridge Topology
100% UIL Tested
Motor Bridge: Primary Switch of Half / Full Bridge Converter
for BLDC Motor
Kelvin High Side MOSFET Drive Pin-out Capability
MV POL: 48V Synchronous Buck Switch
RoHS Compliant
Half/Full Bridge Secondary Synchronous Rectification
Bottom
Top
D2/S1
D2/S1
D2/S1
G2
S2
Pin 1
D1
D1
D1
GR
G1
G2
GR
D2/S1
D1
D2/S1
D1
D2/S1
Pin 1
G1
Power 5 x 6
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
-Continuous
Drain Current
TC = 25 °C
(Note 5)
-Continuous
TC = 100 °C
(Note 5)
-Continuous
TA = 25 °C
-Pulsed
Single Pulse Avalanche Energy
EAS
PD
TJ, TSTG
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Q1
60
Q2
60
Units
V
±20
±20
V
93
93
59
59
221a
221b
A
(Note 4)
550
550
(Note 3)
384
384
48
48
2.21a
2.21b
Operating and Storage Junction Temperature Range
mJ
-55 to +150
W
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction-to-Case
2.6
1a
Thermal Resistance, Junction-to-Ambient
55
2.6
55 1b
°C/W
Package Marking and Ordering Information
Device Marking
FDMD8560L
Device
FDMD8560L
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
Package
Power 5 x 6
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
May 2016
Symbol
Parameter
Test Conditions
Type
Min.
60
60
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 48 V, VGS = 0 V
Q1
Q2
1
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
Q1
Q2
±100
±100
nA
3.0
3.0
V
V
32
32
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
Q1
Q2
1.0
1.0
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
Q1
Q2
-7
-7
2.5
3.2
Q1
4.1
5.4
VGS = 10 V, ID = 22 A
VGS = 4.5 V, ID = 18A
rDS(on)
Static Drain to Source On Resistance
3.9
5.0
VGS = 10 V, ID = 22 A
2.5
3.2
4.1
5.4
3.9
5.0
VGS = 4.5 V, ID = 18 A
Forward Transconductance
mV/°C
VGS = 10 V, ID = 22 A, TJ = 125 °C
Q2
VGS = 10 V, ID = 22 A, TJ = 125 °C
gFS
1.6
1.6
VDD = 5 V, ID = 22 A
mΩ
Q1
Q2
98
98
Q1
Q2
7420
7420
11130
11130
pF
Q1
Q2
1110
1110
1665
1665
pF
38
38
60
60
pF
1.5
1.5
3.0
3.0
Ω
Q1
Q2
20
20
35
35
ns
Q1
Q2
15
15
26
26
ns
Q1
Q2
57
57
90
90
ns
Q1
Q2
11
11
20
20
ns
Q1
Q2
92
92
128
128
nC
Q1
Q2
42
42
59
59
nC
Q1
Q2
19
19
nC
Q1
Q2
7
7
nC
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Q1
Q2
Rg
Gate Resistance
Q1
Q2
VDS = 30 V, VGS = 0 V
f = 1 MHz
0.1
0.1
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
Total Gate Charge
VGS = 0 V to 10 V
Qg(TOT)
Total Gate Charge
VGS = 0 V to 4.5 V
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
VDD = 30 V, ID = 22 A
VGS = 10 V, RGEN = 6 Ω
2
VDD = 30 V,
ID =22 A
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Type
Min.
Typ.
Max.
Units
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage VGS = 0 V, IS = 22 A
(Note 2)
Q1
Q2
0.8
0.8
1.3
1.3
V
VSD
Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2 A
(Note 2)
Q1
Q2
0.7
0.7
1.2
1.2
V
trr
Reverse Recovery Time
Q1
Q2
53
53
84
84
ns
Q1
Q2
44
44
70
70
nC
IF = 22 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
NOTES:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 55 °C/W when mounted on
a 1 in2 pad of 2 oz copper
b. 55 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
c. 155 °C/W when mounted on
a minimum pad of 2 oz copper
d. 155 °C/W when mounted on
a minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. Q1: EAS of 384 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 16 A, VDD = 60 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 51 A.
Q2: EAS of 384 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 16 A, VDD = 60 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 51 A.
4. Pulsed Id please refer to Fig 11 and Fig 24 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
3
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
180
VGS = 4 V
VGS = 3.5 V
120
90
VGS = 3 V
60
30
0
0.0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
2.5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
150
ID, DRAIN CURRENT (A)
6
VGS = 10 V
VGS = 4.5 V
4
VGS = 3 V
VGS = 3.5 V
VGS = 4.5 V
VGS = 10 V
0
3.0
0
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
120
150
180
12
ID = 22 A
VGS = 10 V
1.7
1.6
rDS(on), DRAIN TO
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-75
-50
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
90
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
1.8
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
120
90
60
TJ = 25 oC
TJ = 150 oC
TJ = -55 oC
1
2
3
4
6
TJ = 125 oC
3
TJ = 25 oC
2
200
100
3
4
5
6
7
8
9
10
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
5
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
ID = 22 A
Figure 4. On-Resistance vs. Gate to
Source Voltage
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
9
VGS, GATE TO SOURCE VOLTAGE (V)
180
150
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs. Junction Temperature
ID, DRAIN CURRENT (A)
60
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
0
VGS = 4 V
2
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
4
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
10000
Ciss
ID = 22 A
8
VDD = 30 V
VDD = 20 V
6
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 40 V
4
2
0
0
20
40
60
80
1000
Coss
100
f = 1 MHz
VGS = 0 V
Crss
10
0.1
100
1
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
100
TJ = 100 oC
TJ = 25 oC
10
ID, DRAIN CURRENT (A)
100
IAS, AVALANCHE CURRENT (A)
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
TJ = 125 oC
80
VGS = 10 V
60
VGS = 4.5 V
40
20
o
RθJC = 2.6 C/W
1
0.001
0.01
0.1
1
10
100
0
25
1000
125
150
5
P(PK), PEAK TRANSIENT POWER (W)
10
100
10 μs
10
0.01
0.01
100
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
1000
0.1
75
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
1
50
o
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
10
100 μs
THIS AREA IS
LIMITED BY rDS(on)
1 ms
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.6 oC/W
TC = 25 oC
0.1
CURVE BENT TO
MEASURED DATA
1
10
100200
VDS, DRAIN to SOURCE VOLTAGE (V)
4
10
TC = 25 oC
3
10
2
10
10 -5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
SINGLE PULSE
RθJC = 2.6 oC/W
Figure 12. Single Pulse Maximum Power
Dissipation
5
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
ZθJC(t) = r(t) x RθJC
RθJC = 2.6 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
6
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
180
VGS = 4 V
VGS = 3.5 V
120
90
VGS = 3 V
60
30
0
0.0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
2.5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
150
ID, DRAIN CURRENT (A)
6
VGS = 10 V
VGS = 4.5 V
4
VGS = 3 V
VGS = 3.5 V
VGS = 4.5 V
VGS = 10 V
0
3.0
0
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
120
150
180
12
ID = 22 A
VGS = 10 V
1.7
1.6
rDS(on), DRAIN TO
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
-75
-50
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
90
Figure 15. Normalized on-Resistance vs. Drain
Current and Gate Voltage
1.8
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
120
90
60
TJ = 150 oC
TJ = 25 oC
TJ = -55 oC
1
2
3
4
ID = 22 A
6
TJ = 125 oC
3
TJ = 25 oC
2
3
4
5
6
7
8
9
200
100
VGS = 0 V
10
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
5
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs. Source Current
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
10
Figure 17. On-Resistance vs. Gate to
Source Voltage
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
30
9
VGS, GATE TO SOURCE VOLTAGE (V)
180
150
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 16. Normalized On-Resistance
vs. Junction Temperature
ID, DRAIN CURRENT (A)
60
ID, DRAIN CURRENT (A)
Figure 14. On- Region Characteristics
0
VGS = 4 V
2
7
1.2
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.
10000
Ciss
ID = 22 A
8
VDD = 30 V
VDD = 20 V
6
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 40 V
4
1000
Coss
100
f = 1 MHz
VGS = 0 V
2
0
0
20
40
60
80
100
1
100
Figure 21. Capacitance vs. Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
100
TJ = 100 oC
TJ = 25 oC
10
ID, DRAIN CURRENT (A)
100
TJ = 125 oC
80
VGS = 10 V
60
VGS = 4.5 V
40
20
o
RθJC = 2.6 C/W
1
0.001
0.01
0.1
1
10
100
0
25
1000
50
150
5
P(PK), PEAK TRANSIENT POWER (W)
10
100
10 μs
10
0.01
0.01
125
Figure 23. Maximum Continuous Drain
Current vs. Case Temperature
1000
0.1
100
TC, CASE TEMPERATURE ( C)
Figure 22. Unclamped Inductive
Switching Capability
1
75
o
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
IAS, AVALANCHE CURRENT (A)
Crss
10
0.1
100 μs
THIS AREA IS
LIMITED BY rDS(on)
1 ms
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
o
RθJC = 2.6 C/W
TC = 25 oC
CURVE BENT TO
MEASURED DATA
0.1
1
10
100200
VDS, DRAIN to SOURCE VOLTAGE (V)
4
10
TC = 25 oC
3
10
2
10
10 -5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
Figure 24. Forward Bias Safe
Operating Area
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
SINGLE PULSE
RθJC = 2.6 oC/W
Figure 25. Single Pulse Maximum Power
Dissipation
8
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
ZθJC(t) = r(t) x RθJC
RθJC = 2.6 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Case Transient Thermal Response Curve
©2016 Fairchild Semiconductor Corporation
FDMD8560L Rev.1.0
9
www.fairchildsemi.com
FDMD8560L Dual N-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
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