Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
dual PQFN package. The switch node has been internally
Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
Q2: N-Channel
SyncFETTM (Q2) have been designed to provide optimal power
Max rDS(on) = 5 mΩ at VGS = 10 V, ID = 18 A
efficiency.
Max rDS(on) = 5.2 mΩ at VGS = 4.5 V, ID = 17 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Computing
Communications
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
General Purpose Point of Load
RoHS Compliant
Notebook VCORE
G1
Pin 1
D1
Pin 1
D1
D1
D1
PHASE
(S1/D2)
G2
S2
S2
Top
S2
5
S2
6
S2
7
G2
8
S2
Bottom
Power 56
Q2
4 D1
PHASE
3 D1
2 D1
1 G1
Q1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
TJ, TSTG
Units
V
V
(Note 3)
±20
±12
TC = 25 °C
30
60
-Continuous (Silicon limited)
TC = 25 °C
60
77
-Continuous
TA = 25 °C
131a
181b
-Pulsed
PD
Q2
30
-Continuous (Package limited)
Single Pulse Avalanche Energy
EAS
Q1
30
40
60
334
215
mJ
Power Dissipation for Single Operation
TA = 25 °C
2.21a
2.51b
Power Dissipation for Single Operation
TA = 25 °C
11c
11d
Operating and Storage Junction Temperature Range
A
W
-55 to +150
°C
Thermal Characteristics
Thermal Resistance, Junction to Ambient
571a
501b
RθJA
Thermal Resistance, Junction to Ambient
1251c
1201d
RθJC
Thermal Resistance, Junction to Case
2.9
2.8
RθJA
°C/W
Package Marking and Ordering Information
Device Marking
22CF
21CD
Device
Package
Reel Size
Tape Width
Quantity
FDMS3668S
Power 56
13 ”
12 mm
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
1
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
December 2012
FDMS3668S
Symbol
Parameter
Test Conditions
Type
Min
30
30
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Q1
Q2
1
500
μA
μA
IGSS
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V
VGS = 12 V, VDS= 0 V
Q1
Q2
100
100
nA
nA
2.7
2.2
V
V
16
17
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-3
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
Q1
4
6
5.7
8
11
8.7
VGS = 10 V, ID = 18 A
VGS = 4.5 V, ID = 17 A
VGS = 10 V, ID = 18 A , TJ = 125 °C
Q2
3
3.6
4.4
5
5.2
7.3
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 17 A
Q1
Q2
62
110
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
1325
1935
1765
2575
pF
Q1
Q2
466
479
620
635
pF
Q1
Q2
46
45
70
70
pF
0.6
1.3
2
3
Ω
rDS(on)
gFS
Drain to Source On Resistance
Forward Transconductance
1.1
1.1
1.9
1.5
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
0.2
0.2
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg
Total Gate Charge
Qg
Total Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 17 A, RGEN = 6 Ω
VGS = 0 V to 10 V
Q1:
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2:
VDD = 15 V,
ID = 17 A
2
Q1
Q2
7.7
7.1
15
14
ns
Q1
Q2
2.2
2.7
10
10
ns
Q1
Q2
19
25
34
40
ns
Q1
Q2
1.8
1.9
10
10
ns
Q1
Q2
21
27
29
38
nC
Q1
Q2
9.5
12
13
17
nC
Q1
Q2
3.9
4
nC
Q1
Q2
2.6
2.5
nC
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q1
Q2
Q2
0.8
0.7
0.8
0.7
1.2
1.2
1.2
1.2
V
Q1
Q2
26
21
42
33
ns
Q1
Q2
10
17
20
31
nC
Drain-Source Diode Characteristics
VSD
VGS = 0 V, IS = 13 A
V = 0 V, IS = 2 A
Source to Drain Diode Forward Voltage GS
VGS = 0 V, IS = 17 A
VGS = 0 V, IS = 2 A
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Q1:
IF = 13 A, di/dt = 100 A/μs
Q2:
IF = 17 A, di/dt = 300 A/μs
Notes:
1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied with the negative Vgs rating.
4: EAS of 33 mJ is based on starting TJ = 25 oC; N-ch: L = 1.9 mH, IAS = 6 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A.
5: EAS of 21 mJ is based on starting TJ = 25 oC; N-ch: L = 0.5 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 16 A.
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
3
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
40
4
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 10 V
30
VGS = 6 V
VGS = 4.5 V
20
VGS = 4 V
VGS = 3.5 V
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.2
0.4
0.6
0.8
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
3
VGS = 3.5 V
VGS = 4 V
2
1
0
1.0
0
10
20
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
rDS(on), DRAIN TO
1.2
1.0
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.4
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
16
ID = 13 A
12
TJ = 125 oC
8
4
TJ = 25 oC
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure 4. On-Resistance vs Gate to
Source Voltage
40
IS, REVERSE DRAIN CURRENT (A)
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
30
20
ID = 13 A
VGS = 10 V
-50
VGS = 10 V
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
0.6
-75
VGS = 6 V
VGS = 4.5 V
30
VDS = 5 V
TJ = 150 oC
20
TJ = 25 oC
10
TJ = -55 oC
0
1.5
2.0
2.5
3.0
3.5
TJ = 150 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
4.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
VGS = 0 V
10
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2000
ID = 13 A
VDD = 10 V
Ciss
1000
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 15 V
6
VDD = 20 V
4
Coss
100
Crss
2
f = 1 MHz
VGS = 0 V
0
0
5
10
15
20
10
0.1
25
1
10
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain
to Source Voltage
80
100
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
o
RθJC = 2.9 C/W
TJ = 25 oC
10
TJ = 100 oC
60
VGS = 10 V
40
VGS = 4.5 V
20
Limited by Package
TJ = 125 oC
1
0.001
0.01
0.1
1
10
0
25
100
50
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
150
1000
100 μs
10
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
1s
10 s
DC
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
0.1
100
o
Figure 9. Unclamped Inductive
Switching Capability
1
75
TC, CASE TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
0.1
1
10
o
RθJA = 125 C/W
100
10
1
0.1 -4
10
100200
VDS, DRAIN to SOURCE VOLTAGE (V)
-3
10
-2
10
-1
10
1
100
10
1000
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
SINGLE PULSE
Figure 12. Single Pulse Maximum
Power Dissipation
5
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 125 C/W
(Note 1c)
0.001 -4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
6
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
25 oC unlenss otherwise noted
60
4
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
VGS = 10 V
ID, DRAIN CURRENT (A)
VGS = 4.5 V
VGS = 3.5 V
40
VGS = 3 V
VGS = 2.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.3
0.6
0.9
1.2
3
VGS = 3 V
2
VGS = 3.5 V
1
VGS = 4.5 V
0
1.5
0
20
Figure 14. On-Region Characteristics
rDS(on), DRAIN TO
1.4
1.2
1.0
0.8
-25
0
25
50
75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
60
20
ID = 18 A
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
ID = 18 A
10
TJ = 25 oC
0
100 125 150
TJ = 125 oC
5
2
TJ, JUNCTION TEMPERATURE (oC)
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
100
60
IS, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
40
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
-50
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.6
-75
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
VDS = 5 V
40
TJ = 125 oC
TJ = 25 oC
20
TJ = -55 oC
0
1.0
1.5
2.0
2.5
10
TJ = 125 oC
1
0.1
TJ = 25 oC
TJ = -55 oC
0.01
0.001
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
Figure 18. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
VGS = 0 V
7
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ =
10000
ID = 17 A
Ciss
8
VDD = 10 V
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD = 15 V
4
VDD = 20 V
1000
Coss
100
2
0
f = 1 MHz
VGS = 0 V
0
10
20
Crss
10
0.1
30
1
10
30
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
100
100
o
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
RθJC = 2.8 C/W
TJ = 25 oC
TJ = 100 oC
10
TJ =
1
0.0001
125 oC
80
VGS = 10 V
60
40
Limited by Package
20
0
0.001
0.01
0.1
1
10
100
VGS = 4.5 V
25
50
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
150
3000
100 μs
10
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
SINGLE PULSE
TJ = MAX RATED
1s
100 ms
10s
RθJA = 120 oC/W
DC
TA = 25 oC
0.01
0.01
125
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
100
0.1
100
o
Figure 22. Unclamped Inductive
Switching Capability
1
75
TC, CASE TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
0.1
1
10
100200
SINGLE PULSE
o
RθJA = 120 C/W
100
10
1
0.5 -4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 25. Single Pulse Maximum
Power Dissipation
Figure 24. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
1000
8
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
NORMALIZED THERMAL
IMPEDANCE, ZθJA
2
1
0.1
0.01
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
SINGLE PULSE
t2
o
RθJA = 120 C/W
0.001
0.0001 -4
10
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
(Note 1d)
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
9
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
TJ = 25 oC unless otherwise noted
Typical Characteristics (Q2 N-Channel)
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3668S.
Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power
in the device.
-2
IDSS, REVERSE LEAKAGE CURRENT (A)
20
15
CURRENT (A)
didt = 300 A/μs
10
5
0
-5
0
40
80
120
160
TIME (ns)
TJ = 125 oC
-3
10
TJ = 100 oC
-4
10
-5
10
TJ = 25 oC
-6
10
0
5
10
15
20
25
30
VDS, REVERSE VOLTAGE (V)
Figure 28. SyncFETTM body diode reverse
leakage versus drain-source voltage
Figure 27. FDMS3668S SyncFETTM body
diode reverse recovery characteristic
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
10
10
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Typical Characteristics (continued)
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Competitors solution
Power Stage Device
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
11
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Application Information
FDMS3668S PowerTrench® Power Stage
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
12
www.fairchildsemi.com
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2012 Fairchild Semiconductor Corporation
FDMS3668S Rev.C3
13
www.fairchildsemi.com
FDMS3668S PowerTrench® Power Stage
Following is a guideline, not a requirement which the PCB designer should consider:
CL
B
PKG
CL
8
A
0.00
(2X)
2.00
5.10
4.90
0.10 C
4.00
5
8
7
6
1.27 TYP
0.65 TYP
5
0.63
6.25
5.90
PKG CL
2.52
1.60
KEEP OUT AREA
2.15
0.00 CL
4.16
1.21
2.13
1
PIN # 1
INDICATOR
4
0.10 C
(2X)
1.18
TOP VIEW
2
1
0.63
SEE
DETAIL A
3
4
2.31
3.15
0.59
3.18
5.10
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.10
0.05
0.45
0.25
3.16
2.80
0.65
0.38
1
2
3
(6X)
C A B
C
0.70
0.36
4
1.34
1.12
0.10 C
8X
0.08 C
1.10
0.90
0.35
0.15
0.66±.05
2.25
2.05
4.08
3.70
0.65
0.38
8
0.44
0.24
7
6
5
1.27
3.81
BOTTOM VIEW
1.02
0.82
0.61 (8X)
0.31
(SCALE: 2X)
0.05
0.00
C
SEATING
PLANE
5.10
4.90
0.10 C
(2X)
SEE
DETAIL B
PKG
CL
8
0.35
0.15
5
0.28
0.08
PKG
6.25
5.90
CL
1
(SCALE: 2X)
0.10 C
(2X)
4
0.41 (8X)
0.21
TOP VIEW
10°
5.90
5.70
5.00
4.80
SEE
DETAIL C
0.10 C
0.35
0.15
8X
0.08 C
C
SIDE VIEW
1.10
0.90
0.45
0.25
(6X)
3.16
2.80
0.65
0.38
1
2
3
0.70
0.36
4
0.10
0.05
0.65
0.38
0.44
0.24
2.25
2.05
8
7
6
5
1.27
3.81
BOTTOM VIEW
C A B
C
1.34
1.12
0.66±.05
4.08
3.70
(SCALE: 2X)
SEATING
PLANE
1.02
0.82
0.61
0.31
(8X)
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
© Semiconductor Components Industries, LLC
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
www.onsemi.com
1
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
www.onsemi.com
工商网监
湘ICP备2023018690号
