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FOD8160
High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate
Optocoupler in Wide-Body SOP 5-Pin
Features
Description
■ Optoplanar®
The FOD8160 is a 3.3 V / 5 V high-speed logic gate
optocoupler with open-collector output, which supports
isolated communications to allow digital signals to
communicate between systems without conducting
ground loops or hazardous voltages. The device utilizes
Fairchild’s prioprietary Optoplanar® coplanar packaging
technology and optimized IC design to achieve highnoise immunity, characterized by high common-mode
rejection specifications.
■
■
■
■
Packaging Technology Allows More
Than 10 mm Creepage and Clearance Distance, and
0.5 mm Insulation Distance to Achieve Reliable and
High Voltage Insulation
High Noise Immunity Characterized by Common
Mode Transient Immunity (CMTI)
– 20 kV/µs Minimum CMTI
Specifications Guaranteed Over 3 V to 5.5 V Supply
Voltage and -40°C to 100°C Extended Industrial
Temperature Range
High-Speed, 10 Mbit/s Data Rate (NRZ)
Safety and Regulatory Approvals
– UL1577, 5,000 VACRMS for 1 Minute
– DIN-EN/IEC60747-5-5, 1,414 V Peak Working
Insulation Voltage
Applications
■ Isolating Intelligent Power Module
The FOD8160, packaged in a wide-body SOP 5-Pin
package, consists of an aluminium gallium arsenide
(AlGaAs) LED and an integrated high-speed
photodetector. The output of the detector IC is an open
collector Schottky-clamped transistor. The electrical and
switching characteristics are guaranteed over the
extended industrial temperature range of -40°C to 100°C
and a VCC range of 3 V to 5.5 V.
Functional Schematic
■ Isolating Industrial Communication Interface
Related Resources
6 VCC
ANODE 1
■ www.fairchildsemi.com/products/opto/
■ www.fairchildsemi.com/pf/FO/FODM8061.html
5 VO
■ www.fairchildsemi.com/pf/FO/FODM611.html
CATHODE 3
4 GND
Figure 1. Functional Schematic
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
July 2014
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Truth Table
LED
Output
Off
HIGH
On
LOW
Pin Configuration
1
6
ANODE
CATHODE
VCC
5
3
VO
4
GND
Figure 2. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
Anode
3
Cathode
4
GND
Output Ground
5
VO
Output Voltage
6
VCC
Output Supply Voltage
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
Anode
Cathode
www.fairchildsemi.com
2
As per DIN EN/IEC60747-5-5, this optocoupler is suitable for “safe electrical insulation” only within the safety limit data
below. Compliance with the safety ratings shall be ensured by means of protective circuits.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150 VRMS
I–IV
For Rated Mains Voltage < 300 VRMS
I–IV
For Rated Mains Voltage < 450 VRMS
I–IV
For Rated Mains Voltage < 600 VRMS
I–IV
Climatic Classification
40/100/21
Pollution Degree (DIN VDE 0110/1.89)
2
CTI
Comparative Tracking Index
175
VPR
Input to Output Test Voltage, Method b, VIORM x 1.875 = VPR,
100% Production Test with tm = 1 s, Partial Discharge < 5 pC
2651
Vpeak
Input to Output Test Voltage, Method a, VIORM x 1.6 = VPR,
Type and Sample Test with tm = 10 s, Partial Discharge < 5 pC
2262
Vpeak
VIORM
Maximum Working Insulation Voltage
1414
Vpeak
VIOTM
Highest Allowable Over Voltage
8000
Vpeak
External Creepage
10.0
mm
External Clearance
10.0
mm
Insulation Thickness
0.5
mm
150
°C
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
TS
Case Temperature
IS,INPUT
Input Current
200
mA
PS,OUTPUT
Output Power
600
mW
109
Ω
RIO
Insulation Resistance at TS, VIO = 500 V
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
3
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Safety and Insulation Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Symbol
Parameter
Value
Units
TSTG
Storage Temperature
-40 to +125
°C
TOPR
Operating Temperature
-40 to +100
°C
TJ
TSOL
Junction Temperature
Lead Solder Temperature
(Refer to Reflow Temperature Profile on page 12)
-40 to +125
°C
260 for 10 seconds
°C
Input Characteristics
IF
Average Forward Input Current
25
mA
VR
Reverse Input Voltage
5.0
V
45
mW
V
PDI
Input Power
Dissipation(1)
Output Characteristics
VCC
Supply Voltage
0 to 7.0
VO
Output Voltage
-0.5 to VCC + 0.5
V
IO
Average Output Current
50
mA
Output Power Dissipation(1)
85
mW
PDO
Note:
1. No derating required up to 100°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Min.
Max.
Unit
Ambient Operating Temperature
-40
+100
ºC
VCC
Supply Voltages(2)
3.0
5.5
V
VFL
Logic Low Input Voltage
0
0.8
V
IFL
Logic Low Input Current
250
µA
IFH
Logic High Input Current
TA
Parameter
N
Fan Out (at RL = 1 kΩ)
RL
Output Pull-up Resistor
6.0
330
15
mA
5
TTL loads
4000
Ω
Note:
2. 0.1 µF bypass capacitor must be connected between pins 4 and 6.
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
4
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Absolute Maximum Ratings
Apply over all recommended conditions, typical value is measured at TA = 25°C.
Symbol
Parameter
Conditions
Min.
5,000
VISO
Input-Output Isolation
Voltage
TA = 25°C, R.H. < 50%, t = 1.0 min,
II-O ≤ 20 µA(3)(4)
RISO
Isolation Resistance
VI-O = 500 V(3)
CISO
Isolation Capacitance
VI-O = 0 V, frequency = 1.0
MHz(3)
Typ.
Max.
Units
VACRMS
1011
Ω
1.0
pF
Notes:
3. Device is considered a two-terminal device: pins 1 and 3 are shorted together and pins 4, 5, and 6 are shorted
together.
4. 5,000 VACRMS for 1-minute duration is equivalent to 6,000 VACRMS for 1-second duration.
Electrical Characteristics
Apply over all recommended conditions; TA = -40°C to +100°C, 3.0 V ≤ VCC ≤ 5.5 V; unless otherwise specified.
Typical value is measured at TA = 25°C and VCC = 3.3 V or VCC = 5 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Figure
1.05
1.45
1.80
V
3
Input Characteristics
VF
Δ(VF / TA)
Forward Voltage
IF = 10 mA
Temperature Coefficient
of Forward Voltage
-1.8
BVR
Input Reverse
Breakdown Voltage
IFHL
Threshold Input Current VO = 0.6 V,
IOL(sink) = 13 mA
IR = 10 µA
mV/°C
5.0
V
2.5
6.0
mA
4
Output Characteristics
VOL
Logic Low Output
Voltage
IF = rated IFHL,
IOL(sink) = 13 mA
0.4
0.6
V
5
IOH
Logic High Output
Current
IF = 250 µA, VO = 3.3 V
8.0
50.0
µA
6
IF = 250 µA, VO = 5.0 V
3.0
40.0
µA
6
ICCL
ICCH
Logic Low Output
Supply Current
Logic High Output
Supply Current
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
IF = 10 mA, VCC = 3.3 V
5.3
8.5
mA
7, 9
IF = 10 mA, VCC = 5.0 V
7.1
10.0
mA
7, 9
IF = 0 mA, VCC = 3.3 V
3.5
7.0
mA
8, 9
IF = 0 mA, VCC = 5.0 V
5.3
9.0
mA
8, 9
www.fairchildsemi.com
5
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Isolation Characteristics
Apply over all recommended conditions; TA = -40°C to +100°C, VCC = 3.3 V, IF = 6.0 mA; unless otherwise specified.
Typical value is measured at TA = 25°C and VCC = 3.3 V.
Symbol
Parameter
Conditions
Min.
Typ.
RL = 350 Ω
Data Rate
Max.
Units
Figure
10
Mbit/sec
tPHL
Propagation Delay to
Logic Low Output
RL = 350 Ω, CL = 15 pF
40
80
ns
10, 11,
15
tPLH
Propagation Delay to
Logic High Output
RL = 350 Ω, CL = 15 pF
50
90
ns
10, 11,
15
PWD
Pulse Width Distortion,
| tPHL – tPLH|
RL = 350 Ω, CL = 15 pF
10
35
ns
12, 13,
15
tPSK
Propagation Delay Skew RL = 350 Ω, CL = 15 pF
40
ns
(5)
tR
Output Rise Time
(10% to 90%)
RL = 350 Ω, CL = 15 pF
20
ns
14, 15
tF
Output Fall Time
(90% to 10%)
RL = 350 Ω, CL = 15 pF
10
ns
14, 15
| CMH |
Common-Mode
Transient Immunity at
Output High
IF = 0 mA, VO > 2 V,
VCM = 1,000 V(6)
20
40
kV/µs
16
| CML |
Common-Mode
Transient Immunity at
Output Low
IF = 6.0 mA, VO < 0.8 V,
VCM = 1,000 V(6)
20
40
kV/µs
16
Apply over all recommended conditions; TA = -40°C to +100°C, VCC = 5 V, IF = 6.0 mA; unless otherwise specified.
Typical value is measured at TA = 25°C and VCC = 5 V.
Symbol
Parameter
Conditions
Min.
Typ.
RL = 350 Ω
Data Rate
Max.
Units
Figure
10
Mbit/sec
tPHL
Propagation Delay to
Logic Low Output
RL = 350 Ω, CL = 15 pF
37
80
ns
10, 11,
15
tPLH
Propagation Delay to
Logic High Output
RL = 350 Ω, CL = 15 pF
41
90
ns
10, 11,
15
PWD
Pulse Width Distortion,
| tPHL – tPLH|
RL = 350 Ω, CL = 15 pF
4
25
ns
12, 13,
15
tPSK
Propagation Delay Skew RL = 350 Ω, CL = 15 pF(5)
40
ns
tR
Output Rise Time
(10% to 90%)
RL = 350 Ω, CL = 15 pF
22
ns
14, 15
tF
Output Fall Time
(90% to 10%)
RL = 350 Ω, CL = 15 pF
9
ns
14, 15
| CMH |
Common-Mode
Transient Immunity at
Output High
IF = 0 mA, VO > 2 V,
VCM = 1,000 V(6)
20
40
kV/µs
16
| CML |
Common-Mode
Transient Immunity at
Output Low
IF = 6.0 mA, VO < 0.8 V,
VCM = 1,000 V(6)
20
40
kV/µs
16
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
6
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Switching Characteristics
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
7
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Notes:
5. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH between any two units from the same
manufacturing date code that are operated at same case temperature (±5°C), at same operating conditions, with
equal loads (RL = 350 Ω, CL = 15 pF), and with an input rise time less than 5 ns.
6. Common-mode transient immunity at output HIGH is the maximum tolerable positive dVcm/dt on the leading edge
of the common-mode impulse signal, VCM, to assure that the output remains HIGH. Common-mode transient
immunity at output LOW is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
VCM, to assure that the output remains LOW.
IFHL – THRESHOLD INPUT CURENT (mA)
IF – INPUT LED CURENT (mA)
100
10
1
0.1
0.001
0.6
0.8
-40°C
25°C
TA = 100°C
0.01
1.0
1.2
1.4
1.6
1.8
3.0
IOL = 13 mA
2.5
VCC = 3.3 V
VCC = 5.0 V
2.0
1.5
1.0
-40
2.0
-20
VOL – LOGIC LOW OUTPUT VOLTAGE (V)
0.50
IOL = 13 mA
IF = 6 mA
0.45
0.40
VCC = 3.3 V
0.35
VCC = 5.0 V
0.30
0.25
-20
0
20
40
60
80
100
ICCH – LOGIC HIGH OUTPUT SUPPLY CURRENT (mA)
ICCL – LOGIC LOW OUTPUT SUPPLY CURRENT (mA)
8
VCC = 5.0 V
6
VCC = 3.3 V
4
2
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
IF = 250 μA
VO = 3.3 V / 5.0 V
20
15
10
VCC = 3.3 V
5
VCC = 5.0 V
0
-40
-20
0
20
40
60
80
100
10
IF = 0 mA
8
6
VCC = 5.0 V
4
VCC = 3.3 V
2
0
-40
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
Figure 7. Logic Low Output Supply Current (ICCL)
vs. Ambient Temperature
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
100
Figure 6. Logic High Output Current (IOH)
vs. Ambient Temperature
IF = 10 mA
20
80
TA – AMBIENT TEMPERATURE (°C)
10
0
60
25
Figure 5. Logic Low Output Voltage (VOL)
vs. Ambient Temperature
-20
40
30
TA – AMBIENT TEMPERATURE (°C)
0
-40
20
Figure 4. Threshold Input Current (IFHL) vs.
Ambient Temperature
IOH – LOGIC HIGH OUTPUT SUPPLY CURRENT (μA)
Figure 3. Input LED Current (IF) vs.
Forward Voltage (VF)
0.20
-40
0
TA – AMBIENT TEMPERATURE (°C)
V F – FORWARD VOLTAGE (V)
Figure 8. Logic High Output Supply Current (ICCH)
vs. Ambient Temperature
www.fairchildsemi.com
8
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Typical Performance Characteristics
80
IF = 0 mA (for ICCH), 10 mA (for ICCL)
TA = 25°C
tP – PROPAGATION DELAY (ns)
ICC – OUTPUT SUPPLY CURRENT (mA)
10
8
ICCL
6
ICCH
4
2
0
3.0
3.5
4.0
4.5
5.0
Frequency = 5 MHz, 50% Duty Cycle
IF = 6 mA, RL = 350 Ω
70
60
tPLH @ VCC = 3.3 V
50
tPLH @ VCC = 5.0 V
40
tPHL @ VCC = 5.0 V
20
-40
5.5
-20
VCC – OUTPUT SUPPLY VOLTAGE (V)
(|tPHL – tPLH|) – PULSE WIDTH DISTORTION (ns)
tP – PROPAGATION DELAY (ns)
Frequency = 5 MHz, 50% Duty Cycle
RL = 350 Ω, TA = 25°C
60
tPLH @ VCC = 3.3 V
50
tPLH @ VCC = 5.0 V
tPHL @ VCC = 3.3 V
tPHL @ VCC = 5.0 V
20
5
6
7
8
40
60
80
100
9
10
20
Frequency = 5 MHz, 50% Duty Cycle
IF = 6 mA, RL = 350 Ω
VCC = 3.3 V
16
12
8
VCC = 5.0 V
4
0
-40
-20
I F – INPUT LED CURRENT (mA)
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
Figure 12. Pulse Width Distortion vs.
Ambient Temperature
Figure 11. Propagation Delay vs.
Input LED Current (IF)
40
25
Frequency = 5 MHz, 50% Duty Cycle
RL = 350 Ω, TA = 25°C
Frequency = 5 MHz, 50% Duty Cycle
IF = 6 mA, RL = 350 Ω
tR, tF – RISE, FALL TIME (ns)
(|tPHL – tPLH|) – PULSE WIDTH DISTORTION (ns)
20
Figure 10. Propagation Delay vs.
Ambient Temperature
70
30
0
TA – AMBIENT TEMPERATURE (°C)
Figure 9. Output Supply Current (ICC)
vs. Output Supply Voltage (VCC)
40
tPHL @ VCC = 3.3 V
30
20
VCC = 3.3 V
15
10
VCC = 5.0 V
5
30
tR @ VCC = 5.0 V
20
tR @ VCC = 3.3 V
tF @ VCC = 3.3 V
10
tF @ VCC = 5.0 V
0
-40
0
5
6
7
8
9
10
Figure 13. Pulse Width Distortion vs.
Input LED Current (IF)
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
I F – INPUT LED CURRENT (mA)
Figure 14. Rise Time (tR) and Fall Time (tF)
vs. Ambient Temperature
www.fairchildsemi.com
9
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Typical Performance Characteristics (Continued)
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Test Circuit
Pulse Gen.
5 MHz
tf = tr = 5 ns
DC = 50%
IF
0.1 μF
Bypass
350 Ω
CL
Input
Monitoring
Mode
VO Monitoring
Node
RM
(IF = 6 mA)
Input
50%
tf
tr
90%
1.5 V
10%
VOL
Output
tPHL
tPLH
Figure 15. Test Circuit for Propagation Delay, Rise Time, and Fall Time
IF
VCC
0.1 μF
Bypass
SW
350 Ω
CL
VO Monitoring
Node
RM
VCM
Pulse Gen
1 kV
VCM 90%
10%
0V
tr
tf
VOH
VO (IF = 0 mA)
2V
0.8 V
VO (IF = 6 mA)
VOL
Figure 16. Test Circuit for Instantaneous Common-Mode Rejection Voltage
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
10
Part Number
Package
Packing Method
FOD8160
Wide Body SOP 5-Pin
Tube (100 units per tube)
FOD8160R2
Wide Body SOP 5-Pin
Tape and Reel (1,000 units per reel)
FOD8160V
Wide Body SOP 5-Pin, DIN EN/IEC60747-5-5 Option Tube (100 units per tube)
FOD8160R2V
Wide Body SOP 5-Pin, DIN EN/ IEC60747-5-5 Option Tape and Reel (1,000 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
2
3
8160 V
D X YY KK W
4
6
5
8
7
Definitions
1
Fairchild logo
2
Device number, e.g., ‘8160’ for FOD8160
3
DIN EN/IEC60747-5-5 option (only appears on
component ordered with this option)
4
Plant code, e.g., ‘D’
5
Last-digit year code, e.g., ‘E’ for 2014
6
Two-digit work week ranging from ‘01’ to ‘53’
7
Lot-traceability code
8
Package assembly code, W
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
www.fairchildsemi.com
11
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Ordering Information
FOD8160 — High Noise Immunity, 3.3 V / 5 V, 10 Mbit/sec, Logic Gate Optocoupler in Wide-Body SOP 5-Pin
Reflow Profile
Temperature (°C)
TP
260
240
TL
220
200
180
160
140
120
100
80
60
40
20
0
Max. Ramp-up Rate = 3°C/s
Max. Ramp-down Rate = 6°C/s
tP
Tsmax
tL
Preheat Area
Tsmin
ts
120
240
360
Time 25°C to Peak
Time (seconds)
Figure 17. Reflow Profile
Profile Freature
Pb-Free Assembly Profile
Temperature Minimum (Tsmin)
150°C
Temperature Maximum (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60 to 120 seconds
Ramp-Up Rate (tL to tP)
3°C/second maximum
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60 to 150 seconds
Peak Body Package Temperature
260°C +0°C / –5°C
Time (tP) within 5°C of 260°C
30 seconds
Ramp-Down Rate (TP to TL)
6°C/second maximum
Time 25°C to Peak Temperature
©2012 Fairchild Semiconductor Corporation
FOD8160 Rev. 1.0.2
8 minutes maximum
www.fairchildsemi.com
12
0.20 C A-B
3.95
0.60
2X
1.27
4
6
D
1.38
A
6
4
1.27
4.60
11.38
11.80
11.60
9.20
0.10 C D
2X
1
3
1
0.33 C
PIN ONE
INDICATOR
B
2.54
0.25
5X 0.51
0.31
2.54
C A-B D
LAND PATTERN
RECOMMENDATION
5 TIPS
A
2.65
2.45
0.10 C
3
SEATING
PLANE
2.95 MAX
0.10 C
0.30
0.10
5X
C
NOTES: UNLESS OTHERWISE SPECIFIED
1.35
1.15
GAUGE
PLANE
8°
0°
0.25
C
(R1.29)
SEATING
PLANE
SCALE: 3.2:1
0.74
0.44
A) THIS PACKAGE DOES NOT
CONFORM TO ANY STANDARD.
B) ALL DIMENSIONS ARE IN
(R0.54)
MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF
BURRS, MOLD FLASH AND TIE BAR
PROTRUSIONS
D) DRAWING CONFORMS TO ASME
0.25
Y14.5M-1994
0.19
E) DRAWING FILE NAME:
MKT-M05AREV3
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