FS6370-01G-XTP

FS6370 EEPROM Programmable 3-PLL Clock Generator IC 1.0 Features • • • • • • • • • Just-in-time customization of clock frequencies via internal non-volatile 128-bit serial EEPROM I2C™-bus serial interface Three on-chip PLLs with programmable reference and feedback dividers Four independently programmable muxes and post dividers Programmable power-down of all PLLs and output clock drivers Tristate outputs for board testing One PLL and two mux/post-divider combinations can be modified via SEL_CD input 5 V to 3.3 V operation Accepts 5 MHz to 27 MHz crystal resonators 2.0 Description The FS6370 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three EEPROM-programmable phase-locked loops (PLLs) driving four programmable muxes and post dividers provide a high degree of flexibility. An internal EEPROM permits just-in-time factory programming of devices for end user requirements. Figure 1: Pin Configuration ©2008 SCILLC. All rights reserved. May 2008 – Rev. 3 Publication Order Number: FS6370/D FS6370 Figure 2: Block Diagram Table 1: Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type P U DI U DI P AI AO U DI O P U DI DO P DO DO P DO P Name VSS SEL_CD PD/SCL VSS XIN XOUT OE/SDA VDD MODE CLK_D VSS CLK_C CLK_B VDD CLK_A VDD Description Ground Selects one of two programmed PLL C, Mux C/D and post divider C/D combinations Power-down input (run-mode) or serial interface clock input (program mode) Ground Crystal oscillator feedback Crystal oscillator drive Output enable input (run mode) or serial interface data input/output (program mode) Power supply (5 V to 3.3 V) Selects either program mode (low) or run mode (high) D clock output Ground C clock output B clock output Power supply (5 V to 3.3 V) A clock output Power supply (5 V to 3.3 V) Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = ThreeLevel Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin Rev. 3 | Page 2 of 28 | www.onsemi.com FS6370 3.0 Functional Block Description 3.1 Phase Locked Loops (PLLs) Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is often referred to as the modulus, and is denoted as NR for the reference divider. The divided reference is fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close the loop. Figure 3: PLL Block Diagram The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is: 3.1.1. Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divideddown frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h. 3.1.2. Feedback Divider The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a pre-scaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight pre-scaler could have been used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to Rev. 3 | Page 3 of 28 | www.onsemi.com FS6370 achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and acquisition time. To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-modulus pre-scaler. The A-counter controls the modulus of the pres-caler. If the value programmed into the A-counter is A, the pre-scaler will be set to divide by N+1 for A pre-scaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and the cycle begins again. Note that N=8, and A and M are binary numbers. Figure 4: Feedback Divider Suppose that the A-counter is programmed to zero. The modulus of the pre-scaler will always be fixed at N; and the entire modulus of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the pre-scaler to switch to a divide-by-N+1 for its first divide cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the feedback divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Re-Flow Solder Profile Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) Symbol VDD VI VO IIK IOK TS TA TJ Min. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55 Max. 7 VDD+0.5 VDD+0.5 50 50 150 125 150 260 2 Units V V V mA mA °C °C °C °C kV Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability. CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance Serial Data Transfer Rate Output Driver Load Capacitance CL Symbol VDD TA fXIN CXL Parallel resonant, AT cut Standard mode 10 Conditions/Descriptions 5 V ± 10% 3.3 V ± 10% Min. 4.5 3 0 5 18 100 15 Typ. 5 3.3 Max. 5.5 3.6 70 27 °C MHz pF kb/s pF Units V Rev. 3 | Page 17 of 28 | www.onsemi.com FS6370 Table 12: DC Electrical Specifications Parameter Overall Supply Current, Dynamic IDD IDD(write) IDD(read) IDDL VDD = 5.5V, fCLK = 50MHz ; CL = 15pF See Figure 11 for more information Additional operating current demand, EEPROM program mode, VDD = 5.5 V Additional operating current demand, EEPROM program mode, VDD = 5.5 V VDD = 5.5V, powered down via PD pin 43 2 1 0.3 mA mA mA mA Symbol Conditions/Description Min. Typ. Max. Units Supply Current, Write Supply Current, Read Supply Current, Static Dual Function I/O (P Run mode (PD, OE) Register program mode (SDA, SCL) EEPROM prodgram mode (SDA, SCL) Run mode (PD, OE) Register program mode (SDA, SCL) EEPROM prodgram mode (SDA, SCL) Run mode (PD, OE) Register program mode (SDA, SCL) Register program mode (SDA, SCL) High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) IIH IIL IOL Run/register program mode EEPROM program mode VIL = 0V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V 3.85 2.52 3.85 2.52 3.85 2.52 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 VSS-0.3 2.20 1.44 2.20 1.44 0.275 0.18 -1 -1 -20 -36 26 3.0 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 VDD+0.3 1.65 1.08 1.65 1.08 1.65 1.08 V V High-Level Input Voltage VIH Low-Level Input Voltage VIL Hysteresis Voltage Vhys V 1 1 -80 μA µA mA Run/register program mode, VOL = 0.4V EEPROM program mode, VOL = 0.4V Mode and Frequency Select Inputs (MODE, SEL_CD) High-Level Input Voltage VIH VDD = 5.5 V VDD = 3.6 V VDD = 5.5 V VDD = 3.6 V 2.4 2.0 VSS-0.3 VSS-0.3 -1 -20 Conditions/Description Min. VDD+0.3 VDD+0.3 0.8 0.8 1 -36 Type. V Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Parameter VIL IIH IIL Symbol V μA μA Units -80 Max. Rev. 3 | Page 18 of 28 | www.onsemi.com FS6370 Table 12: DC Electrical Specifications (Continued) Crystal Oscillator Feedback (XIN) Threshold Bias Voltage VTH VDD = 5.5 V VDD = 3.6 V VDD = 5.5 V VDD = 5.5 V, oscillator powered down 5 -25 As seen by an external crystal connected to XIN and XOUT As seen by an external clock driver on XOUT; XIN unconnected -54 18 36 2.9 1.7 54 15 -75 V mA mA µA pF pF High-Level Input Current Low-Level Input Current Crystal Loading Capacitance * Input Loading Capacitance * Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current IIH IIL CL(xtal) CL(XIN) IOH IOL VDD = V(XIN) = 5.5 V, VO = 0 V VDD = 5.5 V, V(XIN = VO = 5.5 V 10 -10 21 -21 30 -30 mA mA Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current * Short Circuit Sink Current * IOH IOL zOH zOL IZ ISCH ISCL VDD = 5.5 V , VO = 0 V; shorted for 30s, max VDD = VO = 5.5 V; shorted for 30s, max. VO = 2.4 V VO = 0.4 V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low -10 -150 123 -125 23 29 27 10 mA mA Ω µA mA mA Voltage (V) 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 Low Drive Current (mA) Min. 0 9 22 29 39 44 51 55 60 62 65 65 66 67 68 69 Typ. 0 11 25 34 46 52 61 66 73 77 81 83 85 87 88 89 91 Max. 0 12 29 40 55 64 76 83 92 97 104 108 112 117 119 120 121 123 Voltage (V) 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 High Drive Current (mA) Min. -87 -85 -83 -80 -74 -65 -61 -53 -48 -39 -32 -21 -13 0 Typ. -112 -110 -108 -104 -97 -88 -84 -77 -71 -62 -55 -44 -36 -24 -15 0 Max. -150 -147 -144 -139 -131 -121 -116 -108 -102 -92 -85 -74 -65 -52 -43 -28 -11 0 The data in this table represents nominal characterization data only. Figure 10: CLK_A, CLK_B, CLK_C, CLK_D Clock Output Rev. 3 | Page 19 of 28 | www.onsemi.com FS6370 Figure 11: Dynamic Current vs. Output Frequency Rev. 3 | Page 20 of 28 | www.onsemi.com FS6370 Table 13: AC Timing Specifications Parameter Overall EEPROM Write Cycle Time Output Frequency * Twc fO VDD = 5.5 V VDD = 3.6 V 0.8 0.8 40 40 400 LFTC bit = 0 LFTC bit = 1 tr VO = 0.5 V to 4.5 V; CL = 15pF VO = 0.3 V to 3.0 V; CL = 15pF VO = 4.5 V to 0.5 V; CL = 15pF VO = 3.0 V to 0.3 V; CL = 15pF 1 1 Output active from power-up, RUN mode via PD pin After last register is written, register program mode 100 1 7 20 2.0 2.1 1.8 1.9 8 8 ns ns μs ms 4 150 100 230 170 MHz/V μs MHz ms MHz Symbol Conditions/Description Clock (MHz) Min. Typ. Max. Units VCO Frequency * VCO Gain * Loop Filter Time Constant * fVCO AVCO VDD = 5.5 V VDD = 3.6 V Rise Time * ns Fall Time * Tristate Enable Delay * Tristate Disable Delay * Clock Stabilization Time * Divider Modulus Feedback Divider Reference Divider Post Divider NF NR NP tf tPZL, tPZH tPZL, tPZH tSTB ns See also Error! Reference source not found. 8 1 2047 255 50 See also Error! Reference source not found. 1 Clock Output (PLL A clock via CLK_A pin) Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 100 100 50 100 50 45 45 55 % Jitter, Long Term (σy(τ)) * Tj(LT) ps 165 110 ps 390 Jitter, Period (peak-peak) * tj(ΔP) Clock Output (PLL B clock via CLK_B pin) Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, =14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) 100 100 60 100 60 45 45 55 % Jitter, Long Term (σy(τ)) * Tj(LT) ps 75 120 ps 400 Jitter, Period (peak-peak) * tj(ΔP) Rev. 3 | Page 21 of 28 | www.onsemi.com FS6370 Table 13: AC Timing Specifications (Continued) Parameter Symbol Conditions/Description Clock (MHz) Min. Typ. Max. Units Clock Output (PLL C clock via CLK_C pin) Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs active From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) 100 100 40 100 40 45 45 55 % Jitter, Long Term (σy(τ))* Tj(LT) ps 105 120 ps 440 Jitter, Period (peak-peak)* tj(ΔP) Clock Output (Crystal Oscillator via CLK_D pin) Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 14.318 45 55 % On rising edges 500µs apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no other PLLs 14.318 20 active Tj(LT) ps Jitter, Long Term (σy(τ))* From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, 14.318 40 C=40MHz) From rising edge to the next rising edge at 2.5V, CL=15pF, 14.318 90 fXIN=14.318MHz, no other PLLs active Jitter, Period (peak-peak)* ps From rising edge to the next rising edge at 2.5V, CL=15pF, tj(ΔP) fXIN=14.318MHz, all other PLLs active (A=50MHz, B=60MHz, 14.318 450 C=40MHz) Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical. Table 14: Serial Interface Timing Specifications Parameter Clock frequency Bus free time between STOP and START Set up time, START (repeated) Hold time, START Set up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set up time, STOP Symbol fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO Conditions/Description SCL Min. 0 4.7 4.7 4.0 Max. 100 Units kHz μs μs μs ns μs SDA SDA Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP 250 0 3.5 1000 300 4.0 4.7 4.0 μs ns ns μs μs μs SDA, SCL SDA, SCL SCL SCL Rev. 3 | Page 22 of 28 | www.onsemi.com FS6370 Figure 12: Bus Timing Data Figure 13: Data Transfer Sequence Rev. 3 | Page 23 of 28 | www.onsemi.com FS6370 11.0 Package Information for Both ‘Green’ and ‘Non-Green’ Table 15: 16-pin SOIC (0.150") Package Dimensions Dimension Inches Min. A A1 A2 B C D E e H h L Θ 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 Max. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 Millimeters Min. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 Max. 1.73 0.249 1.55 0.49 0.249 9.98 3.99 0.050 BSC 0.230 0.010 0.016 0° 0.244 0.016 0.035 8° 1.27 BSC 5.84 0.25 0.41 0° 6.20 0.41 0.89 8° Table 16: 16-pin SOIC (0.150") Package Characteristics Parameter Thermal Impedance, Junction to Free-Air 16-pin 0.150” SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Symbol ΘJA L11 L12 C11 Conditions/Description Air flow = 0 m/s Corner lead Center lead Any lead to any adjacent lead Any lead to VSS Typ. 109 4.0 3.0 0.4 0.5 Units °C/W nH nH pF 12.0 Ordering Information Part Number FS6370-01G-XTD Package 16-pin (0.150”) SOIC (green, ROHS or lead free packaging) 16-pin (0.150”) SOIC (green, ROHS or lead free packaging) Shipping Configuration Tube/Tray Temperature Range 0°C to 70°C (Commercial) FS6370-01G-XTP Tape & Reel 0°C to 70°C (Commercial) Rev. 3 | Page 24 of 28 | www.onsemi.com FS6370 13.0 Demonstration Software Windows 3.1x/95/98-based software is available from ON Semiconductor that illustrates the capabilities of the FS6370. The software can operate under Windows NT. Contact your local sales representative for more information. 13.1 Software Requirements • PC running MS Windows 3.1x or 95/98. Software also runs on Windows NT in a calculation mode only. • 1.8MB available space on hard drive C. 13.2 Software Installation Instructions At the appropriate disk drive prompt (A:\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software. 13.3 Demo Program Operation Launch the fs6370.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6370 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only. The FS6370 demonstration hardware is no longer available nor supported. The opening screen is shown in Figure 14 . Figure 14: Opening Screen Rev. 3 | Page 25 of 28 | www.onsemi.com FS6370 13.3.1. Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3.3 V or 5 V), and the desired maximum output frequency error. Pressing calculate solutions generates several possible divider and VCO-speed combinations. Figure 15: PLL Screen For a 100 MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In this example, highlight solution #7. Notice the VCO operates at 200MHz with a post divider of 2 to obtain an optimal 50 percent duty cycle. Now choose which mux and post divider to use (that is, choose an output pin for the 100 MHz output). Selecting A places the PostDiv value in solution #7 into post divider A and switches mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in solution #7. Note that mux A has been switched to PLL A and the post divider A has the chosen 100MHz output displayed. Repeat the steps for PLL B. PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected by the logic level on the SEL_CD pin, as are the post dividers C and D (see Section 4.2 for more detail). Rev. 3 | Page 26 of 28 | www.onsemi.com FS6370 Figure 16: Post Divider Menu Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output. Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7. The EEPROM settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in Figure 17. Individual bits can be poked, or the entire register value can be changed. Figure 17: Register Screen Rev. 3 | Page 27 of 28 | www.onsemi.com FS6370 14.0 Revision History Revision Date Modification ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Rev. 3 | Page 28 of 28 | www.onsemi.com