FS6377-01G-XTD

DATA SHEET www.onsemi.com Programmable 3-PLL Clock Generator IC FS6377 SOIC−16 CASE 751BA General Description The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three I2 C−programmable phase locked loops (PLLs) feeding four programmable muxes and post dividers provide a high degree of flexibility. w Three On−Chip PLLs with Programmable Reference and Feedback w w w w w 16 FS6377−xxG AWLYWWG 1 Features w w w w MARKING DIAGRAM Dividers Four Independently Programmable Muxes and Post Dividers I2C−Bus Serial Interface Programmable Power−Down of All PLLs and Output Clock Drivers One PLL and Two Mux/Post−Divider Combinations can be Modified by SEL_CD Input Tristate Outputs for Board Testing 5 V to 3.3 V Operation Accepts 5 MHz to 27 MHz Crystal Resonators Commercial and Industrial Temperature Ranges Offered These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant xx A WL Y WW G = 01 or 01i = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† FS6377−01G−XTD SOIC−16 (Pb-Free) 48 Units / Tube FS6377−01G−XTP SOIC−16 (Pb-Free) 3000 / Tape & Reel FS6377−01iG−XTD SOIC−16 (Pb-Free) 48 Units / Tube †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 September, 2021 − Rev. 5 1 Publication Order Number: FS6377/D FS6377 SDA 1 16 SCL SEL_CD 2 15 CLK_A PD 3 14 VDD VSS 4 13 CLK_B XIN 5 12 CLK_C XOUT 6 11 VSS OE 7 10 CLK_D VDD 8 9 ADDR FS6377 16−PIN (0.150”) SOIC Figure 1. Pin Configuration Table 1. PIN DESCRIPTION (Note 1) Pin Type Name 1 DIUO SDA Description 2 DIU SEL_CD 3 DIU PD 4 P VSS Ground 5 AI XIN Crystal oscillator input 6 AO XOUT 7 DIU OE 8 P VDD 9 DIU ADDR Address select 10 DO CLK_D D clock output 11 P VSS 12 DO CLK_C C clock output 13 DO CLK_B B clock output 14 P VDD 15 DO CLK_A 16 DIU SCL Serial interface data input/output Selects one of two PLL C, mux D/C and post divider C/D combinations Power-down input Crystal oscillator output Output enable input Power supply (5 V to 3.3 V) Ground Power supply (5 V to 3.3 V) A clock output Serial interface clock output 1. Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull−up; DID = Input with Internal Pull−down; DIO = Digital Input/Output; DI−3 = Three−level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin. www.onsemi.com 2 FS6377 Figure 2. Block Diagram FUNCTIONAL BLOCK DESCRIPTION Phase Locked Loops (PLLs) Each of the three on−chip PLLs is a standard phase− and frequency−locked loop architecture that multiplies a reference frequency to a desired frequency by a ratio of integers. This frequency multiplication is exact. As shown in Figure 3 each PLL consists of a reference divider, a phase−frequency detector (PFD), a charge pump, an internal loop filter, a voltage−controlled oscillator (VCO), and a feedback divider. During operation, the reference frequency (fREF), generated by the on−board crystal oscillator, is first reduced by the reference divider. The divider value is called the “modulus,” and is denoted as NR for the reference divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high speed, low noise, continuously variable frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close the loop. The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is: f VCO + f REF ǒNN Ǔ F R Figure 3. PLL Diagram Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided− down frequency to the PFD. The reference divider is an 8−bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide−by−256 can also be achieved by programming the eight bits to 00h. Feedback Divider The feedback divider is based on a dual−modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high−speed pre−divider (also called a prescaler) is placed between the VCO and the programmable feedback (eq. 1) www.onsemi.com 3 FS6377 Next, suppose that the A−counter is programmed to a one. This causes the prescaler to switch to a divide−by−N+1 for its first divide cycle and then revert to a divide−by−N. In effect, the A−counter absorbs (or “swallows”) one extra clock during the entire cycle of the feedback divider. The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A VDD) −50 50 mA IOK Output clamp current, dc (VI < 0 or VI > VDD) −50 50 mA TS Storage temperature range (non−condensing) −65 150 °C TA Ambient temperature range, under bias −55 125 °C TJ Junction temperature 150 °C VDD Parameter Re−flow solder profile Per IPC/JEDEC J−STD−020B Input static discharge voltage protection (MIL−STD 883E, Method 3015.7) 2 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. WARNING: ELETROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high−energy electrostatic discharge. Table 11. RECOMMENDED OPERATING RANGES Symbol VDD Parameter Description Min Type Max Unit 5 3.3 5.5 3.6 V 70 85 °C 27 MHz Supply voltage 5V ± 10% 3.3V ± 10% 4.5 3 TA Ambient operating temperature range Commercial Industrial 0 −40 fXIN Crystal resonator frequency CXL Crystal resonator load capacitance Parallel resonant, AT cut Serial data transfer rate Standard mode CL 5 Output driver load capacitance 18 10 pF 100 kb/s 15 pF Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 13 FS6377 Table 12. DC CHARACTERISTICS (Unless otherwise stated, VDD = 5.0 V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested on any specific limits. Min. and max. characterization data are ±3s from typical. Negative currents indicate current flows out of the device.) Symbol Parameter Characteristic Min Typ Max Unit OVERALL IDD Supply current, dynamic, with load outputs VDD = 5.5 V, fCLK = 50 MHz, CL = 15 pF See Figure 10 for more information 43 mA IDDL Supply current, static VDD = 5.5 V, device powered down 0.3 mA POWER−DOWN, OUTPUT ENABLE PINS (PD, OE) VIH High−level input voltage VDD = 5.5 V VDD = 3.6 V 3.85 2.52 VDD + 0.3 VDD + 0.3 V VIL Low−level input voltage VDD = 5.5 V VDD = 3.6 V VSS − 0.3 VSS − 0.3 1.65 1.08 V Vhys Hysteresis voltage VDD = 5.5 V VDD = 3.6 V IIH High−level input current IIL Low−level input current (pull−up) 2.20 1.44 −1 VIL = 0 V −20 −36 V 1 mA −80 mA SERIAL INTERFACE I/O (SCL, SDA) VIH High−level input voltage VDD = 5.5 V VDD = 3.6 V 3.85 2.52 VDD + 0.3 VDD + 0.3 V VIL Low−level input voltage VDD = 5.5 V VDD = 3.6 V VSS − 0.3 VSS − 0.3 1.65 1.08 V Vhys Hysteresis voltage VDD = 5.5 V VDD = 3.6 V 2.20 1.44 IIH High−level input current −1 IIL Low−level input current (pull−up) VIL = 0 V IOL Low−level output sink current (SDA) VOL = 0.4 V, VDD = 5.5 V −20 −36 V 1 mA −80 mA 26 mA MODE AND FREQUENCY SELECT INPUTS (ADDR, SEL_CD) VIH High−level input voltage VDD = 5.5 V VDD = 3.6 V 2.4 2.0 VDD + 0.3 VDD + 0.3 V VIL Low−level input voltage VDD = 5.5 V VDD = 3.6 V VSS − 0.3 VSS − 0.3 0.8 0.8 V IIH High−level input current −1 1 mA IIL Low−level input current (pull−up) −20 −80 mA −36 CRYSTAL OSCILLATOR FEEDBACK (XIN) VTH Threshold bias voltage VDD = 5.5 V VDD = 3.6 V 2.9 1.7 IIH High−level input current VDD = 5.5 V VDD = 5.5 V, oscillator powered down IIL Low−level input current VDD = 5.5 V CL(xtal) Crystal loading capacitance* As seen by an external crystal connected to XIN and XOUT 18 pF CL(XIN) Input loading capacitance* As seen by an external clock driver on XOUT; XIN unconnected 36 pF 5 −25 www.onsemi.com 14 54 −54 V 15 −75 mA mA mA FS6377 Table 12. DC CHARACTERISTICS (continued) (Unless otherwise stated, VDD = 5.0 V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested on any specific limits. Min. and max. characterization data are ±3s from typical. Negative currents indicate current flows out of the device.) Symbol Parameter Characteristic Min Typ Max Unit CRYSTAL OSCILLATOR DRIVER (XOUT) IOH High−level output source current VDD = V(XIN) = 5.5V, VO = 0 V 10 21 30 mA IOL Low−level output sink current VDD = 5.5 V, V(XIN) = 0 V, VO = 5.5 V −10 −21 −30 mA CLOCK OUTPUTS (CLK_A, CLK_B, CLK_C, CLK_D) IOH High−level output source current VO = 2.4 V −125 mA IOL Low−level output sink current VO = 0.4 V 23 mA ZOH Output impedance VO = 0.5 VDD Output driving high Output driving low 29 27 W ZOL IZ Tristate output current −10 −10 ISCH Short circuit source current* VDD = 5.5 V, VO = 0 V; shorted for 30 s, max. −150 ISCL Short circuit sink current* VDD = VO = 5.5 V; shorted for 30 s, max. 123 Low Drive Current (mA) Voltage Min. Typ. Max. (V) 0 0 0 0 0.2 9 11 12 0.5 22 25 29 0.7 29 34 40 1 39 46 55 1.2 44 52 64 1.5 51 61 76 1.7 55 66 83 2 60 73 92 2.2 62 77 97 2.5 65 81 104 2.7 65 83 108 3 66 85 112 3.5 67 87 117 4 68 88 119 4.5 69 89 120 5 91 121 5.5 123 mA mA mA High Drive Current (mA) Voltage Min. Typ. Max. (V) 0 −87 −112 −150 0.5 −85 −110 −147 1 −83 −108 −144 1.5 −80 −104 −139 2 −74 −97 −131 2.5 −65 −88 −121 2.7 −61 −84 −116 3 −53 −77 −108 3.2 −48 −71 −102 3.5 −39 −62 −92 3.7 −32 −55 −85 4 −21 −44 −74 4.2 −13 −36 −65 4.5 0 −24 −52 4.7 −15 −43 5 0 −28 5.2 −11 5.5 0 The data in this table represents nominal characterization data only. Figure 9. CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs www.onsemi.com 15 FS6377 VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency= 200MHz, CL = 17pF except where noted VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL = 17pF except where noted Figure 10. Dynamic Current vs Output Frequency www.onsemi.com 16 FS6377 Table 13. AC TIMING SPECIFICATIONS (Unless otherwise stated, VDD = 5.0 V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3s from typical.) Symbol Parameter Characteristic Clock Min Typ Max Unit OVERALL fO fVCO AVCO Output frequency* VDD = 5.5 V VDD = 3.6 V 0.8 0.8 150 100 MHz VCO frequency* VDD = 5.5 V VDD = 3.6 V 40 40 230 170 MHz 400 MHz/V Loop filter time constant* VCO gain* LFTC bit = 0 LFTC bit = 1 7 20 ms tr Rise time* VO = 0.5 V to 4.5 V; CL = 15 pF VO = 0.3 V to 3.0 V; CL = 15 pF 1.9 1.6 ns tr Fall time* VO = 4.5 V to 0.5 V; CL = 15 pF VO = 3.0 V to 0.3 V; CL = 15 pF 1.8 1.5 ns tPZL, tPZH Tristate enable delay* 1 8 ns tPZL, tPZH Tristate disable delay* 1 8 ns tSTB Clock stabilization time* 1 ms ms Output active from power−up, via PD pin After last register is written 100 DIVIDER MODULUS NF Feedback divider NR Reference divider NP Post divider See Table 2 See Table 8 8 2047 1 255 1 50 45 55 CLOCK OUTPUTS (PLL A CLOCK VIA CLK_A PIN) APPROXIMATE tj(LT) tj(DP) Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5 V) to one clock period 100 Jitter, long term (sy(t))* On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, no other PLLs active 100 45 On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, all other PLLs active (B = 60 MHz, C = 40 MHz, D = 14.318 MHz) 50 165 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, NF= 220, NR = 63, NPX = 50, no other PLLs active 100 110 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, all other PLLs active (B = 60 MHz, C = 40 MHz, D = 14.318 MHz) 50 390 Jitter, period (peak− peak)* % ps ps CLOCK OUTPUTS (PLL B CLOCK VIA CLK_B PIN) APPROXIMATE tj(LT) Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5 V) to one clock period 100 Jitter, long term (sy(t))* On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, no other PLLs active 100 45 On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318MHz, NF = 220, NR = 63, NPX = 50, all other PLLs active (A = 50 MHz, C = 40 MHz,D = 14.318 MHz) 60 75 www.onsemi.com 17 45 55 % ps FS6377 Table 13. AC TIMING SPECIFICATIONS (continued) (Unless otherwise stated, VDD = 5.0 V ±10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3s from typical.) Symbol Parameter Characteristic Clock Min Typ Max Unit CLOCK OUTPUTS (PLL B CLOCK VIA CLK_B PIN) APPROXIMATE tj(DP) Jitter, period (peak− peak)* From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, no other PLLs active 100 120 From rising edge to the next rising edge at 2.5 V, CL = 15pF, fXIN = 14.318MHz,NF = 220, NR = 63, NPX = 50, all other PLLs active (A = 50 MHz, C = 40 MHz, D = 14.318 MHz) 60 400 ps CLOCK OUTPUTS (PLL C CLOCK VIA CLK_C PIN) APPROXIMATE tj(LT) tj(DP) Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5 V) to one clock period 100 Jitter, long term (sy(t))* On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, no other PLLs active 100 45 On rising edges 500 ms apart at 2.5V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, NF= 220, NR = 63, NPX = 50, all other PLLs active (A = 50 MHz, B = 60 Mhz,D = 14.318 MHz) 40 105 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63,NPX = 50, no other PLLs active 100 120 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, NF = 220, NR = 63, NPX = 50, all other PLLs active (A = 50 MHz, B = 60 MHz, D = 14.318 MHz) 40 440 Jitter, period (peak− peak)* 45 55 % ps ps CLOCK OUTPUTS (CRYSTAL OSCILLATOR VIA CLK_D PIN) APPROXIMATE tj(LT) tj(DP) Duty cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5 V) to one clock period 14.318 Jitter, long term (sy(t))* On rising edges 500 ms apart at 2.5 V relative to an ideal clock, CL = 15 pF, fXIN = 14.318 MHz, no other PLLs active 14.318 20 From rising edges to the next at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, all other PLLs active (A = 50 MHz, B = 60 MHz, C = 40 MHz) 14.318 40 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, no other PLLs active 14.318 90 From rising edge to the next rising edge at 2.5 V, CL = 15 pF, fXIN = 14.318 MHz, all other PLLs active (A = 50 MHz, B = 60 MHz, C = 40 MHz) 14.318 450 Jitter, period (peak− peak)* www.onsemi.com 18 45 55 % ps ps FS6377 Table 14. SERIAL INTERFACE TIMING SPECIFICATIONS (Unless otherwise stated, all power supplies = 3.3 V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not currently production tested to any specific limits. Min. and max. characterization data are ±3s from typical.) Min Symbol Parameter fSCL Clock frequency tBUF Characteristic SCL Max Standard Mode 0 100 Unit kHz Bus free time between STOP and START 4.7 ms tsu:STA Set−up time, START (repeated) 4.7 ms tnd:STA Hold time, START 4.0 ms tsu:DAT Set−up time, data input SDA 250 ns thd:DAT Hold time, data input SDA 0 ms tAA Output data valid from clock Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP tR Rise time, data and clock tF Fall time, data and clock tHI High time, clock SCL 4.0 ms tLO Low time, clock SCL 4.7 ms 4.0 ms Tsu:STO 3.5 ms SDA, SCL 1000 ns SDA, SCL 300 ns Set−up time, STOP Figure 11. Bus Timing Data Figure 12. Data Transfer Sequence Table 15. 16−PIN SOIC (0.150”) PACKAGE CHARACTERISTICS Symbol Type Unit QJA Thermal impedance, junction to free− air16−pin 0.150” SOIC Parameter Air flow = 0m /s Description 110 °C/W L11 Lead inductance, self Corner lead Center lead 4.0 3.0 nH nH L12 Lead inductance, mutual Any lead to any adjacent lead 0.4 nH C11 Lead capacitance, bulk Any lead to VSS 0.5 pF www.onsemi.com 19 FS6377 DEMONSTRATION SOFTWARE Windows XP− (and earlier) based software is available from onsemi that illustrates the capabilities of the FS6377 and aids in application development. Contact your local sales representative for more information. Software Requirements • PC running MS Windows 95/98, 98 SE, ME, NT4, • 2000, XP Home Edition, or XP Professional Edition. 1.8MB available space on hard drive C. Demo Program Operation Launch the demo program from the website. Note that the parallel port cannot be accessed if your machine is not connected to the demo board. A warning message will appear as shown in Figure 13. Clicking “Ignore” starts the program for calculation only. The FS6377 demo hardware is available on a limited basis for demonstration by an onsemi field applications engineer, but is no longer available for purchase.. The opening screen is shown in Figure 14. Figure 14. Opening Screen Example Programming Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop−up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3.3 V or 5 V) and the desired maximum output frequency error. Pressing Calculate Solutions generates several possible divider and VCO−speed combinations. Figure 13. Warning Message− Click “Ignore” Figure 15. PLL Screen For a 100 MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200 MHz with a post divider of two to obtain an optimal 50 percent duty cycle. www.onsemi.com 20 FS6377 Now choose which mux and post divider to use (that is, choose an output pin for the 100 MHz output). Selecting A places the PostDiv value in Solution #7 into post divider A and switches mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that mux A has been switched to PLL A and the post divider A has the chosen 100 MHz output displayed. Repeat the steps for PLL B. PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected by the logic level on the SEL_CD pin, as are the post dividers C and D. Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output. Clicking on post divider A reveals a pull−down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical menu is shown in Figure 16. The range of possible post divider values is also given in Table 7. The register settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in Figure 17. Individual bits can be poked, or the entire register value can be changed. Figure 17. Register Screen Figure 16. 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