FS7145-02G-XTP

FS7140, FS7145 Programmable PhaseLocked Loop Clock Generator Description The FS7140 or FS7145 is a monolithic CMOS clock generator/ regenerator IC designed to minimize cost and component count in a variety of electronic systems. Via the I2C−bus interface, the FS7140/45 can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS7140/45 the most flexible stand−alone PLL clock generator available. Features • Extremely Flexible and Low−jitter Phase Locked Loop (PLL) • • • • • • • • Frequency Synthesis No External Loop Filter Components Needed 150 MHz CMOS or 340 MHz PECL Outputs Completely Configurable via I2C−bus Up to Four FS714x can be Used on a Single I2C−bus 3.3 V Operation Independent On−chip Crystal Oscillator and External Reference Input Very Low “Cumulative” Jitter Pb−Free Packages are Available Applications • • • • Precision Frequency Synthesis Low−frequency Clock Multiplication Video Line−locked Clock Generation Laser Beam Printers (FS7145) © Semiconductor Components Industries, LLC, 2011 October, 2011 − Rev. 7 http://onsemi.com SOIC−16 01 SUFFIX CASE 751BA SSOP−16 02 SUFFIX CASE 565AE PIN CONNECTIONS SCL SDA ADDR0 VSS XIN XOUT ADDR1 VDD 1 CLKN CLKP VDD * REF VSS N/C IPRG (Top View) * FS7140 pin 13 = N/C * FS7145 pin 13 = SYNC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. 1 Publication Order Number: FS7140/D FS7140, FS7145 Figure 1. Device Block Diagram Table 1. PIN DESCRIPTIONS* Pin Type Name Description 1 DI SCL Serial interface clock (requires an external pull−up) 2 DIO SDA Serial interface data input/output (requires an external pull−up) 3 DID ADDR0 4 P VSS Ground 5 AI XIN Crystal oscillator feedback 6 AO XOUT Crystal oscillator drive 7 DID ADDR1 Address select bit “1” 8 P VDD Power supply (+3.3 V nominal) PECL current drive programming Address select bit “0” 9 AI IPRG 10 − n/c 11 P VSS Ground 12 DIU REF Reference frequency input 13 − DIU n/c SYNC FS7140 = No connection FS7145 = Synchronization input 14 P VDD Power supply (+3.3 V nominal) 15 DO CLKP Clock output 16 DO CLKN Inverted clock output No connection *Key: AI: Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull−up; DID = Input with Internal Pull−down; DIO = Digital Input/Output; DI−3 = Three−Level Digital Input; DO = Digital Output; P = Power/Ground; # = Active Low Pin http://onsemi.com 2 FS7140, FS7145 ELECTRICAL SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Min Typ Max Units Supply voltage, dc (VSS = ground) VSS − 0.5 4.5 V V1 Input voltage, dc VSS − 0.5 VDD + 0.5 V VO Output voltage, dc VSS − 0.5 VDD + 0.5 V IIK Input clamp current, dc (VI < 0 or VI > VDD) −50 50 mA IOK Output clamp current, dc (VI < 0 or VI > VDD) −50 50 mA TS Storage temperature range (non−condensing) −65 150 °C TA Ambient temperature range, under bias −55 125 °C TJ Junction temperature 150 °C 2 kV Re−flow solder profile Per IPC/JEDEC J−STD−020B Input static discharge voltage protection (MIL−STD 883E, Method 3015.7) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. WARNING: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 3. OPERATING CONDITIONS Symbol VDD TA Parameter Supply voltage Ambient operating temperature range Min Typ Max Units 3.0 3.3 3.6 V 70 °C 0 http://onsemi.com 3 FS7140, FS7145 Table 4. DC ELECTRICAL SPECIFICATIONS (Note 1) Symbol Conditions/Description Supply current, dynamic IDD CMOS mode; FXTAL = 15 MHz; FVCO = 400 MHz; FCLK = 200 MHz; does not include load current 35 Supply current, static IDDL SHUT1, SHUT2 bit both “1” 400 Parameter Min Typ Max Units OVERALL mA 700 mA SERIAL COMMUNICATION I/O (SDA, SCL) High−level input voltage VIH Low−level input voltage VIL Hysteresis voltage Vhys Input leakage current II Low−level output sink current (SDA) IOL 0.8*VDD V 0.2*VDD 0.33*VDD SDA, SCL in read condition SDA in acknowledge condition; VSDA = 0.4 V −10 5 V V +10 14 mA mA ADDRESS SELECT INPUT (ADDR0, ADDR1) High−level input voltage VIH VDD−1.0 Low−level input voltage VIL High−level input current (pull−down) IIH VADDRx = VDD Low−level input current IIL VADDRx = 0 V V 0.8 30 −1 V mA 1 mA REFERENCE FREQUENCY INPUT (REF) High−level input voltage VIH Low−level input voltage VIL VDD−1.0 High−level input current IIH VREF = VDD Low−level input current (pull−down) IIL VREF = 0 V V −1 0.8 V 1 mA −30 mA SYNC CONTROL INPUT (SYNC) High−level input voltage VIH VDD−1.0 Low−level input voltage VIL High−level input current IIH VREF = VDD Low−level input current (pull−down) IIL VREF = 0 V V −1 0.8 V 1 mA −30 mA VDD/2 V mA CRYSTAL OSCILLATOR INPUT (XIN) Threshold bias voltage VTH High−level input current IIH VXIN = VDD 40 Low−level input current IIL VXIN = GND −40 Crystal frequency FX Fundamental mode Recommended crystal load capacitance* CL(XTAL) mA 35 For best matching with internal crystal oscillator load MHz 16−18 pF −8.5 mA 11 mA CRYSTAL OSCILLATOR OUTPUT (XOUT) High−level output source current IOH VXOUT = 0 Low−level output sink current IOL VXOUT = VDD IIL VIPRG = 0 V; PECL mode PECL CURRENT PROGRAM I/O (IPRG) Low−level input current −10 10 mA CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP) High−level output source current IOH VO = 2.0 V 19 mA 1. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. Negative currents indicate flows out of the device. http://onsemi.com 4 FS7140, FS7145 Table 4. DC ELECTRICAL SPECIFICATIONS (Note 1) Parameter Symbol Conditions/Description Min Typ Max Units CLOCK OUTPUTS, CMOS MODE (CLKN, CLKP) Low−level output sink current IOL VO = 0.4 V −35 mA VDD/3 V CLOCK OUTPUTS, PECL MODE (CLKN, CLKP) IPRG bias voltage VIPRG VIPRG will be clamped to this level when a resistor is connected from VDD to IPRG IPRG bias current IIPRG IIPRG − (VVDD − VIPRG) / RSET Sink current to IPRG current ratio 3.5 mA 10 mA 13 Tristate output current IZ −10 1. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. Negative currents indicate flows out of the device. Table 5. AC TIMING SPECIFICATIONS (Note 2) Parameter Symbol Conditions/Description Min Typ Max Units 0 150 MHz 0 300 40 400 OVERALL Output frequency* fo(max) CMOS outputs PECL outputs VCO frequency* fVCO MHz CMOS mode rise time* tr CL = 7 pF 1 ns CMOS mode fall time* tf CL = 7 pF 1 ns PECL mode rise time* tr CL = 7 pF; RL = 65 ohm 1 ns PECL mode fall time* tf CL = 7 pF; RL = 65 ohm 1 ns REFERENCE FREQUENCY INPUT (REF) Input frequency FREF Reference high time tREHF 3 80 MHz ns Reference low time tREFL 3 ns TCLK SYNC CONTROL INPUT (SYNC) Sync high time tSYNCH For orderly CLK stop/start 3 Sync low time tSYNCL For orderly CLK stop/start 3 CLOCK OUTPUT (CLKN, CLKP) Duty cycle (CMOS mode)* Measured at 1.4 V 50 % Duty cycle (PECL mode)* Measured at zero crossings of (VCLKP − VCLKN) 50 % Jitter, long term (sy(t))* Jitter, period (peak−peak)* tj(LT) tj(DP) For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer using a 500 microsecond window, using statistics gathered over 1000 samples. ps FREF/NREF > 1000 kHz 25 ps FREF/NREF ^ 500 kHz 50 ps FREF/NREF ^ 250 kHz 100 ps FREF/NREF ^ 125 kHz 190 ps FREF/NREF ^ 62.5 kHz 240 ps FREF/NREF ^ 31.5 kHz 300 ps 40 MHz < VCO frequency < 100 MHz 75 ps VCO frequency > 100 MHz 50 ps 2. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. http://onsemi.com 5 FS7140, FS7145 Table 6. SERIAL INTERFACE TIMING SPECIFICATIONS (Note 3) Fast Mode Symbol Conditions/Description Min Max Units Clock frequency fSCL SCL 0 400 kHz Bus free time between STOP and START tBUF 1300 ns Set−up time, START (repeated) Tsu:STA 600 ns Hold time, START thd:STA 600 ns Set−up time, data input Tsu:DAT SDA 100 ns Hold time, data input thd:DAT SDA 0 ns Parameter Output data valid from clock tAA Rise time, data and clock tR SDA, SCL Fall time, data and clock tF SDA, SCL High time, clock tHI SCL 600 ns Low time, clock tLO SCL 1300 ns 600 ns Set−up time, STOP tsu:STO 900 ns 300 ns 300 ns 3. Unless otherwise stated, VDD = 3.3 V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. FUNCTIONAL BLOCK DIAGRAM Phase Locked Loop (PLL) A post divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is: The PLL is a standard phase− and frequency−locked loop architecture. The PLL consists of a reference divider, a phase−frequency detector (PFD), a charge pump, an internal loop filter, a voltage−controlled oscillator (VCO), a feedback divider, and a post divider. The reference frequency (generated by either the on−board crystal oscillator or an external frequency source), is first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then: ǒ Ǔǒ Ǔ f CLK + f REF 1 N Px Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider is a 12 bit divider, and can be programmed for any modulus from 1 to 4095 (divide by 1 not available on date codes prior to 0108). Feedback Divider The feedback divider is based on a dual−modulus divider (also called dual−modulus prescaler) technique. It permits division by any integer value between 12 and 16383. Simply program the FBKDIV register with the binary equivalent of the desired modulus. Selected moduli below 12 are also permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not available on date codes prior to 0108). f VCO f + REF NF NR This basic PLL equation can be rewritten as ǒ Ǔ f VCO + f REF NF NR NF NR Post Divider The post divider consists of three individually programmable dividers, as shown in Figure 2. http://onsemi.com 6 FS7140, FS7145 Figure 2. Post Divider Device Shutdown The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPX. NPX = NP1 x NP2 x NP3 The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). See Table 12 for additional information. Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared together. Serial communications capability is not disabled by either SHUT1 or SHUT2. Differential Output Stage The differential output stage supports both CMOS and pseudo−ECL (PECL) signals. The desired output interface is chosen via the programming registers. If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull−up resistors that are part of the Thévenin termination. Example Assume that it is desired to connect a PECL−type fanout buffer right next to the FS7140. Further assume: • VDD = 3.3 V • Desired VHI = 2.4 V • Desired VLO = 1.6 V • Equivalent RLOAD = 75 ohms Crystal Oscillator The FS7140 is equipped with a Pierce−type crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, crystals for other standard load capacitances may be used if great precision of the reference frequency (100 ppm or less) is not required. Reference Divider Source MUX The source of frequency for the reference divider can be chosen to be the device crystal oscillator or the REF pin by the REFDSRC bit. When not using the crystal oscillator, it is preferred to connect XIN to VSS. Do not connect to XOUT. When not using the REF input, it is preferred to leave it floating or connected to VDD. Then: R1 (from CLKP and CLKN output to VDD) = RLOAD * VDD / VHI = 75 * 3.3 / 2.4 = 103 ohms R2 (from CLKP and CLKN output to GND) = RLOAD * VDD / (VDD − VHI) = 75 * 3.3 / (3.3 − 2.4) = 275 ohms Rprgm (from VDD to IPRG pin) = 26 * (VDD * RLOAD) / (VHI − VLO) / 3 = 26 * (3.3 * 75) / (2.4 − 1.6) / 3 = 2.68 Kohms Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by the FBKDSRC bit. Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase relationship between the output clock and reference clock are desired (line−locked mode, for example). http://onsemi.com 7 FS7140, FS7145 SYNC Circuitry Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first−in, first−overwritten fashion. The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC (positive−going or negative−going) is supported. Example (positive−going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by control of the device post−divider. Phase resolution equal to 1/2 of the VCO period can be achieved (approximately down to 2 ns). Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. I2C−bus Control Interface This device is a read/write slave device meeting all Philips I2C−bus specifications except a ”general call.” The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. I2C−bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic−one corresponds to a nominal voltage of VDD, while a logic−zero corresponds to ground (VSS). I2C−bus Operation All programmable registers can be accessed randomly or sequentially via this bi−directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. The device accepts the following I2C−bus commands: Bus Conditions Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C−bus protocol. Slave Address After generating a START condition, the bus master broadcasts a seven−bit slave address followed by a R/W bit. The address of the device is: Not Busy A6 A5 A4 A3 A2 A1 A0 1 0 1 1 0 X X where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the same bus. Note that every device on an I2C−bus must have a unique address to avoid possible bus conflicts. Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven−bit device address is a logic−low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave’s address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. STOP Data Transfer A low to high transition of the SDA line while SCL input is high indicates a STOP condition. All commands to the device must be followed by a STOP condition. Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. http://onsemi.com 8 FS7140, FS7145 slave, the master is allowed to write up to eight bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven−bit address is a logic−low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave’s address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave’s address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic−high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight−bit word. The master does not acknowledge the transfer but does generate a STOP condition. Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven−bit address is a logic−low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave’s address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave’s address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic−high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven−bit device address is a logic−low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave’s address pointer. Following an acknowledge by the http://onsemi.com 9 FS7140, FS7145 Figure 3. Random Register Write Procedure Figure 4. Random Register Read Procedure Figure 5. Sequential Register Write Procedure Figure 6. Sequential Register Read Procedure http://onsemi.com 10 FS7140, FS7145 Programming Information All register bits are cleared to zero on power−up. All register bits may be read back as written. Table 7. FS7140 REGISTER MAP Address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Byte 7 Reserved (Bit 63) Must be set to “0” Reserved (Bit 62) Must be set to “0” Reserved (Bit 61) Must be set to “0” Reserved (Bit 60) Must be set to “0” Reserved (Bit 59) Must be set to “0” Reserved (Bit 58) Must be set to “0” Reserved (Bit 57) Must be set to “0” Reserved (Bit 56) Must be set to “0” Byte 6 Reserved (Bit 55) Must be set to “0” Reserved (Bit 54) Must be set to “0” SHUT2 (Bit 53) 0 = Normal 1 = Powered down Reserved (Bit 52) Must be set to “0” Reserved (Bit 51) Must be set to “0” Reserved (Bit 50) Must be set to “0” Reserved (Bit 49) Must be set to “0” Reserved (Bit 48) Must be set to “0” Byte 5 Reserved (Bit 47) Must be set to “0” LC (Bit 46) Loop filter cap select LR[1] (Bit 45) LR[0] (Bit 44) Reserved (Bit 43) Must be set to “0” Reserved (Bit 42) Must be set to “0” CP[1] (Bit 41) CP[0] (Bit 40) CMOS (Bit 39) 0 = PECL 1 = CMOS FBKDSRC (Bit 38) 0 = VCO output 1 = Post divider output FBKDIV[13] (Bit 37) 8192 FBKDIV[11] (Bit 35) 2048 FBKDIV[10] (Bit 34) 1024 FBKDIV[6] (Bit 30) 64 FBKDIV[5] (Bit 29) 32 Byte 4 Byte 3 FBKDIV[7] (Bit 31) 128 Loop filter resistor select FBKDIV[12] (Bit 36) 4096 Charge pump current select FBKDIV[9] (Bit 33) 512 FBKDIV[8] (Bit 32) 256 See the Feedback Divider section for disallowed FBKDIV values FBKDIV[4] (Bit 28) 16 FBKDIV[3] (Bit 27) 8 FBKDIV[2] (Bit 26) 4 FBKDIV[1] (Bit 25) 2 FBKDIV[0] (Bit 24) 1 POST1[1] (Bit 17) POST1[0] (Bit 16) See the Feedback Divider section for disallowed FBKDIV values Byte 2 POST2[3] (Bit 23) POST2[2] (Bit 22) POST2[0] (Bit 20) POST2[1] (Bit 21) POST1[3] (Bit 19) Modulus = N + 1 (N = 0 to 11); See Table 12 Byte 1 POST3[1] (Bit 15) POST3[0] (Bit 14) Modulus = 1, 2, 4 or 8; See Table 12 Byte 0 REFDIV[7] (Bit 7) 128 REFDIV[6] (Bit 6) 64 POST1[2] (Bit 18) Modulus = N + 1 (N = 0 to 11); See Table 12 SHUT1 (Bit 13) 0 = Normal 1 = Powered down REFDSRC (Bit 12) 0 = Crystal oscillator 1 = REF pin REFDIV[11] (Bit 11) 2048 REFDIV[10] (Bit 10) 1024 REFDIV[9] (Bit 9) 512 REFDIV[8] (Bit 8) 256 REFDIV[5] (Bit 5) 32 REFDIV[4] (Bit 4) 16 REFDIV[3] (Bit 3) 8 REFDIV[2] (Bit 2) 4 REFDIV[1] (Bit 1) 2 REFDIV[0] (Bit 0) 1 http://onsemi.com 11 FS7140, FS7145 Table 8. FS7145 REGISTER MAP Address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Byte 7 Reserved (Bit 63) Must be set to “0” Reserved (Bit 62) Must be set to “0” Reserved (Bit 61) Must be set to “0” Reserved (Bit 60) Must be set to “0” Reserved (Bit 59) Must be set to “0” Reserved (Bit 58) Must be set to “0” Reserved (Bit 57) Must be set to “0” Reserved (Bit 56) Must be set to “0” Byte 6 Reserved (Bit 55) Must be set to “0” Reserved (Bit 54) Must be set to “0” SHUT2 (Bit 53) 0 = Normal 1 = Powered down Reserved (Bit 52) Must be set to “0” Reserved (Bit 51) Must be set to “0” Reserved (Bit 50) Must be set to “0” Byte 5 Reserved (Bit 47) Must be set to “0” LC (Bit 46) Loop filter cap select LR[1] (Bit 45) LR[0] (Bit 44) Reserved (Bit 43) Must be set to “0” Reserved (Bit 42) Must be set to “0” CMOS (Bit 39) 0 = PECL 1 = CMOS FBKDSRC (Bit 38) 0 = VCO output 1 = Post divider output FBKDIV[13] (Bit 37) 8192 FBKDIV[11] (Bit 35) 2048 FBKDIV[10] (Bit 34) 1024 FBKDIV[6] (Bit 30) 64 FBKDIV[5] (Bit 29) 32 Byte 4 Byte 3 FBKDIV[7] (Bit 31) 128 Loop filter resistor select FBKDIV[12] (Bit 36) 4096 SYNCPOL SYNCEN (Bit 49) (Bit 48) “0” = negative “0” = negative “1” = positive “1” = positive CP[1] (Bit 41) CP[0] (Bit 40) Charge pump current select FBKDIV[9] (Bit 33) 512 FBKDIV[8] (Bit 32) 256 See the Feedback Divider section for disallowed FBKDIV values FBKDIV[4] (Bit 28) 16 FBKDIV[3] (Bit 27) 8 FBKDIV[2] (Bit 26) 4 FBKDIV[1] (Bit 25) 2 FBKDIV[0] (Bit 24) 1 POST1[1] (Bit 17) POST1[0] (Bit 16) See the Feedback Divider section for disallowed FBKDIV values Byte 2 POST2[3] (Bit 23) POST2[2] (Bit 22) POST2[0] (Bit 20) POST1[3] (Bit 19) SHUT1 (Bit 13) 0 = Normal 1 = Powered down REFDSRC (Bit 12) 0 = Crystal oscillator 1 = REF pin REFDIV[11] (Bit 11) 2048 REFDIV[10] (Bit 10) 1024 REFDIV[9] (Bit 9) 512 REFDIV[8] (Bit 8) 256 REFDIV[5] (Bit 5) 32 REFDIV[4] (Bit 4) 16 REFDIV[3] (Bit 3) 8 REFDIV[2] (Bit 2) 4 REFDIV[1] (Bit 1) 2 REFDIV[0] (Bit 0) 1 POST2[1] (Bit 21) Modulus = N + 1 (N = 0 to 11); See Table 12 Byte 1 POST3[1] (Bit 15) POST3[0] (Bit 14) Modulus = 1, 2, 4 or 8; See Table 12 Byte 0 REFDIV[7] (Bit 7) 128 REFDIV[6] (Bit 6) 64 POST1[2] (Bit 18) Modulus = N + 1 (N = 0 to 11); See Table 12 http://onsemi.com 12 FS7140, FS7145 Table 9. DEVICE CONFIGURATION BITS Name REFDSRC FBKDSRC SHUT1 SHUT2 CMOS Table 13. POST DIVIDER CONTROL BITS Description Name POST1[3:0] Reference divider source [0000] 1 Feedback divider source [0001] 2 [0] = VCO output / [1] = post divider output [0010] 3 Shutdown1 [0011] 4 [0] = normal / [1] = powered down [0100] 5 Shutdown2 [0101] 6 [0] = normal / [1] = powered down [0110] 7 CLKP/CLKN output mode [0111] 8 [0] = PECL output / [1] CMOS output [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] Do not use Name LR[1:0] LC Description Charge pump current [00] 2.0 mA [1101] [01] 4.5 mA [1110] [10] 11.0 mA [11] 22.5 mA [1111] POST2[3:0] Loop filter resistor select [0000] 1 400 KW [0001] 2 [01] 133 KW [0010] 3 [10] 30 KW [0011] 4 [11] 12 KW [0100] 5 Loop filter capacitor select [0101] 6 [0] 185 pF [0110] 7 [1] 500 pF [0111] 8 [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] Do not use Name Description REFDIV[11:0] Reference divider (NR) FBKDIV[13:0] Feedback divider (NR) [1101] Table 12. SYNC CONTROL BITS (FS7145 only) Name [1110] Description [1111] Sync enable POST3[1:0] [0] = disabled / [1] = enabled SYNCPOL Post divider #2 (NP2) modulus [00] Table 11. PLL DIVIDER CONTROL BITS SYNCEN Post divider #1 (NP1) modulus [0] = crystal oscillator / [1] = REF pin Table 10. MAIN LOOP TUNING BITS CP[1:0] Description Post divider #3 (NP3) modulus Sync polarity [00] 1 [0] = negative edge / [1] = positive edge [01] 2 [10] 4 [11] 8 http://onsemi.com 13 FS7140, FS7145 Figure 7. Bus Timing Data Figure 8. Data Transfer Sequence http://onsemi.com 14 FS7140, FS7145 PACKAGE DIMENSIONS SSOP 16 CASE 565AE−01 ISSUE O http://onsemi.com 15 FS7140, FS7145 PACKAGE DIMENSIONS SOIC 16 CASE 751BA−01 ISSUE O http://onsemi.com 16 FS7140, FS7145 Table 14. ORDERING INFORMATION Part Number Package Shipping Configuration Temperature Range FS7145−01−XTD 16−pin (0.150″) SOIC Tube/Tray 0°C to 70°C (commercial) FS7145−01−XTP 16−pin (0.150″) SOIC Tape & Reel 0°C to 70°C (commercial) FS7140−02G−XTD 16−pin (5.3 mm) SSOP ‘Green’ or lead−free packaging Tube/Tray 0°C to 70°C (commercial) FS7140−02G−XTP 16−pin (5.3 mm) SSOP ‘Green’ or lead−free packaging Tape & Reel 0°C to 70°C (commercial) FS7140−01G−XTD 16−pin (0.150″) SOIC ‘Green’ or lead−free packaging Tube/Tray 0°C to 70°C (commercial) FS7140−01G−XTP 16−pin (0.150″) SOIC ‘Green’ or lead−free packaging Tape & Reel 0°C to 70°C (commercial) FS7145−02G−XTD 16−pin (5.3 mm) SSOP ‘Green’ or lead−free packaging Tube/Tray 0°C to 70°C (commercial) FS7145−02G−XTP 16−pin (5.3 mm) SSOP ‘Green’ or lead−free packaging Tape & Reel 0°C to 70°C (commercial) ON Semiconductor is licensed by Philips Corporation to carry the I2C protocol. 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