FSA8008A
Audio Jack Detection and
Configuration Switch
The FSA8008A is an audio jack detector and switch for 3− or 4−pole
accessories. In addition to detection, the FSA8008A features an
integrated MIC switch that allows the processor to configure the audio
jack. The architecture is designed to allow common third−party
headphones to be used for listening to music from mobile handsets,
personal media players, and portable peripheral devices.
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Features
• Determines 3− or 4−Pole Audio Jacks
• Removes Audio Jack Pop−n−Click Caused by MIC Bias
• Detects Audio Jack Accessories:
1
UQFN10
CASE 523BC
♦
Standard Headphones
♦ Headsets with MIC
♦ Send / End Button Presses
Integrates a MIC Switch for 4−Pole Configuration
Detection
Accessory Plug−In 3− or
4−Pole Audio Jack Send/End
Key Pressed
Functionality
Decreased Timing for Sensitive
Send/End Keys
• 3.5 mm and 2.5 mm Audio Jacks
• Cellular Phones, Smartphones
• MP3 and PMP
Switch Type
MIC
VDD
2.5 to 4.4 V
VIO
1.6 to VDD
THD (MIC)
0.01% Typical
Related Resources
ESD (Air Gap)
15 kV
Operating
Temperature
−40°C to 85°C
Package
10−Lead UMLP
1.4 x 1.8 x 0.5 mm,
0.4 mm Pitch
Top Mark
KD
Ordering
Information
FSA8008AUMX
•
Applications
• FSA8008A Demonstration Board
2.5 to 4.4V
Baseband
Processor
1.6 to VDD
VDD
VIO
VDD
DET
EN
J POLE
S/E
GPIO 1
GPIO 2
GPIO 3
GPIO 4
LOW = plugged
HIGH = unplugged
Normally Open
(NO ) Switch
0.5mA
J _DET
L R GND MIC
Oscillator
and Logic
1
2 3 4
Audio
R MIC
MIC
MIC Bias
16−32W
COMP
CMIC
HIGH =>J_MIC=0V
LOW =>J_MIC>0.2V
R SPKR
GND
16−32W
MIC
L SPKR
J_MIC
S
−
Figure 1. Mobile Phone Example
© Semiconductor Components Industries, LLC, 2011
December, 2017 − Rev. 2
1
Publication Order Number:
FSA8008A/D
FSA8008A
Pin Configuration
EN
3
JPOLE
4
VDD
5
DET
VIO
2
1
6
7
S/E
MIC
10
J_DET
9
GND
8
J_MIC
Figure 2. 10−Lead UMLP Pin Assignment (Through View)
Table 1. PIN DESCRIPTIONS
Name
Pin #
Type
Description
DET
2
Output
Indicates if an accessory is plugged into the audio jack, as detected
on the J_DET pin
0
Plugged
1
Unplugged
JPOLE
4
Output
Indicates if an accessory plugged into the audio jack is 3 pole or 4
pole
0
4−pole jack
1
3−pole jack
Indicates state of SEND/END for a 4−pole accessory when a key
has been pressed
0
No key press
1
Key press
S/E
6
Output
Function
EN
3
Input
Controls internal microphone switch between the J_MIC and MIC
pins
0
MIC / J_MIC switch open
1
MIC / J_MIC switch closed
J_DET
10
Input
Input from a pin of the audio jack socket tied to a mechanical switch
that typically closes whenever an audio jack is inserted into that
socket
0
Plugged
1
Unplugged
MIC
7
Switch
Microphone switch path that goes to the microphone preamplifier
J_MIC
8
Switch
Microphone switch path that connects to the microphone and SEND/
END key audio jack pole
VDD
5
Power
VIO
1
Power
Baseband I/O supply voltage
GND
9
Ground
Ground for both the audio jack and the PCB
Core supply voltage
1. 0 = VOL or VIL; 1 = VOH or VIH
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2
See EN pin
FSA8008A
Power Up
(POR GOOD)
Is there an
accessory
plugged into
the audio
jack?
NO
YES
3-Pole Configuration
3-Pole
• DET = 0
• JPOLE = 1
• S/E = 0
Is the
accessory 3
or 4 pole?
YES
4- Pole Configuration
4-Pole
Is the
accessory a
3 or 4 pole?
• DET = 0
• JPOLE = 0
• S/E = 0
Configure MIC Switch
• EN = Set by processor
NO
Stuck
Send/End
Key Check (Note 2)
Is there an
accessory
plugged into
the audio
jack?
NO
Is Send/END
key pressed?
YES
NO
Key Press
• S/E = 1
YES
Detached Accessory
No Key Press
• S/E = 0
Is there an
accessory
plugged into
the audio
jack?
NO
Set to Default States
• DET = 1
• JPOLE = 1
• S/E =0
YES
Figure 3. Functional Flow Diagram
2. Stuck Send/End key function is only available if EN=H.
Table 2. STUCK SEND/END KEY
EN
FSA8008A
H
Stuck Send / End Key Active
L
Stuck Send / End Key Disabled
Table 3. STATES DURING POWER GOOD AND OFF
State Description
VDD
VIO
Active
1
1
OFF
0
0
1
0
0
1
DET
EN
JPOLE
S/E
J−DET
MIC Switch
H
(unplugged)
Open
Active
1
(unplugged)
3−State
1
(3 Pole)
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3
0
(No Press)
FSA8008A
Table 4. I/O STATES DURING DETECTION (Note 3)
S/E
JPOLE
J_DET
J_MIC
EN
3 Pole
4 Pole
3 Pole
4 Pole
DET
0
1
1
0 (no press)
0 (no press)
0 (4 Pole)
0 (4 Pole)
0
0
0
0
0 (no press)
1 (press)
1 (3 Pole)
0 (4 Pole)
0
0
1
0
0 (no press)
0 (no press)
1 (3 Pole)
0 (4 Pole)
0
0
0
1
0 (no press)
1 (press)
1 (3 Pole)
0 (4 Pole)
0
1
X
X
0 (no press)
0 (no press)
1 (3 Pole)
1 (3 Pole)
1
3. State detected after initial plug−in.
Table 5. ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Units
Supply Voltage from Battery
−0.5
6.0
V
VSW
Switch I/O Voltage for “S” Switch and All Input Voltages Except J_DET
−0.5
VDD+0.5
V
VJD
Input Voltage for J_DET Input
−1.5
VDD+0.5
V
IIK
Input Clamp Diode Current
−50
ISW
Switch I/O Current (Continuous)
VDD & VIO
TSTG
Parameter
Storage Temperature Range
−65
mA
50
mA
+150
_C
TJ
Maximum Junction Temperature
+150
_C
TL
Lead Temperature (Soldering, 10 Seconds)
+260
_C
ESD
IEC 61000−4−2 System ESD
JEDEC JESD22−A114, Human Body Model
JEDEC JESD22−C101, Charged Device Model
Air Gap
15.0
Contact
8.0
All Pins
7.5
J_DET, J_MIC, VDD, VIO
12.0
All Pins
2.0
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed.
Table 6. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Units
VDD
Battery Supply Voltage
2.5
4.4
V
VIO
Parallel I/O Supply Voltage
1.6
VDD
V
TA
Operating Temperature
−40
+85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
FSA8008A
Table 7. DC ELECTRICAL CHARACTERISTICS All typical values are at TA = 25°C unless otherwise specified.
TA = −40 to +855C
Symbol
Parameter
VDD (V)
Conditions
Min
Typ
Max
Units
0.9
2.9
W
0.8
2.5
0.6
2.0
MIC SWITCH
RON
Mic Switch On Resistance
IOUT = 30 mA,
VIN = 2.0 V
2.5
2.8
3.8
RFLAT(ON)
On Resistance Flatness
2.5
IOUT = 30 mA,
VIN = 1.6, 2.0, 2.5
1.50
2.8
IOUT = 30 mA,
VIN = 1.6, 2.0, 2.8
0.70
3.8
2.5 to 4.4
0.25
VIN
Switch Input Voltage Range
0
VDD
V
CON
MIC and J_MIC Switch ON Capacitance
3.8
f = 1 MHz
76
pF
COFF
MIC and J_MIC Switch OFF Capacitance
3.8
f = 1 MHz
24
pF
J_DETAudioV
Audio Voltage Range on J_DET Pin
2.5 to 4.4
DET = L
−1
1
V
J_DETAudiof
Audio Frequency on J_DET Pin
2.5 to 4.4
DET = L
20
20000
Hz
J_DETRGND
Detection Resistance to Ground
2.5 to 4.4
Audio Jack Inserted
0
500
KW
J_DET
J_DETHYS
Hysteresis of J_DET
100
mV
PARALLEL I/O
VIH
Input High Voltage
0.7 x VIO
VIL
Input Low Voltage
VOH
Output High Voltage
IOH = −100 mA
VOL
Output Low Voltage
IOL = +100 mA
VIO
V
0.3 x VIO
V
0.8 x VIO
V
0.2 x VIO
V
COMPARATOR
VCOMP
Comparator Threshold for SEND/
END Sensing
2.5−3.8
J_DET, EN = L
200
mV
CURRENT
IOFF
IIN
Power Off Leakage Current Through
Switch
Input Leakage Current
0
MIC and J_MIC
Ports VIN = 4.4 V
1.5
mA
0 to 4.4
Inputs 0 = 4.4 V
1
mA
ICC−SLNA
Battery Supply Sleep Mode Current
No Accessory Attached
2.5 to 4.4
Static Current During
Sleep Mode (EN = L)
1
3
mA
ICC−SLWA
Battery Supply Sleep Mode Current
with Accessory Attached
2.5 to 4.4
Active Current (EN =
L and/or DET = H)
15
25
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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5
FSA8008A
Table 8. AC ELECTRICAL CHARACTERISTICS All typical values are for VCC = 3.3 V at TA = 25°C unless otherwise specified.
TA = −40 to +855C
Symbol
Parameter
VDD (V)
Conditions
Min
Typ
Max
Unit
MIC SWITCH
THD
Total Harmonic Distortion
3.8
RT = 600 W, VSW = 0.5 VPP,
f = 20 Hz to 20 kHz, VIN = 2.0 V
0.01
%
OIRR
Off Isolation
3.8
f = 20 kHz, RS = 32 W,
CL = 0 pF, RT = 32 W
−90
dB
Output Edge Rates
(DET, S/E, JPOLE)
2.5
CL = 5 pF, 20% to 80%
19
ns
PARALLEL I/O
tR, tF
3.8
15
ms
tPOLL
On Time of MIC Switch for
Sensing SEND/END Button Press
Oscillator Stable Time
2.5 to 4.4
1
tPER
Period of MIC Switching Time for
Sensing SEND/END Button Press
2.5 to 4.4
10
tDET−IN
Debounce Time after J−DET
Changes State from High to Low
2.5 to 4.4
422
ms
tDET_REM
Debounce Time after J_DET
Changes State from Low to High
2.5 to 4.4
30
ms
tDET
Detection Timeout for Sensing
3−Pole or 4−Pole Audio Jack
Plugged In
2.5 to 4.4
4.5
ms
tKBK
Debounce Time for Sensing
SEND/END Key Press / Release
2.5 to 4.4
27
ms
−90
dB
POWER
PSRR
Power Supply Rejection Ratio
3.8
Power Supply Noise 300 mVPP,
Measured 10/90%, f = 217 Hz
ORDERING INFORMATION
Part Number
Operating Temperature Range
Top Mark
Package
FSA8008AUMX
−40 to +85°C
KD
10−Lead, 1.4 x 1.8 x 0.55 mm, 0.4 mm Pitch,
Ultrathin Molded Leadless Package (UMLP)
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN10 1.4x1.8, 0.4P
CASE 523BC
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13705G
UQFN10 1.4x1.8, 0.4P
DATE 31 OCT 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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FSA8008AUMX