FSL116HR

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. FSL116HR Green-Mode Power Switch Description The FSL116HR integrated Pulse Width Modulator (PWM) and SENSEFET® is specifically designed for high− performance offline Switched−Mode Power Supplies (SMPS) with minimal external components. FSL116HR includes integrated high−voltage power switching regulators that combine an avalanche−rugged SENSEFET with a Current−Mode PWM control block. The integrated PWM controller includes: Under−Voltage Lockout (UVLO) protection, Leading−Edge Blanking (LEB), a frequency generator for EMI attenuation, an optimized gate turn−on / turn−off driver, Thermal Shutdown (TSD) protection, and temperature− compensated precision current sources for loop compensation and fault−protection circuitry. The FSL116HR offers good soft−start performance. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSL116HR reduces total component count, design size, and weight; while increasing efficiency, productivity, and system reliability. This device provides a basic platform that is well suited for the design of cost−effective flyback converters. Features • Internal Avalanche−Rugged SENSEFET (650 V) • Under 50 mW Standby Power Consumption at 265 VAC, No−load Condition with Burst Mode • Precision Fixed Operating Frequency with Frequency Modulation for • • • • • • • • • Attenuating EMI Internal Startup Circuit Built−in Soft−Start: 20 ms Pulse−by−Pulse Current Limiting Various Protections: Over−Voltage Protection (OVP), Overload Protection (OLP), Output−Short Protection (OSP), Abnormal Over−Current Protection (AOCP), Internal Thermal Shutdown Function with Hysteresis (TSD) Auto−Restart Mode Under−Voltage Lockout (UVLO) Low Operating Current: 1.8 mA Adjustable Peak Current Limit This is a Pb−Free Device www.onsemi.com PDIP8 9.42x6.38, 2.54P CASE 646CM MARKING DIAGRAM $Y&E&Z&2&K FSL116HR $Y &E &Z &2 &K FSL116HR = ON Semiconductor Logo = Designates Space = Assembly Plant Code = 2−Digit Date Code Format = 2−Digit Lot Run Tracebility Code = Specific Device Code Data ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Applications • SMPS for VCR, STB, DVD, & DVCD Players • SMPS for Home Appliance • Adapter © Semiconductor Components Industries, LLC, 2019 July, 2019 − Rev. 2 1 Publication Order Number: FSL116HR/D FSL116HR Related Resources Table 1. MAXIMUM OUTPUT POWER • AN−4137 − Design Guidelines for Offline Flyback • • • Maximum Output Power (Note 1) Converters Using Power Switch AN−4141 − Troubleshooting and Design Tips for Power Switch Flyback Applications AN−4147 − Design Guidelines for RCD Snubber of Flyback Power Supply WebDesigner − Flyback Design & Simulation − In Minutes at No Expense 230VAC +15% (Note 2) 85 − 265 VAC Adapter (Note 3) Open Frame Adapter (Note 3) Open Frame 11 W 16 W 10 W 14 W 1. The junction temperature can limit the maximum output power. 2. 230 VAC or 100 / 115 VAC with doubler. 3. Typical continuous power in a non−ventilated enclosed adapter measured at 50°C ambient. ORDERING INFORMATION Part Number Operating Temperature Range Top Mark Package Shipping FSL116HR −40 to 105°C FSL116HR 8−Lead, Dual Inline Package (DIP) (Pb−Free) 3000 Units / Tube Application Diagram AC IN DC OUT VSTR I PK Drain PWM VFB VCC Source Figure 1. Typical Application www.onsemi.com 2 FSL116HR Internal Block Diagram VSTR 5 VCC 2 D rai n 6,7,8 ICH VBURL / VBURH 8 V / 12 V VCC Good Internal Bias VREF VCC V CC I DELAY Random Frequency Generator IFB OSC S Q PWM VFB 3 2.5R Gate Driver R Q R IPK 4 On−Time Detector LEB Soft Start OSP VSD VCC Good VCC VOVP S Q R Q 1 GND AOCP VAOCP TSD Figure 2. Internal Block Diagram Pin Configuration GND VCC Drain 8−DIP Drain VFB Drain IPK VSTR Figure 3. Pin Configuration www.onsemi.com 3 FSL116HR PIN DEFINITIONS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin No. Name Description 1 GND Ground. SENSEFET source terminal on the primary side and internal control ground. 2 VCC Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin 5 (VSTR) via an internal switch during startup (see Figure 2). Once VCC reaches the UVLO upper threshold (12 V), the internal startup switch opens and device power is supplied via the auxiliary transformer winding. 3 VFB Feedback Voltage. The non−inverting input to the PWM comparator, it has a 0.4 mA current source connected internally, while a capacitor and opto−coupler are typically connected externally. There is a delay while charging external capacitor CFB from 2.4 V to 6 V using an internal 5 mA current source. This delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. 4 IPK Peak Current Limit. Adjusts the peak current limit of the SENSEFET. The feedback 0.4 mA current source is diverted to the parallel combination of an internal 6 kW resistor and any external resistor to GND on this pin to determine the peak current limit. 5 VSTR Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and charges an external storage capacitor placed between the VCC pin and ground. Once VCC reaches 12 V, the internal switch is opened. 6, 7, 8 Drain Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of 650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit VSTR VSTR Pin Voltage −0.3 650.0 V VDS Drain Pin Voltage −0.3 650.0 V VCC Supply Voltage − 26 V VFB Feedback Voltage Range −0.3 12 V ID Continuous Drain Current − 1 A IDM Drain Current Pulsed (Note 4) − 4 A EAS Single Pulsed Avalanche Energy (Note 5) − 38 mJ PD Total Power Dissipation − 1.5 W TJ Operating Junction Temperature TA Operating Ambient Temperature −40 +105 °C TSTG Storage Temperature −55 +150 °C ESD Human Body Model, JESD22−A114 (Note 6) 5 − KV Charged Device Model, JESD22−C101 (Note 6) 2 − QJA Junction−to−Ambient Thermal Resistance (Note 7, 8) − 80 °C/W QJC Junction−to−Case Thermal Resistance (Note 7, 9) − 19 °C/W QJT Junction−to−Top Thermal Resistance (Note 7, 10) − 33.7 °C/W Internally Limited °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. Repetitive rating: pulse width limited by maximum junction temperature. 5. L = 30 mH, starting TJ = 25°C. 6. Meets JEDEC standards JESD 22−A114 and JESD 22−C101. 7. All items are tested with the standards JESD 51−2 and JESD 51−10. 8. QJA free−standing, with no heat−sink, under natural convection. 9. QJC junction−to−lead thermal characteristics under QJA test condition. TC is measured on the source #7 pin closed to plastic interface for QJA thermo−couple mounted on soldering. 10. QJT junction−to−top of thermal characteristic under QJA test condition. Tt is measured on top of package. Thermo−couple is mounted in epoxy glue. www.onsemi.com 4 FSL116HR ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Test Condition Min Typ Max Unit SENSEFET SECTION BVDSS IDSS RDS(ON) CISS Drain−Source Breakdown Voltage VCC = 0 V, ID = 250 mA 650 − − V Zero Gate Voltage Drain Current VDS = 650 V, VGS = 0 V − − 250 mA Drain−Source On−State Resistance VGS = 10 V, VGS = 0 V, TC = 25°C − 7.3 10.0 W Input Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz − 135 − pF 21 − pF COSS Output Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz − CRSS Reverse Transfer Capacitance VGS = 0 V, VDS = 25 V, f = 1 MHz − 3.2 − pF td(ON) Turn−On Delay VDS = 350 V, IDS = 1 A − 10 − ns Rise Time VDS = 350 V, IDS = 1 A − 13.4 − ns Turn−Off Delay VDS = 350 V, IDS = 1 A − 14.9 − ns Fall Time VDS = 350 V, IDS = 1 A − 36.8 − ns Switching Frequency VDS = 650 V, VGS = 0 V 90 100 110 KHz Switching Frequency Variation VGS = 10 V, VGS = 0 V, TC = 125°C − tr td(OFF) tf CONTROL SECTION fOSC DfOSC fFM Frequency Modulation ±5 ±10 % − ±3 − KHz DMAX Maximum Duty Cycle VFB = 4 V 71 77 83 % DMIN Minimum Duty Cycle VFB = 0 V 0 0 0 % 11 12 13 V 7 8 9 V VSTART UVLO Threshold Voltage VSTOP After Turn−On IFB Feedback Source Current VFB = 0 V 320 400 480 mA tS/S Internal Soft−Start Time VFB = 4 V 15 20 25 ms 0.56 0.70 0.84 V VBURL 0.37 0.50 0.63 V VBUR(HYS) − 200 − mV 0.96 1.10 1.24 A 200 − − ns BURST−MODE SECTION VBURH Burst−Mode Voltage VCC = 14 V, VFB Sweep PROTECTION SECTION ILIM Peak Current Limit tCLD Current Limit Delay Time (Note 11) VSD Shutdown Feedback Voltage VCC = 15 V 5.5 6.0 6.5 V IDELAY Shutdown Delay Current VFB = 5 V 3.5 5.0 6.5 mA VOVP Over−Voltage Protection Threshold VFB = 2 V 22.5 24.0 25.5 V tOSP Output Short Protection (Note 11) TJ = 25°C OSP Triggered when ton < tOSP, VFB > VOSP and Lasts Longer than tOSP_FB − 1.00 1.35 ms 1.44 1.60 − V 2.0 2.5 − ms 0.85 1.00 1.15 V 125 137 150 °C − 60 − °C VOSP tOSP_FB VAOCP TSD HYSTSD TJ = 25°C, di/dt = 300 mA/ms Threshold Time Threshold Feedback Voltage Feedback Blanking Time AOCP Voltage (Note 11) Thermal Shutdown (Note 11) TJ = 25°C Shutdown Temperature Hysteresis www.onsemi.com 5 FSL116HR ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (continued) Symbol Parameter Test Condition Min Typ Max Unit 300 − − ns PROTECTION SECTION tLEB Leading−Edge Blanking Time (Note 11) TOTAL DEVICE SECTION IOP1 Operating Supply Current (Note 11) (While Switching) VCC = 14 V, VFB > VBURH − 2.5 3.5 mA IOP2 Operating Supply Current, (Control Part Only) VCC = 14 V, VFB < VBURL − 1.8 2.5 mA ICH Startup Charging Current VCC = 0 V 0.9 1.1 1.5 mA Minimum VSTR Supply Voltage VCC = VFB = 0 V, VSTR Increase 35 − − V VSTR Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 11. Guaranteed by design, not 100% tested in production. TYPICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Operating Frequency (fOSC) Maximum Duty Cycle (DMAX) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 −40°C −25°C 0°C 25°C 50°C 75°C 100°C 120°C 140°C −40°C −25°C Figure 4. Operating Frequency vs. Temperature 0°C 25°C 50°C 75°C 100°C 120°C 140°C Figure 5. Maximum Duty Cycle vs. Temperature Start Threshold Voltage (VSTART) Operating Supply Current (Iop2) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 −40°C −25°C 0°C 25°C 50°C 75°C 100°C 120°C 140°C −40°C −25°C Figure 6. Operating Supply Current vs. Temperature 0°C 25°C 50°C 75°C 100°C 120°C 140°C Figure 7. Start Threshold Voltage vs. Temperature www.onsemi.com 6 FSL116HR TYPICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (continued) Stop Theshold Voltage (VSTOP) Feedback Source Current (IFB) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 −40°C −25°C 0°C 25°C 50°C 75°C 100°C 120°C 140°C −40°C −25°C Figure 8. Stop Threshold Voltage vs. Temperature 0°C 25°C 50°C 75°C 100°C 120°C 140°C Figure 9. Feedback Source Current vs. Temperature Peak Current Limit (ILIM) Startup Charging Current (ICH) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 −40°C −25°C 0°C 25°C 50°C 75°C 100°C 120°C 140°C −40°C −25°C Figure 10. Startup Charging Current vs. Temperature 0°C 25°C 50°C 75°C 100°C 120°C 140°C Figure 11. Peak Current Limit vs. Temperature Burst Operating Supply Current (Iop1) Over−Voltage Protection (VOVP) 1.4 1.4 1.3 1.3 1.2 1.2 1.1 1.1 1 1 0.9 0.9 0.8 0.8 0.7 0.7 0.6 0.6 −40°C −25°C 0°C 25°C 50°C 75°C 100°C 120°C 140°C −40°C −25°C Figure 12. Burst Operating Supply Current vs. Temperature 0°C 25°C 50°C 75°C 100°C 120°C 140°C Figure 13. Over−Voltage Protection vs. Temperature www.onsemi.com 7 FSL116HR FUNCTIONAL DESCRIPTION Feedback Control FSL116HR employs Current−Mode control, as shown in Figure 16. An opto−coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the RSENSE resistor makes it possible to control the switching duty cycle. When the shunt regulator reference pin voltage exceeds the internal reference voltage of 2.5 V, the opto−coupler LED current increases, the feedback voltage VFB is pulled down, and the duty cycle is reduced. This typically occurs when the input voltage is increased or the output load is decreased. Startup At startup, an internal high−voltage current source supplies the internal bias and charges the external capacitor (CA) connected with the VCC pin, as illustrated in Figure 14. When VCC reaches the start voltage of 12 V, the power switch begins switching and the internal high− voltage current source is disabled. The power switch continues normal switching operation and the power is provided from the auxiliary transformer winding unless VCC goes below the stop voltage of 8 V. VDC VCC Ca 2 VCC VSTR J−FET VCC good 0.4 mA OSC VFB VO 5 D1 D2 CFB I CH 8 V / 12 V VCC 5 mA I STR R 2.5 V VREF 2.5 R Gate Driver LEB Internal Bias VSD OLP RSENSE Figure 14. Startup Circuit Figure 16. Pulse−Width−Modulation Circuit Oscillator Block The oscillator frequency is set internally and the power switch has a random frequency fluctuation function. Fluctuation of the switching frequency of a switched power supply can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the range of the frequency variation. The range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of external feedback voltage and internal free−running oscillator. This randomly chosen switching frequency effectively spreads the EMI noise nearby switching frequency and allows the use of a cost− effective inductor instead of an AC input line filter to satisfy the world−wide EMI requirements. IDS Leading−Edge Blanking (LEB) At the instant the internal SENSEFET is turned on, the primary−side capacitance and secondary−side rectifier diode reverse recovery typically cause a high−current spike through the SENSEFET. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in the Current−Mode PWM control. To counter this effect, the power switch employs a leading−edge blanking (LEB) circuit (see the Figure 16). This circuit inhibits the PWM comparator for a short time (tLEB) after the SENSEFET is turned on. Protection Circuits The power switch has protective functions such as overload protection (OLP), over−voltage protection (OVP), output− short protection (OSP), under−voltage lockout (UVLO), abnormal over−current protection (AOCP), and thermal shutdown (TSD). Because these various protection circuits are fully integrated in the IC without external components, reliability is improved without increasing cost. If a fault condition occurs, switching is terminated and the SENSEFET remains off. This causes VCC to fall. When VCC reaches the UVLO stop voltage, VSTOP (8 V), the protection is reset and the internal high−voltage current source charges the VCC capacitor via the VSTR pin. When VCC reaches the UVLO start voltage, VSTART (12 V), the power switch resumes normal operation. In this manner, the auto−restart can alternately enable and disable the switching of the power SENSEFET until the fault condition is eliminated. several mseconds tSW = 1 / fSW tSW Dt fSW t fSW + 1/2 DfSWMAX several miliseconds no repetition fSW − 1/2 DfSWMAX t Figure 15. Frequency Fluctuation Waveform www.onsemi.com 8 FSL116HR Fault occurs Power on VDS Abnormal Over−Current Protection (AOCP) When the secondary rectifier diodes or the transformer pin are shorted, a steep current with extremely high di/dt can flow through the SENSEFET during the LEB time. Even though the power switch has overload protection, it is not enough to protect the power switch in that abnormal case, since severe current stress is imposed on the SENSEFET until OLP triggers. The power switch includes the internal Abnormal Over−Current Protection (AOCP) circuit shown in Figure . When the gate turn−on signal is applied to the power SENSEFET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the latch, resulting in the shutdown of the SMPS. Fault removed VCC 12 V 8V t Normal operation Fault Normal operation Figure 17. Auto−Restart Protection Waveforms 2.5 R Overload Protection (OLP) Overload is defined as the load current exceeding a pre−set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS is operating normally, the overload protection (OLP) circuit can be activated during the load transition or startup. To avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or a true overload situation. In conjunction with the IPK current limit pin (if used), the current−mode feedback path limits the current in the SENSEFET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (VO) decreases below its rating voltage. This reduces the current through the opto−coupler LED, which also reduces the opto−coupler transistor current, increasing the feedback voltage (VFB). If VFB exceeds 2.4 V, the feedback input diode is blocked and the 5 mA current source (IDELAY) starts to charge CFB slowly up to VCC. In this condition, VFB increases until it reaches 6 V, when the switching operation is terminated, as shown in Figure 18. The shutdown delay is the time required to charge CFB from 2.4 V to 6 V with 5 mA current source. R Gate Driver LEB RSENSE AOCP VAOCP 2 GND Figure 19. Abnormal Over−Current Protection Thermal Shutdown (TSD) The SENSEFET and the control IC are integrated, making it easier to detect the temperature of the SENSEFET. When the temperature exceeds approximately 137°C, thermal shutdown is activated. Over−Voltage Protection (OVP) In the event of a malfunction in the secondary−side feedback circuit or an open feedback loop caused by a soldering defect, the current through the opto−coupler transistor becomes almost zero. Then, VFB climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until the overload protection is activated. Because excess energy is provided to the output, the output voltage may exceed the rated voltage before the overload protection is activated, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an Over−Voltage Protection (OVP) circuit is employed. In general, VCC is proportional to the output voltage and the power switch uses VCC instead of directly monitoring the output voltage. If VCC exceeds 24 V, OVP circuit is activated, resulting in termination of the switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed to be below 24 V. Overload Protection 6V 2.4 V t12 = CFB x (V (t2) − V (t1)) / IDELAY t2 S Q R Q VFB t1 OSC PWM t Figure 18. Overload Protection (OLP) www.onsemi.com 9 FSL116HR Burst Mode Operation Output−Short Protection (OSP) If the output is shorted, steep current with extremely high di/dt can flow through the SENSEFET during the LEB time. Such a steep current brings high−voltage stress on the drain of SENSEFET when turned off. To protect the device from such an abnormal condition, OSP detects VFB and SENSEFET turn−on time. When the VFB is higher than 1.6 V and the SENSEFET turn−on time is lower than 1.0 ms, the FPS recognizes this condition as an abnormal error and shuts down PWM switching until VCC reaches VSTART again. An abnormal condition output is shown in Figure 20. MOSFET Drain Current Rectifier Diode Current To minimize power dissipation in Standby Mode, the FPS enters Burst Mode. As the load decreases, the feedback voltage decreases. As shown in Figure 22, the device automatically enters Burst Mode when the feedback voltage drops below VBURH. Switching continues, but the current limit is fixed internally to minimize flux density in the transformer. The fixed current limit is larger than that defined by VFB = VBURH and, therefore, VFB is driven down further. Switching continues until the feedback voltage drops below VBURL. At this point, switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback voltage to rise. Once it passes VBURH, switching resumes. The feedback voltage then falls and the process repeats. Burst Mode alternately enables and disables switching of the SENSEFET and reduces switching loss in Standby Mode. Turn−off Delay ILIM VFB VOUT Minimum Turn−on Time 1.6 ms D VO VOset Output Short Occurs IOUT VFB 0.7 V 0.5 V Figure 20. Output Short Waveforms (OSP) IDS SOFT−START The FPS has an internal soft−start circuit that slowly increases the feedback voltage, together with the SENSEFET current, after it starts. The typical soft−start time is 20 ms, as shown in Figure 21, where progressive increments of the SENSEFET current are allowed during the startup phase. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. Soft−start helps to prevent transformer saturation and reduces the stress on the secondary diode. VDS time Switching t1 disabled t4 Figure 22. Burst−Mode Operation Adjusting Peak Current Limit As shown in Figure 23, a combined 6 kW internal resistance is connected to the non−inverting lead on the PWM comparator. An external resistance of Rx on the current limit pin forms a parallel resistance with the 6 kW when the internal diodes are biased by the main current source of 400 mA. For example, FSL116HR has a typical SENSEFET peak current limit (ILIM) of 1.1 A. ILIM can be adjusted to 0.8 A by inserting Rx between the IPK pin and the ground. The value of the Rx can be estimated by the following equations: 1.25 ms ILIM 16 Steps Current Limit 0.25 ILIM t2 Switching t3 disabled Drain Current 1.1 A : 0.8 A + 6 kW : X kW X + Rx ø 6 kW Figure 21. Internal Soft−Start where X is the resistance of the parallel network. www.onsemi.com 10 (eq. 1) (eq. 2) FSL116HR VCC VCC IDELAY IFB 400 mA VFB PWM 3 4.25 kW IPK Rx 1.7 kW 4 Current Sense Figure 23. Peak Current Limit Adjustment SENSEFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP8 9.42x6.38, 2.54P CASE 646CM ISSUE O DATE 31 JUL 2016 9.83 9.00 5 8 6.670 6.096 1 4 8.255 7.610 TOP VIEW 1.65 1.27 (0.56) 7.62 3.683 3.200 5.08 MAX 3.60 3.00 0.33 MIN 0.560 0.355 2.54 15° 0° 0.356 0.200 7.62 9.957 7.870 FRONT VIEW SIDE VIEW NOTES: A. CONFORMS TO JEDEC MS−001, VARIATION BA B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONS AND TOLERANCES PER ASME Y14.5M−2009 DOCUMENT NUMBER: DESCRIPTION: 98AON13468G PDIP8 9.42X6.38, 2.54P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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