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Green Mode Power Switch
FSL206MR
Description
The FSL206MR integrated Pulse−Width Modulator (PWM) and
SENSEFET® is specifically designed for high−performance offline
Switched−Mode Power Supplies (SMPS) while minimizing external
components. This device integrates high−voltage power regulators
that combine an avalanche−rugged SENSEFET with a Current−Mode
PWM control block.
The integrated PWM controller includes: a 7.8 V regulator,
eliminating the need for auxiliary bias winding; Under−Voltage
Lockout (UVLO) protection; Leading−Edge Blanking (LEB); an
optimized gate turn−on/turn−off driver; EMI attenuator; Thermal
Shutdown (TSD) protection; temperature−compensated precision
current sources for loop compensation; soft−start during startup; and
fault−protection circuitry such as Overload Protection (OLP),
Over−Voltage Protection (OVP), Abnormal Over−Current Protection
(AOCP), and Line Under−Voltage Protection (LUVP).
The internal high−voltage startup switch and the Burst−Mode
operation with very low operating current reduce the power loss in
Standby Mode. As a result, it is possible to reach a power loss of
150 mW with no bias winding and 25 mW (for FSL206MR) or
30 mW (for FSL206MRBN) with a bias winding under no−load
conditions when the input voltage is 265 Vac.
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PDIP8 9.42x6.38, 2.54P
CASE 646CM
PDIP8 9.59x6.6, 2.54P
CASE 646CN
PDIP8 GW
CASE 709AJ
MARKING DIAGRAM
Features
• Internal Avalanche−Rugged SENSEFET 650 V
• Precision Fixed Operating Frequency: 67 kHz
• No−Load < 150 mW at 265 Vac without Bias Winding; 2V
VCC
Q
Q
VCC Good
Figure 2. Internal Block Diagram
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2
FSL206MR
PIN CONFIGURATION
GND
VCC
VFB
Drain
8−DIP
8−LSOP
Drain
Drain
VSTR
LS
Figure 3. Pin Configuration
PIN DEFINITIONS
Pin No.
Name
Description
1
GND
Ground. SENSEFET source terminal on the primary side and internal control ground.
2
VCC
Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin
5 (VSTR) via an internal switch during startup (see Figure 2). Once VCC reaches the UVLO upper threshold (12 V),
the internal startup switch opens and device power is supplied via the auxiliary transformer winding.
3
VFB
Feedback Voltage. Non−inverting input to the PWM comparator, with a 0.11 mA current source connected internally
and a capacitor and opto−coupler typically connected externally. There is a delay while charging external capacitor
CFB from 2.4 V to 5 V using an internal 2.7 mA current source. This delay prevents false triggering under transient
conditions, but allows the protection mechanism to operate under true overload conditions.
4
LS
Line Sense Pin This pin is used to protect the device when the input voltage is lower than the rated input voltage
range. If this pin is not used, connect to ground.
5
VSTR
Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and
charges an external storage capacitor placed between the VCC pin and ground. Once VCC reaches 8 V, all internal
blocks are activated. After that, the internal high−voltage regulator (HV REG) turns on and off irregularly to maintain
VCC at 7.8 V.
6, 7, 8
Drain
Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of
650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
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3
FSL206MR
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Symbol
Min
Max
Unit
VSTR
VSTR Pin Voltage
Parameter
−0.3
650
V
VDS
Drain Pin Voltage
−0.3
650
V
VCC
Supply Voltage
−
26
V
VLS
LS Pin Voltage
−
Internally Clamped Voltage (Note 4)
V
VFB
Feedback Voltage Range
−0.3
Internally Clamped Voltage (Note 4)
V
IDM
Drain Current Pulsed (Note 5)
−
1.5
A
EAS
Single−Pulsed Avalanche Energy (Note 6)
−
11
mJ
PD
Total Power Dissipation
−
1.3
W
TJ
Operating Junction Temperature
−40
+150
°C
TA
Operating Ambient Temperature
−40
+125
°C
TSTG
Storage Temperature
−55
+150
°C
ESD
Human Body Model, JESD22−A114
−
4
kV
Charged Device Model, JESD22−C101
−
2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. VFB is clamped by internal clamping diode (13 V ICLAMP_MAX < 100 mA). After Shutdown, before VCC reaching VSTOP, VSD < VFB < VCC.
5. Repetitive rating: pulse−width limited by maximum junction temperature.
6. L = 21 mH, starting TJ = 25°C
THERMAL IMPEDANCE (TA = 25°C unless otherwise specified)
Symbol
qJA
Parameter
Value
Unit
93
°C/W
Junction−to−Ambient Thermal Impedance (Note 7)
7. JEDEC recommended environment, JESD51−2 and test board, JESD51−10 with minimum land pattern for 8DIP and JESD51−3 with
minimum land pattern for 8LSOP.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SENSEFET SECTION
Drain−Source Breakdown
Voltage
VCC = 0 V, ID = 250 mA
650
−
−
V
Zero Gate Voltage Drain Current
VDS = 650 V, VGS = 0 V
−
−
50
mA
VDS = 520 V, VGS = 0 V, TA = 125°C (Note 8)
−
−
250
mA
Drain−Source On−State
Resistance (Note 9)
VGS = 10 V, ID = 0.3 A
−
14
19
W
CISS
Input Capacitance
VGS = 0 V, VDS = 25 V, f = 1 MHz
−
162
−
pF
COSS
Output Capacitance
VGS = 0 V, VDS = 25 V, f = 1 MHz
−
14.9
−
pF
CRSS
Reverse Transfer Capacitance
VGS = 0 V, VDS = 25 V, f = 1 MHz
−
2.7
−
pF
BVDSS
IDSS
RDS(ON)
tr
Rise Time
VDS = 325 V, ID = 0.5 A, RG = 25 W
−
6.1
−
ns
tf
Fall Time
VDS = 325 V, ID = 0.5 A, RG = 25 W
−
43.6
−
ns
Switching Frequency
VFB = 4 V, VCC = 10 V
61
67
73
KHz
DfOSC
Switching Frequency Variation
−25°C < TJ < 85°C
−
±5
±10
%
fM
Frequency Modulation (Note 8)
−
±3
−
kHz
CONTROL SECTION
fOSC
DMAX
Maximum Duty Cycle
VFB = 4 V, VCC = 10 V
66
72
78
%
DMIN
Minimum Duty Ratio
VFB = 0 V, VCC = 10 V
0
0
0
%
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4
FSL206MR
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) (continued)
Symbol
VSTART
Parameter
UVLO Threshold Voltage
VSTOP
Test Condition
Min
Typ
Max
Unit
VFB = 0 V, VCC Sweep
7
8
9
V
After Turn−on
6
7
8
V
IFB
Feedback Source Current
VFB = 0, VCC = 10 V
90
110
130
mA
tS/S
Internal Soft−Start Time
VFB = 4 V, VCC = 10 V
10
15
20
ms
BURST−MODE SECTION
VBURH
VBURL
HYSBUR
Burst−Mode HIGH
Threshold Voltage
VCC = 10 V
VFB Increase
Burst−Mode LOW
Threshold Voltage
VCC = 10 V
VFB Decrease
Burst−Mode Hysteresis
FSL206MR
0.66
0.83
1.00
V
FSL206MRB
0.40
0.50
0.60
V
FSL206MR
0.59
0.74
0.89
V
FSL206MRB
0.28
0.35
0.42
V
FSL206MR
−
90
−
mV
FSL206MRB
−
150
−
mV
0.54
0.60
0.66
A
−
100
−
ns
PROTECTION SECTION
ILIM
Peak Current Limit
tCLD
Current Limit Delay Time (Note 8)
VSD
Shutdown Feedback Voltage
VCC = 10 V
4.5
5.0
5.5
V
Shutdown Delay Current
VFB = 4 V
2.1
2.7
3.3
mA
250
−
−
ns
−
0.7
−
V
IDELAY
tLEB
VFB = 4 V, di/dt = 300 mA/ms, VCC = 10 V
Leading Edge Blanking Time
(Note 8)
VAOCP
Abnormal Over−Current
Protection (Note 8)
VOVP
Over−Voltage Protection
VFB = 4 V, VCC Increase
23.0
24.5
26.0
V
VLS_OFF
Line−Sense Protection On to Off
VFB = 3 V, VCC = 10 V, VLS Decrease
1.9
2.0
2.1
V
VLS_ON
Line−Sense Protection Off to On
VFB = 3 V, VCC = 10 V, VLS Increase
1.4
1.5
1.6
V
TSD
Thermal Shutdown Temperature
(Note 8)
125
135
150
°C
−
60
−
°C
−
7.8
−
V
HYSTSD
TSD Hysteresis Temperature
(Note 8)
HIGH VOLTAGE REGULATOR SECTION
HHVR
HV Regulator Voltage
VFB = 0 V, VSTR = 40 V
TOTAL DEVICE SECTION
IOP1
Operating Supply Current (Control VCC = 15 V, 0 V < VFB < VBURL
Part Only, without Switching)
−
0.3
0.5
mA
IOP2
Operating Supply Current (Control VCC = 8 V, 0 V < VFB < VBURL
Part Only, without Switching)
−
0.25
0.45
mA
IOP3
Operating Supply Current (Note 8) VCC = 15 V, VBURL < VFB < VSD
(While Switching)
−
−
1.3
mA
ICH
Startup Charging Current
VCC = 0 V, VSTR > 40 V
1.6
1.9
2.4
mA
ISTART
Startup Current
VCC = Before VSTART, VFB = 0 V
−
100
150
mA
VSTR
Minimum VSTR Supply Voltage
VCC = VFB = 0 V, VSTR Increase
−
26
−
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Though guaranteed by design, it is not 100% tested in production.
9. Pulse test: pulse width = 300 ms, duty cycle = 2%.
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5
FSL206MR
TYPICAL PERFORMANCE CHARACTERISTICS
HV Regulator Voltage (VHVR)
Operating Frequency (f OSC)
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
‐40℃ ‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
115℃
‐40℃
Figure 4. Operating Frequency vs. Temperature
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
Figure 5. HV Regulator Voltage vs. Temperature
Stop Theshold Voltage (VSTOP)
Start Theshold Voltage (VSTART)
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
‐40℃
‐25℃
0℃
25℃
50℃
75℃
90℃
‐40℃
110℃
Figure 6. Start Threshold Voltage vs. Temperature
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
Figure 7. Stop Threshold Voltage vs. Temperature
Feedback Source Current (IFB)
Peak Current Limit (ILIM)
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
‐40℃
‐25℃
0℃
25℃
50℃
75℃
90℃
‐40℃
110℃
Figure 8. Feedback Source Current vs. Temperature
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
Figure 9. Peak Current Limit vs. Temperature
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6
FSL206MR
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(These Characteristic graphs are normalized at TA = 25.)
Startup Charging Current (ICH)
Operating Supply Current (Iop1)
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
‐40℃
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
‐40℃
Figure 10. Startup Charging Current vs. Temperature
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
Figure 11. Operating Supply Current 1
vs. Temperature
Operating Supply Current (Iop2)
Over‐Voltage Protection (VOVP)
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.1
1
1
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.6
‐40℃
‐25℃
0℃
25℃
50℃
75℃
90℃
110℃
‐40℃
Figure 12. Operating Supply Current 2
vs. Temperature
Shutdown Delay Current (IDELAY)
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
‐25℃
0℃
25℃
50℃
75℃
90℃
0℃
25℃
50℃
75℃
90℃
110℃
Figure 13. Over−Voltage Protection Voltage
vs. Temperature
1.4
‐40℃
‐25℃
110℃
Figure 14. Shutdown Delay Current vs. Temperature
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7
FSL206MR
FUNCTIONAL DESCRIPTION
Feedback Control
FSL206MR employs current−mode control, as shown in
Figure 17. An opto−coupler (such as the FOD817A) and
shunt regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the feedback
voltage with the voltage across the RSENSE resistor makes it
possible to control the switching duty cycle. When the shunt
regulator reference pin voltage exceeds the internal
reference voltage of 2.5 V, the optocoupler LED current
increases, the feedback voltage VFB is pulled down, and the
duty cycle is reduced. This typically occurs when the input
voltage is increased or the output load is decreased.
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(CA) connected with the VCC pin, as illustrated in Figure 15.
An internal high−voltage regulator (HV REG) located
between the VSTR and VCC pins regulates the VCC to 7.8 V
and supplies operating current. Therefore, FSL206MR
needs no auxiliary bias winding.
VDC,link
VSTR
VCC
3
7.8V
ICH
2
HV/REG
ISTART
CA
VREF
UVLO
Figure 15. Startup Block
Oscillator Block
Figure 17. Pulse−Width−Modulation (PWM) Circuit
The oscillator frequency is set internally and the power
switch has a random frequency fluctuation function.
Fluctuation of the switching frequency of a switched power
supply can reduce EMI by spreading the energy over a wider
frequency range than the bandwidth measured by the EMI
test equipment. The amount of EMI reduction is directly
related to the range of the frequency variation. The range of
frequency variation is fixed internally; however, its
selection is randomly chosen by the combination of external
feedback voltage and internal free−running oscillator. This
randomly chosen switching frequency effectively spreads
the EMI noise nearby switching frequency and allows the
use of a cost−effective inductor instead of an AC input line
filter to satisfy the world−wide EMI requirements.
IDS
several
mseconds
Leading−Edge Blanking (LEB)
At the instant the internal SENSEFET is turned on, the
primary−side capacitance and secondary−side rectifier
diode reverse recovery typically cause a high−current spike
through the SENSEFET. Excessive voltage across the
RSENSE resistor leads to incorrect feedback operation in the
current−mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit (see the Figure 17). This circuit inhibits the PWM
comparator for a short time (tLEB) after the SENSEFET is
turned on.
Protection Circuits
The protective functions include Overload Protection
(OLP), Over−Voltage Protection (OVP), Under−Voltage
Lockout (UVLO), Line Under−Voltage Protection (LUVP),
Abnormal Over−Current Protection (AOCP), and thermal
shutdown power switch. Because these protection circuits
are fully integrated inside the IC without external
components, reliability is improved without increasing cost.
Once a fault condition occurs, switching is terminated and
the SENSEFET remains off. This causes VCC to fall. When
VCC reaches the UVLO stop voltage VSTOP (7 V), the
protection is reset and the internal high− voltage current
source charges the VCC capacitor via the VSTR pin. When
VCC reaches the UVLO start voltage VSTART (8 V), the FPS
resumes normal operation. In this manner, auto−restart can
alternately enable and disable the switching of the power
SENSEFET until the fault condition is eliminated.
tSW=1/fSW
tSW
Dt
fSW
t
fSW+1/2DfSW
no repetition
several
milliseconds
fSW-1/2DfSW
MAX
MAX
t
Figure 16. Frequency Fluctuation Waveform
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8
FSL206MR
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer pin
are shorted, a steep current with extremely high di/dt can
flow through the SENSEFET during the LEB time. Even
though the power switch has OLP (Overload Protection), it
is not enough to protect the FPS in that abnormal case, since
severe current stress is imposed on the SENSEFET until
OLP triggers. The power switch includes the internal AOCP
(Abnormal Over−Current Protection) circuit shown in
Figure 20. When the gate turn−on signal is applied to the
power SENSEFET, the AOCP block is enabled and monitors
the current through the sensing resistor. The voltage across
the resistor is compared with a preset AOCP level. If the
sensing resistor voltage is greater than the AOCP level, the
set signal is applied to the latch, resulting in the shutdown of
the SMPS.
Figure 18. Auto−Restart Protection Waveforms
Overload Protection (OLP)
Overload is defined as the load current exceeding a preset
level due to an unexpected event. In this situation, the
protection circuit should be activated to protect the SMPS.
However, even when the SMPS is operating normally, the
overload protection (OLP) circuit can be activated during
the load transition or startup. To avoid this undesired
operation, the OLP circuit is activated after a specified time
to determine whether it is a transient situation or a true
overload situation. The Current−Mode feedback path limits
the current in the SENSEFET when the maximum PWM
duty cycle is attained. If the output consumes more than this
maximum power, the output voltage (VO) decreases below
its rating voltage. This reduces the current through the
opto−coupler LED, which also reduces the opto−coupler
transistor current, increasing the feedback voltage (VFB). If
VFB exceeds 2.4 V, the feedback input diode is blocked and
the 2.7 mA current source (IDELAY) starts to charge CFB
slowly up. In this condition, VFB increases until it reaches
5 V, when the switching operation is terminated, as shown
in Figure 19. The shutdown delay is the time required to
charge CFB from 2.4 V to 5 V with 2.7 mA current source.
Figure 20. Abnormal Over−Current Protection
Thermal Shutdown (TSD)
The SENSEFET and control IC being integrated makes it
easier to detect the temperature of the SENSEFET. When the
junction temperature exceeds ~135°C, thermal shutdown is
activated and the power switch is restarted after temperature
decreases to 60°C.
Over−Voltage Protection (OVP)
In the event of a malfunction in the secondary−side
feedback circuit or an open feedback loop caused by
a soldering defect, the current through the opto−coupler
transistor becomes almost zero (refer to Figure 17). Then
VFB climbs up in a similar manner to the overload situation,
forcing the preset maximum current to be supplied to the
SMPS until the overload protection is activated. Because
excess energy is provided to the output, the output voltage
may exceed the rated voltage before the overload protection
is activated, resulting in the breakdown of the devices in the
secondary side. To prevent this situation, an over−voltage
protection (OVP) circuit is employed. In general, VCC is
proportional to the output voltage and the FPS uses VCC
instead of directly monitoring the output voltage. If VCC
exceeds 24.5 V, OVP circuit is activated, resulting in
termination of the switching operation. To avoid undesired
activation of OVP during normal operation, VCC should be
designed to be below 24.5 V.
VFB
Overload Protection
2.4V
t12 = CFB × (V(t2 )−V(t1 )) / IDELAY
t1
t2
t
Figure 19. Overload Protection (OLP)
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9
FSL206MR
Line Under−Voltage Protection (LUVP)
Burst Operation
If the input voltage of the converter is lower than the
minimum operating voltage, the converter input current
increases too much, causing components failure. If the input
voltage is low, the converter should be protected. In the
FSL206MR, the LUVP circuit senses the input voltage using
the LS pin and, if this voltage is lower than 1.5 V, the LUVP
signal is generated. The comparator has 0.5 V hysteresis. If
the LUVP signal is generated, the output drive block is shut
down and the output voltage feedback loop is saturated.
To minimize power dissipation in Standby Mode, the
power switch enters Burst Mode. As the load decreases, the
feedback voltage decreases. As shown in Figure 23, the
device automatically enters Burst Mode when the feedback
voltage drops below VBURH. Switching continues until the
feedback voltage drops below VBURL. At this point,
switching stops and the output voltages start to drop at a rate
dependent on the standby current load. This causes the
feedback voltage to rise. Once it passes VBURH, switching
resumes. The feedback voltage then falls and the process
repeats. Burst Mode alternately enables and disables
switching of the SENSEFET and reduces switching loss in
Standby Mode.
−
+
Figure 21. Line UVP Circuit
Soft−Start
The FSL206MR has an internal soft−start circuit that
slowly increases the feedback voltage, together with the
SENSEFET current, after it starts. The typical soft−start
time is 15 ms, as shown in Figure 22, where progressive
increments of the SENSEFET current are allowed during the
startup phase. The pulse width to the power switching device
is progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors. The
voltage on the output capacitors is progressively increased
with the intention of smoothly establishing the required
output voltage. It also helps prevent transformer saturation
and reduce the stress on the secondary diode.
Figure 23. Burst−Mode Operation
Figure 22. Internal Soft−Start
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.42x6.38, 2.54P
CASE 646CM
ISSUE O
DATE 31 JUL 2016
9.83
9.00
5
8
6.670
6.096
1
4
8.255
7.610
TOP VIEW
1.65
1.27
(0.56)
7.62
3.683
3.200
5.08 MAX
3.60
3.00
0.33 MIN
0.560
0.355
2.54
15°
0°
0.356
0.200
7.62
9.957
7.870
FRONT VIEW
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS−001, VARIATION BA
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M−2009
DOCUMENT NUMBER:
DESCRIPTION:
98AON13468G
PDIP8 9.42X6.38, 2.54P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.59x6.6, 2.54P
CASE 646CN
ISSUE O
DATE 31 JUL 2016
[
]
0.400 10.160
0.355 9.017
8
5
[ ]
0.280 7.112
0.240 6.096
1
HALF LEAD STYLE 4X
0.031 [0.786] MIN
MAX 0.210 [5.334]
4
FULL LEAD STYLE 4X
0.010 [0.252] MIN
0.195 4.965
0.115 2.933
[ ]
[ ]
0.325 8.263
0.300 7.628
0.015 [0.389] GAGE PLANE
PIN 1 INDICATOR
SEATING PLANE
[ ]
0.150 3.811
0.115 2.922
C
MIN 0.015 [0.381]
0.100 [2.540]
(0.031 [0.786])4X
0.430 [10.922]
MAX
[ ]
0.022 0.562
0.014 0.358
0.10
0.300 [7.618]
0.070 1.778 4X FOR 1/2 LEAD STYLE
0.045 1.143 8X FOR FULL LEAD STYLE
[ ]
C
NOTES:
A)THIS PACKAGE CONFORMS TO
JEDEC MS−001 VARIATION BA WHICH DEFINES
2 VERSIONS OF THE PACKAGE TERMINAL STYLE WHICH ARE SHOWN HERE.
B) CONTROLING DIMS ARE IN INCHES
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSION
S AND TOLERANCES PER ASME Y14.5M−2009
DOCUMENT NUMBER:
STATUS:
98AON13470G
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
http://onsemi.com
PDIP8 9.59X6.6, 2.54P
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON13470G
PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION FROM FAIRCHILD N08M TO ON
SEMICONDUCTOR. REQ. BY I. CAMBALIZA.
DATE
31 JUL 2016
ON Semiconductor and
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. O
Case Outline Number:
646CN
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 GW
CASE 709AJ
ISSUE O
DATE 31 JAN 2017
DOCUMENT NUMBER:
STATUS:
98AON13756G
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
PDIP8 GW
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
Case Outline Number:
PAGE 1 OFXXX
2
DOCUMENT NUMBER:
98AON13756G
PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION FROM FAIRCHILD MKT−MLSOP08A TO ON
SEMICONDUCTOR. REQ. BY D. TRUHITTE.
DATE
31 JAN 2017
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. O
Case Outline Number:
709AJ
ON Semiconductor and
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