Green Mode Power Switch
for Valley Switching
Converter - Low EMI and
High Efficiency
FSQ0365, FSQ0265,
FSQ0165, FSQ321
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Description
A Valley Switching Converter generally shows lower EMI and
higher power conversion efficiency than a conventional
hard−switched converter with a fixed switching frequency. The
FSQ−series is an integrated Pulse−Width Modulation (PWM)
controller and SENSEFET® specifically designed for valley switching
operation with minimal external components. The PWM controller
includes an integrated fixed−frequency oscillator, under−voltage
lockout, Leading−Edge Blanking (LEB), optimized gate driver,
internal soft−start, temperature−compensated precise current sources
for loop compensation, and self−protection circuitry.
Compared with discrete MOSFET and PWM controller solutions,
the FSQ−series reduces total cost, component count, size and weight;
while simultaneously increasing efficiency, productivity, and system
reliability. This device provides a basic platform for cost−effective
designs of valley switching fly−back converters.
Features
• Optimized for Valley Switching Converter (VSC)
• Low EMI through Variable Frequency Control and Inherent
PDIP−8
CASE 626−05
PDIP8 GW
CASE 709AJ
MARKING DIAGRAM
$Y&E&Z&2&K
FSQxxxx
$Y
&E
&Z
&2
&K
FSQxxxx
= ON Semiconductor Logo
= Designated Space
= Assembly Plant Code
= 2−Digit Date code format
= 2−Digits Lot Run Traceability Code
= Specific Device Code Data
Frequency Modulation
• High Efficiency through Minimum Voltage Switching
• Narrow Frequency Variation Range Over Wide Load and Input
Voltage Variation
• Advanced Burst−Mode Operation for Low Standby Power
•
•
•
•
•
•
Consumption
Pulse−by−Pulse Current Limit
Protection Functions: Overload Protection (OLP), Over−Voltage
Protection (OVP), Abnormal Over−Current Protection (AOCP),
Internal Thermal Shutdown (TSD)
Under−Voltage Lockout (UVLO) with Hysteresis
Internal Startup Circuit
Internal High−Voltage SENSEFET: 650 V
Built−in Soft−Start: 15 ms
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Applications
• Power Supplies for DVD Player,
DVD Recorder, Set−Top Box
• Adapter
• Auxiliary Power Supply for PC, LCD TV,
and PDP TV
Related Application Notes
•
•
•
•
http://www.onsemi.com/pub/Collateral/AN−4137.pdf.pdf
http://www.onsemi.com/pub/Collateral/AN−4141.pdf.pdf
http://www.onsemi.com/pub/Collateral/AN−4150.pdf.pdf
https://www.onsemi.com/pub/Collateral/AN−4134.PDF
© Semiconductor Components Industries, LLC, 2017
December, 2020 − Rev. 3
1
Publication Order Number:
FSQ0365/D
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 1. ORDERING INFORMATION
Maximum Output Table(1)
230 VAC +15%(2)
Part Number
Package
85 − 265 VAC
Open
Adapter(3) Frame(4)
Shipping†
Operating
Temperature
−40 to +85°C
0.6 A
19 W
8W
12W
7W
10W
−40 to +85°C
0.9 A
10 W
10W
15W
9W
13W
−40 to +85°C
1.2 A
6W
14W
20W
11W
16W
−40 to +85°C
1.5 A
4.5 W
17.5W
25W
13W
19W
FSQ321
PDIP−8
3000 / Tube
FSQ321LX
PDIP8 GW
1000 / Tape & Reel
FSQ0165RN
PDIP−8
3000 / Tube
FSQ0165RLX
PDIP8 GW
1000 / Tape & Reel
FSQ0265RN
PDIP−8
3000 / Tube
FSQ0265RLX
PDIP8 GW
1000 / Tape & Reel
FSQ0365RN
PDIP−8
3000 / Tube
FSQ0365RLX
PDIP8 GW
1000 / Tape & Reel
Current RDS(ON)
Limit
(Max.) Adapter(3)
Open
Frame(4)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. The junction temperature can limit the maximum output power.
2. 230 VAC or 100/115 VAC with voltage doubler. The maximum power with CCM operation.
3. Typical continuous power in a non−ventilated, enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open−frame design at 50°C ambient temperature.
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2
FSQ0365, FSQ0265, FSQ0165, FSQ321
Application Circuit
Vo
AC
IN
V str
Drain
PWM
Sync
GND
V fb
V cc
Figure 1. Typical Flyback Application
Internal Block Diagram
Vstr
Sync
4
5
Vcc
Drain
2
6 7 8
+
OSC
0.7V/0.2V
−
+
+
V ref
VCC
Idelay
Vfb
3
0.35/0. 55
VBurst
V ref
VCC Good
−
−
8V/12V
IFB
PWM
3R
R
Soft−
Start
LEB
200ns
S
Q
R
Q
Gate
Driver
AOCP
1
6V
TSD
S
Q
R
Q
VSD
Sync
V ovp
2.5ms Time
Delay
VOCP
(1.1V)
6V
VCC Good
FSQ0365RN Rev.00
Figure 2. Internal Block Diagram
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3
GND
FSQ0365, FSQ0265, FSQ0165, FSQ321
Pin Assignments
GND
VCC
VFB
Drain
8−DIP
8−LSOP
Drain
Drain
VSTR
Sync
Figure 3. Pin Configuration (Top View)
Table 2. PIN DEFINITIONS
Pin#
Name
Description
1
GND
SENSEFET source terminal on primary side and internal control ground.
2
VCC
Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied
from pin 5 (Vstr) via an internal switch during startup (see Figure 2).
It is not until VCC reaches the UVLO upper threshold (12 V) that the internal startup switch opens and device power is supplied via the auxiliary transformer winding.
3
Vfb
The feedback voltage pin is the non−inverting input to the PWM comparator. It has a 0.9 mA current source
connected internally while a capacitor and opto-coupler are typically connected externally. There is a time
delay while charging external capacitor Cfb from 3 V to 6 V using an internal 5 μA current source. This delay
prevents false triggering under transient conditions, but still allows the protection mechanism to operate
under true overload conditions.
4
Sync
This pin is internally connected to the sync−detect comparator for valley switching. Typically the voltage of
the auxiliary winding is used as Sync input voltage and external resistors and capacitor are needed to make
delay to match valley point. The threshold of the internal sync comparator is 0.7 V / 0.2 V.
5
Vstr
This pin is connected to the rectified AC line voltage source. At startup, the internal switch supplies internal
bias and charges an external storage capacitor placed between the Vcc pin and ground. Once the VCC
reaches 12 V, the internal switch is opened.
6, 7, 8
Drain
The drain pins are designed to connect directly to the primary lead of the transformer and are capable of
switching a maximum of 650 V. Minimizing the length of the trace connecting these pins to the transformer
decreases leakage inductance.
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4
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 3. ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Symbol
Parameter
Min.
Max.
Unit
VSTR
Vstr Pin Voltage
500
V
VDS
Drain Pin Voltage
650
V
VCC
Supply Voltage
VFB
Feedback Voltage Range
Sync Pin Voltage
VSync
IDM
EAS
Drain Current Pulsed (Note 5)
Single Pulsed Avalanche Energy (Note 6)
20
V
−0.3
9.0
V
−0.3
9.0
V
FSQ0365
12.0
A
FSQ0265
8.0
FSQ0165
4.0
FSQ321
1.5
FSQ0365
230
FSQ0265
140
FSQ0165
50
FSQ321
10
PD
Total Power Dissipation
TJ
Recommended Operating Junction Temperature
TA
mJ
1.5
W
−40
Internally Limited
°C
Operating Ambient Temperature
−40
+85
°C
TSTG
Storage Temperature
−55
+150
°C
ESD
Human Body Model; JESD22−A114
CLASS 1C
CLASS B
Machine Model; JESD22−A115
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. Repetitive rating: pulse width limited by maximum junction temperature.
6. L = 51 mH, starting TJ = 25°C.
Table 4. THERMAL IMPEDANCE
Symbol
Parameter
Value
Unit
°C/W
8−DIP (Note 7)
qJA
Junction−to−Ambient Thermal Resistance (Note 8)
80
qJC
Junction−to−Case Thermal Resistance (Note 9)
20
qJT
Junction−to−Top Thermal Resistance (Note 10)
35
7. All items are tested with the standards JESD 51−2 and 51−10 (DIP)
8. Free−standing with no heat−sink, under natural convection
9. Infinite cooling condition − refer to the SEMI G30−88
10. Measured on the package top surface.
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FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 5. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
SENSEFET Section
BVDSS
Drain−Source Breakdown Voltage
VCC = 0 V, ID = 100 mA
IDSS
Zero−Gate−Voltage Drain Current
VDS = 650 V
RDS(ON)
CISS
COSS
CRSS
td(on)
tr
td(off)
tf
Drain−Source On−
State Resistance
(Note 11)
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
Turn−On Delay
Rise Time
Turn−Off Delay
Fall Time
650
V
100
A
3.5
4.5
W
FSQ0265
5.0
6.0
FSQ0165
8.0
10.0
FSQ321
14.0
19.0
FSQ0365
FSQ0365
TJ = 25°C, ID = 0.5 A
315
VGS = 0 V, VDS = 25 V, f = 1 MHz
FSQ0265
550
FSQ0165
250
FSQ321
162
FSQ0365
47
VGS = 0 V, VDS = 25 V, f = 1 MHz
FSQ0265
38
FSQ0165
25
FSQ321
18
FSQ0365
17.0
FSQ0165
10.0
FSQ321
3.8
20.0
FSQ0165
12.0
FSQ321
9.5
15
FSQ0165
4
FSQ321
19
ns
28.2
VDD = 350 V, ID = 25 mA
FSQ0265
55.0
FSQ0165
30.0
FSQ321
33.0
FSQ0365
ns
34
VDD = 350 V, ID = 25 mA
FSQ0265
FSQ0365
pF
11.2
VDD = 350 V, ID = 25 mA
FSQ0265
FSQ0365
pF
9.0
VGS = 0 V, VDS = 25 V, f = 1 MHz
FSQ0265
FSQ0365
pF
ns
32
VDD = 350 V, ID = 25 mA
FSQ0265
25
FSQ0165
10
FSQ321
42
ns
Burst−Mode Section
VBURH
Burst−Mode Voltage
TJ = 25°C, tPD = 200 ns (Note 12)
VBURL
VBUR(HYS)
0.45
0.55
0.65
V
0.25
0.35
0.45
V
200
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6
mV
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 5. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) (continued)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Control Section
tON.MAX1
Maximum On Time1
All but FSQ321
TJ = 25°C
10.5
12.0
13.5
ms
tON.MAX2
Maximum On Time2
FSQ321
TJ = 25°C
6.35
7.06
7.77
ms
tB1
Blanking Time1
All but FSQ321
13.2
15.0
16.8
ms
tB2
Blanking Time2
FSQ321
7.5
8.2
ms
tW
Detection Time Window
TJ = 25°C, Vsync = 0 V
3.0
ms
DfS
Switching Frequency Variation (Note 14)
−25°C < TJ < 85°C
±5
±10
%
IFB
Feedback Source Current
VFB = 0 V
900
1100
mA
Minimum Duty Cycle
VFB = 0 V
0
%
UVLO Threshold Voltage
After Turn−on
DMIN
VSTART
VSTOP
700
11
12
13
V
7
8
9
V
tS/S1
Internal Soft−Start Time 1
All but FSQ321
With Free−Running Frequency
15
ms
tS/S2
Internal Soft−Start Time 2
FSQ321
With Free−Running Frequency
10
ms
Protection Section
ILIM
VSD
IDELAY
Peak Current Limit
A
FSQ0365
TJ = 25°C, di/dt = 240 mA/ms
1.32
1.50
1.68
FSQ0265
TJ = 25°C, di/dt = 200 mA/ms
1.06
1.20
1.34
FSQ0165
TJ = 25°C, di/dt = 175 mA/ms
0.8
0.9
1.0
FSQ321
TJ = 25°C, di/dt = 125 mA/ms
0.53
0.60
0.67
Shutdown Feedback Voltage
VCC = 15 V
5.5
6.0
6.5
V
Shutdown Delay Current
VFB = 5 V
4.0
5.0
6.0
mA
tLEB
Leading−Edge Blanking Time(13)
VOVP
Over−Voltage Protection
tOVP
Over−Voltage Protection Blanking Time
TSD
200
ns
5.5
6.0
6.5
V
2
3
4
ms
Thermal Shutdown Temperature (Note 13)
125
140
155
°C
Sync Threshold Voltage
0.55
0.70
0.85
V
0.14
0.20
0.26
V
VCC = 15 V, VFB = 2 V
Sync Section
VSH
VSL
tSync
300
Sync Delay Time (Notes 13, 14)
ns
Total Device Section
IOP
ISTART
ICH
VSTR
1
3
5
mA
VCC = VSTART − 0.1 V
(Before VCC Reaches VSTART)
270
360
450
mA
VCC = 0 V, VSTR = Minimum 40 V
0.65
0.85
1.00
mA
Operating Supply Current
(Control Part Only)
VCC = 15 V
Start Current
Startup Charging Current
26
Minimum VSTR Supply Voltage
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Pulse test: Pulse−Width = 300 ms, duty = 2%
12. Propagation delay in the control IC.
13. Though guaranteed, it is not 100% tested in production.
14. Includes gate turn−on time.
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
1.2
1.0
1.0
Normalized
Normalized
(Characteristics graphs are normalized at TA = 25°C)
0.8
0.6
0.4
0.2
0.0
−25
0.8
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
0
Temperature [ °C]
1.2
1.2
1.0
1.0
0.8
0.6
0.4
0.2
100
125
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Figure 6. UVLO Stop Threshold Voltage (VSTOP)
vs. TA
Figure 7. Startup Charging Current (ICH) vs. TA
1.2
1.2
1.0
1.0
Normalized
Normalized
75
0.8
Temperature [ °C]
0.8
0.6
0.4
0.2
0.0
−25
50
Figure 5. UVLO Start Threshold Voltage (VSTART)
vs. TA
Normalized
Normalized
Figure 4. Operating Supply Current (IOP) vs. TA
0.0
−25
25
Temperature [ °C]
0.8
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 8. Initial Switching Frequency (fS) vs. TA
Figure 9. Maximum On Time (tON.MAX) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
1.2
1.2
1.0
1.0
Normalized
Normalized
(Characteristics graphs are normalized at TA = 25°C)
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0.0
−25
0
25
50
75
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 10. Blanking Time (tB) vs. TA
Figure 11. Feedback Source Current (IFB) vs. TA
1.2
1.2
1.0
1.0
Normalized
Normalized
0.8
0.8
0.6
0.4
0.2
0.0
−25
0.8
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Figure 12. Shutdown Delay Current (IDELAY) vs. TA
Figure 13. Burst Mode High Threshold Voltage
(Vburh) vs. TA
1.2
1.2
1.0
1.0
Normalized
Normalized
Temperature [ °C]
0.8
0.6
0.4
0.2
0.0
−25
0.8
0.6
0.4
0.2
0
25
50
75
Temperature [ °C]
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Figure 14. Burst Mode Low Threshold Voltage
(Vburl) vs. TA
Figure 15. Peak Current Limit (ILIM) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
1.2
1.2
1.0
1.0
Normalized
Normalized
(Characteristics graphs are normalized at TA = 25°C)
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
0
25
50
75
100
125
Temperature [ °C]
Temperature [ °C]
Figure 16. Sync High Threshold (VSH) vs. TA
Figure 17. Sync Low Threshold (VSL) vs. TA
1.2
1.2
1.0
1.0
Normalized
Normalized
0.0
−25
0.8
0.8
0.6
0.4
0.2
0.0
−25
0.8
0.6
0.4
0.2
0
25
50
75
100
0.0
−25
125
Temperature [ °C]
0
25
50
75
100
125
Temperature [ °C]
Figure 18. Shutdown Feedback Voltage (VSD)
vs. TA
Figure 19. Over−Voltage Protection (VOP) vs. TA
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FSQ0365, FSQ0265, FSQ0165, FSQ321
FUNCTIONAL DESCRIPTION
Rsense resistor would lead to incorrect feedback operation in
the Current Mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit. This circuit inhibits the PWM comparator for a short
time (tLEB) after the SENSEFET is turned on.
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(Ca) connected to the VCC pin, as illustrated in Figure 20.
When VCC reaches 12 V, the power switch begins switching
and the internal high−voltage current source is disabled. The
power switch continues its normal switching operation and
the power is supplied from the auxiliary transformer
winding unless VCC goes below the stop voltage of 8 V.
Vref
VCC
Idelay
VFB
VO
IFB
3
FOD817A
D2
3R
+
VDC
VFB*
KA431
−
OLP
VSD
2
5
Figure 21. Pulse−Width−Modulation Circuit
Synchronization
Vref
The FSQ−series employs a valley switching technique to
minimize the switching noise and loss. The basic waveforms
of the valley switching converter are shown in Figure 22. To
minimize the MOSFET’s switching loss, the MOSFET
should be turned on when the drain voltage reaches its
minimum value, as shown in Figure 22. The minimum drain
voltage is indirectly detected by monitoring the VCC
winding voltage, as shown in Figure 22.
VCC good
FSQ0365RN Rev.00
Rsense
FSQ0365RN Rev. 00
Vstr
ICH
8V/12V
Gate
driver
R
Ca
VCC
SENSEFET
OSC
D1
CB
Internal
Bias
Figure 20. Startup Circuit
Feedback Control
Power Switch employs Current Mode control, as shown
in Figure 21. An opto−coupler (such as FOD817A) and
shunt regulator (such as KA431) are often used to
implement the feedback network. Comparing the feedback
voltage with the voltage across the RSENSE resistor makes it
possible to control the switching duty cycle. When the
reference pin voltage of the shunt regulator exceeds the
internal reference voltage of 2.5 V, the opto−coupler LED
current increases, pulling down the feedback voltage and
reducing the duty cycle. This event typically occurs when
input voltage is increased or output load is decreased.
Vds
VRO
VRO
VDC
tF
Vsync
Vovp (6V)
Pulse−by−Pulse Current Limit
Because Current Mode control is employed, the peak
current through the SENSEFET is limited by the inverting
input of PWM comparator (VFB*), as shown in Figure 21.
Assuming that the 0.9mA current source flows only through
the internal resistor (3R + R = 2.8 kW), the cathode voltage
of diode D2 is about 2.5 V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum voltage
of the cathode of D2 is clamped at this voltage, clamping
VFB*. Therefore, the peak value of the current through the
SENSEFET is limited.
0.7V
0.2V
300ns Delay
MOSFET Gate
ON
ON
FSQ0365RN Rev.00
Figure 22. Valley Resonant Switching Waveforms
Protection Circuits
Leading−Edge Blanking (LEB)
At the instant the internal SENSEFET is turned on, a
high−current spike usually occurs through the SENSEFET,
caused by primary−side capacitance and secondary−side
rectifier reverse recovery. Excessive voltage across the
The FSQ−series has several self−protective functions,
such as Overload Protection (OLP), Abnormal
Over−Current protection (AOCP), Over−Voltage Protection
(OVP), and Thermal Shutdown (TSD). All the protections
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11
FSQ0365, FSQ0265, FSQ0165, FSQ321
shutdown is the time required to charge CB from 2.8 V to
6 V with 5 mA. A 20 ~ 50 ms delay is typical for most
applications.
are implemented as Auto−Restart Mode. Once the fault
condition is detected, switching is terminated and the
SENSEFET remains off. This causes VCC to fall. When VCC
falls down to the Under−Voltage Lockout (UVLO) stop
voltage of 8 V, the protection is reset and the startup circuit
charges the VCC capacitor. When the VCC reaches the start
voltage of 12 V, the FSQ−series resumes normal operation.
If the fault condition is not removed, the SENSEFET
remains off and VCC drops to stop voltage again. In this
manner, the auto−restart can alternately enable and disable
the switching of the power SENSEFET until the fault
condition is eliminated. Because these protection circuits
are fully integrated into the IC without external components,
the reliability is improved without increasing cost.
VFB
FSQ0365RN Rev.00
Overload protection
6.0V
2.8V
t12= CFB*(6.0−2.8)/Idelay
t1
VDS
Power
on
Fault
occurs
Abnormal Over−Current Protection (AOCP)
When the secondary rectifier diodes or the transformer
pins are shorted, a steep current with extremely high−di/dt
can flow through the SENSEFET during the LEB time.
Even though the FSQ−series has Overload Protection
(OLP), it is not enough to protect the FSQ−series in that
abnormal case, since severe current stress is imposed on the
SENSEFET until OLP triggers. The FSQ−series has an
internal Abnormal Over−Current Protection (AOCP) circuit
as shown in Figure 25. When the gate turn−on signal is
applied to the power SENSEFET, the AOCP block is
enabled and monitors the current through the sensing
resistor. The voltage across the resistor is compared with a
preset AOCP level. If the sensing resistor voltage is greater
than the AOCP level, the set signal is applied to the latch,
resulting in the shutdown of the SMPS.
12V
8V
t
Normal
operation
Fault
situation
t
Figure 24. Overload Protection
Fault
removed
VCC
FSQ0365RN Rev. 00
t2
Normal
operation
Figure 23. Auto−Restart Protection Waveforms
Overload Protection (OLP)
Overload is defined as the load current exceeding its
normal level due to an unexpected abnormal event. In this
situation, the protection circuit should trigger to protect the
SMPS. However, even when the SMPS is in the normal
operation, the overload protection circuit can be triggered
during load transition. To avoid this undesired operation, the
overload protection circuit is designed to trigger only after
a specified time to determine whether it is a transient
situation or a true overload situation. Because of the
pulse−by−pulse current limit capability, the maximum peak
current through the SENSEFET is limited, and therefore the
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
power, the output voltage (VO) decreases below the set
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
current, thus increasing the feedback voltage (VFB). If VFB
exceeds 2.8 V, D1 is blocked and the 5 mA current source
starts to charge CB slowly up to VCC. In this condition, VFB
continues increasing until it reaches 6 V, when the switching
operation is terminated, as shown in Figure 24. The delay for
3R
OSC
PWM
LEB
200ns
S
Q
R
Q
Gate
driver
R
Rsense
1
GND
+
AOCP
−
FSQ0365RN Rev.00
VOCP
Figure 25. Abnormal Over−Current Protection
Over−Voltage Protection (OVP)
If the secondary−side feedback circuit malfunctions or a
solder defect causes an opening in the feedback path, the
current through the opto−coupler transistor becomes almost
zero. Then VFB climbs up in a similar manner to the overload
situation, forcing the preset maximum current to be supplied
to the SMPS until the overload protection triggers. Because
more energy than required is provided to the output, the
output voltage may exceed the rated voltage before the
www.onsemi.com
12
FSQ0365, FSQ0265, FSQ0165, FSQ321
overload protection triggers, resulting in the breakdown of
the devices in the secondary side. To prevent this situation,
an OVP circuit is employed. In general, the peak voltage of
the sync signal is proportional to the output voltage and the
FSQ−series uses a sync signal instead of directly monitoring
the output voltage. If the sync signal exceeds 6 V, an OVP
is triggered, shutting down the SMPS. To avoid undesired
triggering of OVP during normal operation, the peak voltage
of the sync signal should be designed below 6 V.
VO
VOset
VFB
0.55V
0.35V
IDS
Thermal Shutdown (TSD)
The SENSEFET and the control IC are built in one
package. This makes it easy for the control IC to detect the
abnormal over temperature of the SENSEFET. If the
temperature exceeds ~150°C, the thermal shutdown
triggers.
VDS
Soft−Start
An internal soft−start circuit increases PWM comparator
inverting input voltage with the SENSEFET current slowly
after it starts up. The typical soft−start time is 15 ms. The
pulsewidth to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on the
output capacitors is progressively increased with the
intention of smoothly establishing the required output
voltage. This helps prevent transformer saturation and
reduces stress on the secondary diode during startup.
time
Switching
disabled
FSQ0365RN Rev.00
t1
t2 t3
Switching
disabled
t4
Figure 26. Waveforms of Burst Operation
Switching Frequency Limit
To minimize switching loss and Electromagnetic
Interference (EMI), the MOSFET turns on when the drain
voltage reaches its minimum value in valley switching
operation. However, this causes switching frequency to
increases at light load conditions. As the load decreases, the
peak drain current diminishes and the switching frequency
increases. This results in severe switching losses at
light−load condition, as well as intermittent switching and
audible noise. Because of these problems, the valley
switching converter topology has limitations in a wide range
of applications.
To overcome this problem, FSQ−series employs a
frequency−limit function, as shown in Figure 27 and
Figure 28. Once the SENSEFET is turned on, the next
turn−on is prohibited during the blanking time (tB). After the
blanking time, the controller finds the valley within the
detection time window (tW) and turns on the MOSFET, as
shown in Figure 27 and Figure 28 (cases A, B, and C). If no
valley is found during tW, the internal SENSEFET is forced
to turn on at the end of tW (case D). Therefore, FSQ devices
have a minimum switching frequency of 55kHz and a
maximum switching frequency of 67kHz, as shown in
Figure 28.
Burst Operation
To minimize power dissipation in Standby Mode, the
power switch enters Burst−Mode operation. As the load
decreases, the feedback voltage decreases. As shown in
Figure 26, the device automatically enters Burst Mode when
the feedback voltage drops below VBURL (350 mV). At this
point, switching stops and the output voltages start to drop
at a rate dependent on standby current load. This causes the
feedback voltage to rise. Once it passes VBURH (550 mV),
switching resumes. The feedback voltage then falls and the
process repeats. Burst Mode alternately enables and disables
switching of the power SENSEFET, reducing switching loss
in Standby Mode.
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13
FSQ0365, FSQ0265, FSQ0165, FSQ321
When the resonant period is 2 ms
tsmax=18ms
67kHz
IDS
IDS
A
59kHz
55kHz
A
B
C
Constant
frequency
D
tB=15ms
Burst
mode
ts
IDS
IDS
PO
B
FSQ0365RN Rev. 00
tB=15ms
Figure 28. Switching Frequency Range
ts
IDS
IDS
C
tB=15ms
ts
IDS
IDS
tB=15ms
tsmax=18ms
D
tW=3ms
FSQ0365RN Rev. 00
Figure 27. Valley Switching with Limited Frequency
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14
FSQ0365, FSQ0265, FSQ0165, FSQ321
Typical Application Circuit of FSQ0365RN
Application
Power Switch Device
Input Voltage Range
Rated Output Power
DVD Player
Power Supply
FSQ0365RN
85−265 VAC
19 W
Features
Output Voltage
(Maximum Current)
5.1 V (1.0 A)
3.4 V (1.0 A)
12 V (0.4 A)
16 V (0.3 A)
Key Design Notes
• High efficiency ( > 77% at universal input)
• Low standby mode power consumption (< 1 W at
• The delay time for overload protection is designed to be
230 VAC input and 0.5 W load)
• Reduce EMI noise through Valley Switching operation
• Enhanced system reliability through various protection
•
functions
• Internal soft−start: 15 ms
•
about 30 ms with C107 of 47nF. If faster/slower
triggering of OLP is required, C107 can be changed to
a smaller/larger value (eg. 100 nF for 60 ms).
The input voltage of Vsync must be higher than −0.3 V.
By proper voltage sharing by R106 & R107 resistors,
the input voltage can be adjusted.
The SMD−type 100 nF capacitor must be placed as
close as possible to VCC pin to avoid malfunction by
abrupt pulsating noises and to improved surge
immunity.
Schematic
C209
47pF
T101
EER2828
RT101
5D−9
R105
100kΩ
C104
10nF
630V
R102
56kΩ
C103
33mF
400V
L201
11
1
C210
47pF
2
R108
62Ω
12V, 0.4A
3
10
IC101
FSQ0365RN
1
BD101
Bridge
Diode
3
4
3
4
C102
100nF,275V AC
C105
47nF
50V
Sync
8
Drain
7
Drain
6
Drain
FB
Vcc
Vstr
GND
1
C202
470mF
35V
C201
470mF
35V
L202
D101
1N 4007
2
5
16V, 0.3A
D201
UF4003
D202
UF4003
C203
470mF
35V
C204
470mF
35V
12
L203
C106 C107
100nF 22mF
2 SMD 50V
6
R103
5Ω
D102
1N 4004 R104
12kΩ
5.1V, 1A
D203
SB360
4
C205
1000mF
10V
C206
1000mF
10V
L204
5
9
ZD101
1N4746A
LF101
40mH
3.4V, 1A
D204
SB360
D103
1N4148
R106 R107
6.2kΩ 6.2kΩ
C110
33pF
50V
8
C302
3.3nF
C101
100nF
275VAC
R201
510Ω
R203
6.2kΩ
R202
1kΩ
TNR
10D471K
C208
1000mF
10V
C207
1000mF
10V
R204
20kΩ
C209
100nF
IC202
FOD817A
F101
FUSE
IC201
KA431
AC IN
R205
6kΩ
FSQ0365RN Rev:00
Figure 29. Demo Circuit of FSQ0365RN
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15
FSQ0365, FSQ0265, FSQ0165, FSQ321
Transformer
EER2828
Np/2
12
Np/2
1
11
Np/2 2
3
Na 4
N16V
N16V
10
N12V
N12V
9 N
3.4V
Na
N5.1V
8
6mm
5
3mm
N3.4V
7
Np/2
6 N
5.1V
FSQ0365RN Rev: 00
Figure 30. Transformer Schematic Diagram of FSQ0365RN
Table 6. WINDING SPECIFICATION
Pin (s " f)
No.
Wire
3→2
Np/2
Turns
Winding Method
x1
50
Center Solenoid Winding
0.33φ x 2
4
Center Solenoid Winding
0.33φ x 1
2
Center Solenoid Winding
0.25φ x 1
16
Center Solenoid Winding
0.33φ x 3
14
Center Solenoid Winding
0.33φ x 3
18
Center Solenoid Winding
0.25φ x 1
50
Center Solenoid Winding
0.25φ
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
9→8
N3.4V
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
6→9
N5V
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
4→5
Na
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
10 → 12
N12V
Insulation: Polyester Tape t = 0.050 mm, 3−Layer
11 → 12
N16V
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
2→1
Np/2
Insulation: Polyester Tape t = 0.050 mm, 2−Layer
Table 7. TRANSFORMER ELECTRICAL CHARACTERISTICS
Pin
Specification
Remarks
Inductance
1−3
1.4 mH ± 10%
100 kHz, 1 V
Leakage
1−3
25 mH Maximum
Short All Other Pins
Core & Bobbin
Core: EER2828 (Ae = 86.66 mm2)
Bobbin: EER2828
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16
FSQ0365, FSQ0265, FSQ0165, FSQ321
Table 8. EVALUATION BOARD PART LIST
Part
Value
Note
Part
Value
L201
10 mH
Note
Resistor
Inductor
R102
56 kW
1W
R103
5W
1/2 W
L202
10 mH
R104
12 kW
1/4 W
L203
4.9 mH
R105
100 kW
1/4 W
L204
4.9 mH
R106
6.2 kW
1/4 W
R107
6.2 kW
1/4 W
D101
IN4007
R108
62 W
1W
D102
IN4004
R201
510 W
1/4 W
ZD101
1N4746A
R202
1 kW
1/4 W
D103
1N4148
R203
6.2 kW
1/4 W
D201
UF4003
R204
20 kW
1/4 W
D202
UF4003
R205
6 kW
1/4 W
D203
SB360
D204
SB360
Diode
Capacitor
C101
100 nF / 275 VAC
Box Capacitor
C102
100 nF / 275 VAC
Box Capacitor
C103
33 mF / 400 V
Electrolytic Capacitor
IC101
FSQ0365RN
Power Switch
C104
10 nF / 630 V
Film Capacitor
IC201
KA431 (TL431)
Voltage reference
C105
47 nF / 50 V
Mono Capacitor
IC202
FOD817A
Opto−coupler
C106
100 nF / 50 V
SMD (1206)
C107
22 mF / 50 V
Electrolytic Capacitor
C110
33 pF / 50 V
Ceramic Capacitor
C201
470 mF / 35 V
Electrolytic Capacitor
C202
470 mF / 35 V
Electrolytic Capacitor
C203
470 mF / 35 V
Electrolytic Capacitor
C204
470 mF / 35 V
Electrolytic Capacitor
C205
1000 mF / 10 V
Electrolytic Capacitor
C206
1000 mF / 10 V
Electrolytic Capacitor
C207
1000 mF / 10 V
Electrolytic Capacitor
C208
1000 mF / 10 V
Electrolytic Capacitor
C209
100 nF / 50 V
Ceramic Capacitor
IC
Fuse
Fuse
2A/250V
NTC
RT101
5D−9
Bridge Diode
BD101
2KBP06M2N257
Bridge Diode
Line Filter
LF101
40 mH
Transformer
T101
Varistor
TNR
10D471K
SENSEFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 GW
CASE 709AJ
ISSUE O
DATE 31 JAN 2017
DOCUMENT NUMBER:
STATUS:
98AON13756G
ON SEMICONDUCTOR STANDARD
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
October, DESCRIPTION:
2002 − Rev. 0
PDIP8 GW
http://onsemi.com
1
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
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2
DOCUMENT NUMBER:
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PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION FROM FAIRCHILD MKT−MLSOP08A TO ON
SEMICONDUCTOR. REQ. BY D. TRUHITTE.
DATE
31 JAN 2017
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2017
January, 2017 − Rev. O
Case Outline Number:
709AJ
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