MOSFET – Power, N-Channel,
UltraFET
55 V, 75 A, 7 mW
HUF75345G3, HUF75345P3,
HUF75345S3S
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Description
These N−Channel power MOSFETs are manufactured using
the innovative UltraFET process. This advanced process technology
achieves the lowest possible on−resistance per silicon area, resulting
in outstanding performance. This device is capable of withstanding
high energy in the avalanche mode and the diode exhibits very low
reverse recovery time and stored charge. It was designed for use
in applications where power efficiency is important, such as switching
regulators, switching converters, motor drivers, relay drivers,
low−voltage bus switches, and power management in portable
and battery−operated products.
VDSS
RDS(ON) MAX
ID MAX
55 V
7 mW
75 A
D
G
S
Features
• 75 A, 55 V
• Simulation Models
•
•
•
DRAIN (TAB)
SABER®
− Temperature Compensated PSPICEt and
− Thermal Impedance SPICE and SABER Models
Peak Current vs Pulse Width Curve
UIS Rating Curve
These Devices are Pb−Free
TO−247−3
CASE 340CK
Models
G
D
DRAIN (FLANGE)
S
TO−220−3
CASE 340AT
GD
S
DRAIN (FLANGE)
G
D2PAK−3
CASE 418AJ
S
MARKING DIAGRAM
$Y&Z&3&K
75345X
$Y
&Z
&3
&K
75345X
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
= Specific Device Code
X = G/P/S
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2009
March, 2020 − Rev. 3
1
Publication Order Number:
HUF75345S3S/D
HUF75345G3, HUF75345P3, HUF75345S3S
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Package
Brand
HUF75345G3
TO−247−3
75345G
HUF75345P3
TO−220−3
75345P
HUF75345S3ST
D2PAK−3
75345S
MOSFET MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted)
Symbol
Parameter
Value
Unit
VDSS
Drain to Source Voltage (Note 1)
55
V
VDGR
Drain to Gate Voltage (RGS = 20 kW) (Note 1)
55
V
Gate to Source Voltage
±20
V
75
A
VGS
ID
Drain Current
− Continuous (Figure 2)
− Pulsed
IDM
Drain Current
EAS
Pulsed Avalanche Rating
PD
Power Dissipation
TJ, TSTG
TL
Tpkg
Figure 4
Figure 6
(TC = 25°C)
325
W
− Derate Above 25°C
2.17
W/°C
−55 to +175
°C
Maximum Temperature for Soldering Leads at 0.063 in (1.6 mm) from Case for 10 s
300
°C
Maximum Temperature for Soldering Leads Package Body for 10 s
260
°C
Operating and Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. TJ = 25°C to 150°C
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HUF75345G3, HUF75345P3, HUF75345S3S
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
OFF STATE CHARACTERISTICS
Drain to Source Breakdown Voltage
ID = 250 mA, VGS = 0 V (Figure 11)
IDSS
Zero Gate Voltage Drain Current
VDS = 50 V, VGS = 0 V
IGSS
Gate to Source Leakage Current
BVDSS
55
V
1
mA
VDS = 45 V, VGS = 0 V, TC = 150_C
250
VGS = ±20 V
±100
nA
4.0
V
0.007
W
ON STATE CHARACTERISTICS
VGS(TH)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 mA (Figure 10)
RDS(ON)
Drain to Source On Resistance
ID = 75 A, VGS = 10 V (Figure 9)
2
0.006
THERMAL CHARACTERISTICS
RqJC
Thermal Resistance Junction to Case
(Figure 3)
0.46
_C/W
RqJA
Thermal Resistance Junction to Ambient
TO−247
30
_C/W
Thermal Resistance Junction to Ambient
TO−220, D2PAK
62
_C/W
VDD = 30 V, ID = 75 A,
RL = 0.4 W, VGS = 10 V, RGS = 2.5 W
195
ns
SWITCHING CHARACTERISTICS (VGS = 10 V)
tON
td(ON)
tr
td(OFF)
tf
tOFF
Turn-On Time
Turn-On Delay Time
14
ns
Rise Time
118
ns
Turn-Off Delay Time
42
ns
Fall Time
26
ns
Turn-Off Time
98
ns
GATE CHARGE CHARACTERISTICS
Qg(tot)
Total Gate Charge
VGS = 0 V to 20 V,
VDD = 30 V, ID = 75 A, RL = 0.4 W,
Ig(REF) = 1.0 mA (Figure 13)
220
275
nC
Qg(10)
Gate Charge at 10 V
VGS = 0 V to 10 V,
VDD = 30 V, ID = 75 A, RL = 0.4 W,
Ig(REF) = 1.0 mA (Figure 13)
125
165
nC
Qg(th)
Threshold Gate Charge
VGS = 0 V to 2 V,
VDD = 30 V, ID = 75 A, RL = 0.4 W,
Ig(REF) = 1.0 mA (Figure 13)
6.8
10
nC
Qgs
Gate to Source Gate Charge
14
nC
Qgd
Gate to Drain “Miller” Charge
VDD = 30 V, ID = 75 A, RL = 0.4 W,
Ig(REF) = 1.0 mA (Figure 13)
58
nC
VDS = 25 V, VGS = 0 V, f = 1 Mhz
(Figure 12)
4000
pF
1450
pF
450
pF
CAPACITANCE CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SOURCE TO DRAIN DIODE CHARACTERISTICS
VSD
trr
QRR
Source to Drain Diode Voltage
ISD = 75 A
1.25
V
Reverse Recovery Time
ISD = 75 A, dlSD/dt = 100 A/ms
55
ns
Reverse Recovered Charge
ISD = 75 A, dlSD/dt = 100 A/ms
80
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL PERFORMANCE CURVES
TC = 25°C unless otherwise noted
80
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
60
40
20
0
0
25
50
75
100
125
150
0
25
175
50
TC , CASE TEMPERATURE ( oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power
Dissipation vs. Case Temperature
ZQJC, NORMALIZED THERMAL IMPEDANCE
75
Figure 2. Maximum Continuous
Drain Current vs Case Temperature
2
1
DUTY CYCLE − DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
0.01
10−5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZqJC x RqJC + TC
SINGLE PULSE
10−4
10−3
10−2
10−1
100
101
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
2000
TC = 25oC
IDM, PEAK CURRENT (A)
1000
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 − TC
I = I25
150
VGS = 20V
VGS = 10V
100
50
10−5
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10−4
10−3
10−2
t, PULSE WIDTH (s)
Figure 4. Peak Current Capability
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4
10−1
100
101
HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL CHARACTERISTICS (Continued)
TC = 25°C unless otherwise noted
NOTE:
1000
TJ = MAX RATED
TC = 25oC
100 ms
100
If R = 0
tAV = (L)(I AS)/(1.3*RATED BVDSS − VDD)
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
1000
Refer to ON Semiconductor Application Notes
AN−7514 and AN−7515
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV DSS − V DD) +1]
100
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
VDSS(MAX) = 55V
1
1
10
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0.01
200
0.1
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
150
VGS = 5V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
VGS = 20V
VGS = 10V
VGS = 7V
VGS = 6V
90
60
30
0
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
TC = 25oC
0
1
2
3
120
90
60
25oC
30
0
4
175oC
0
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
1.2
2.0
1.5
1.0
0
40
80
120
3.0
4.5
VDD = 15V
6.0
7.5
Figure 8. Transfer Characteristics
PULSE DURATION = 80 ms, VGS = 10V, ID = 75A
DUTY CYCLE = 0.5% MAX
−40
1.5
−55oC
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 7. Saturation Characteristics
0.5
−80
100
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
VDS , DRAIN TO SOURCE VOLTAGE (V)
2.5
10
Figure 6. Unclamped Inductive Switching
Capability
150
120
1
tAV, TIME IN AVALANCHE (ms)
1.0
0.8
0.6
0.4
−80
200
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
VGS = VDS, ID = 250 mA
−40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
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5
200
HUF75345G3, HUF75345P3, HUF75345S3S
TYPICAL CHARACTERISTICS (Continued)
TC = 25°C unless otherwise noted
7000
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
ID = 250 mA
6000
C, CAPACITANCE (pF)
1.2
1.1
1.0
0.9
5000
CISS
4000
3000
2000
COSS
1000
CRSS
0.8
−80
0
−40
0
40
80
120
160
200
0
10
Figure 11. Normalized Drain to Source
Breakdown vs. Junction Temperature
10
20
VDD = 30V
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 75A
ID = 55A
ID = 35A
ID = 20A
2
0
40
50
Figure 12. Capacitance vs. Drain to Source
Voltage
8
0
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (oC)
VGS , GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.3
25
75
50
Qg, GATE CHARGE (nC)
100
Figure 13. Gate Charge Waveforms
for Constant Gate Currents
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6
125
60
HUF75345G3, HUF75345P3, HUF75345S3S
TEST CIRCUITS WAVEFORMS
VDS
BVDSS
tP
L
VARY tp TO OBTAIN
REQUIRED PEAK IAS
RG
+
DUT
VGS
0V
VDS
IAS
tp
−
VDD
VDD
0
IAS
0.01 W
tAV
Figure 14. Unclamped Energy
Test Circuit
Figure 15. Unclamped Energy
Waveforms
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
Qg(10)
VGS
+
DUT
−
VGS = 10V
VGS
VDD
VGS = 2V
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
RL
VDS
+
VGS
−
td(OFF)
tr
tf
90%
90%
VDD
10%
0
10%
DUT
90%
RGS
VGS
10%
0
VGS
Figure 18. Switching Time Test Circuit
50%
50%
PULSE WIDTH
Figure 19. Resistive Switching Waveforms
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HUF75345G3, HUF75345P3, HUF75345S3S
PSPICE Electrical Model
.SUBCKT HUF75345 2 1 3 ; rev 3 Feb 99
CA 12 8 5.55e−9
CB 15 14 5.55e−9
CIN 6 8 3.45e−9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 56.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1e−9
LGATE 1 9 2.6e−9
LSOURCE 3 7 1.1e−9
KGATE LSOURCE LGATE 0.0085
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e−4
RGATE 9 20 0.36
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e−6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.15e−3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*500),3.5))}
.MODEL DBODYMOD D (IS = 6e−12 RS = 1.4e−3 IKF = 20 XTI = 5 TRS1 = 2.75e−3 TRS2 = 5.0e−6 CJO = 5.5e−9 TT =
5.9e−8 M = 0.5 VJ = 0.75)
.MODEL DBREAKMOD D (RS = 2.8e−2 IKF = 30 TRS1 = −4.0e−3 TRS2 = 1.0e−6)
.MODEL DPLCAPMOD D (CJO = 6.75e−9 IS = 1e−30 M = 0.88 VJ = 1.45 FC = 0.5)
.MODEL MMEDMOD NMOS (VTO = 2.93 KP = 13.75 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36)
.MODEL MSTROMOD NMOS (VTO = 3.23 KP = 96 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u Lambda = 0.06)
.MODEL MWEAKMOD NMOS (VTO = 2.35 KP =0.02 IS = 1e−30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL RBREAKMOD RES (TC1 = 8.0e−4 TC2 = 4.0e−6)
.MODEL RDRAINMOD RES (TC1 = 1.5e−1 TC2 = 6.5e−4)
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HUF75345G3, HUF75345P3, HUF75345S3S
.MODEL RSLCMOD RES (TC1 = 1.0e−4 TC2 = 1.05e−6)
.MODEL RSOURCEMOD RES (TC1 = 1.0e−3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = −1.5e−3 TC2 = −2.6e−5)
.MODEL RVTEMPMOD RES (TC1 = −2.75e−3 TC2 = 1.45e−6)
.MODEL S1AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −9.00 VOFF= −4.00)
.MODEL S1BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = −4.00 VOFF= −9.00)
.MODEL S2AMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.00 VOFF= 0.50)
.MODEL S2BMOD VSWITCH (RON = 1e−5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
ESLC
−
−
ESG
+
GATE
1
LGATE
RLGATE
11
+
17
EBREAK 18
50
RDRAIN
6
8
EVTHRES
+ 19 −
8
EVTEMP
RGATE +
18 −
22
9
20
21
DBODY
−
16
MWEAK
6
MMED
MSTRO
LSOURCE
CIN
8
7
RSOURCE
12
S1A
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
−
EDS
19
−
IT
14
+
+
EGS
RLSOURCE
VBAT
5
8
+
−
8
22
RVTHRES
Figure 20. PSPICE Electrical Model
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SOURCE
3
HUF75345G3, HUF75345P3, HUF75345S3S
SABER Electrical Model
REV 3 February 1999
template huf75345 n2, n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 6e−12, xti = 5, cjo = 5.5e−9, tt = 5.9e−8, m=0.5, vj=0.75)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 6.75e−9, is = 1e−30, m = 0.88, vj = 1.45,fc=0.5)
m..model mmedmod = (type=_n, vto = 2.93, kp = 13.75, is = 1e−30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.23, kp = 96, is=1e−30,tox=1,
lambda = 0.06)
m..model mweakmod = (type=_n, vto = 2.35, kp = 0.02, is = 1e−30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e−5, roff = 0.1, von = −9, voff = −4)
sw_vcsp..model s1bmod = (ron = 1e−5, roff = 0.1, von = −4, voff = −9)
sw_vcsp..model s2amod = (ron = 1e−5, roff = 0.1, von = 0, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e−5, roff = 0.1, von = 0.5, voff = 0)
c.ca n12 n8 = 5.55e−9
c.cb n15 n14 = 5.55e−9
c.cin n6 n8 = 3.45e−9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e−9
l.lgate n1 n9 = 2.6e−9
l.lsource n3 n7 = 1.1e−9
k.k1 i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 8e−4, tc2 = 4e−6
res.rdbody n71 n5 = 1.4e−3, tc1 = 2.75e−3, tc2 = 5e−6
res.rdbreak n72 n5 = 2.8e−2, tc1 = −4e−3, tc2 = 1e−6
res.rdrain n50 n16 = 1e−4, tc1 = 1.5e−1, tc2 = 6.5e−4
res.rgate n9 n20 = 0.36
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e−6, tc1 = 1e−4, tc2 = 1.05e−6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.15e−3, tc1 = 1e−3, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = −2.75e−3, tc2 = 1.45e−6
res.rvthres n22 n8 = 1, tc1 = −1.5e−3, tc2 = −2.6e−5
spe.ebreak n11 n7 n17 n18 = 56.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
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HUF75345G3, HUF75345P3, HUF75345S3S
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51−>n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3.5))
}
}
LDRAIN
DPLCAP
5
10
RSLC1
51
RSLC2
RLDRAIN
RDBREAK
72
ISCL
ESG
+
GATE
1
LGATE
RLGATE
RDRAIN
6
8
EVTEMP
RGATE + 18 −
22
9
20
EVTHRES
+ 19 −
8
6
21
71
11
16
MWEAK
DBODY
EBREAK
+
17
18
MMED
MSTRO
CIN
RDBODY
DBREAK
50
−
−
8
LSOURCE
7
RSOURCE
12
S1A
S2A
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
−
EDS
19
−
IT
14
+
+
EGS
RLSOURCE
RBREAK
15
14
13
5
8
+
−
8
RVTHRES
Figure 21. SABER Electrical Model
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11
DRAIN
2
22
VBAT
SOURCE
3
HUF75345G3, HUF75345P3, HUF75345S3S
SPICE Thermal Model
th
JUNCTION
REV 5 February 1999
HUF75345
CTHERM1 th 6 6.3e−3
CTHERM2 6 5 1.5e−2
CTHERM3 5 4 2.0e−2
CTHERM4 4 3 3.0e−2
CTHERM5 3 2 8.0e−2
CTHERM6 2 tl 1.5e−1
RTHERM1
RTHERM1 th 6 5.0e−3
RTHERM2 6 5 1.8e−2
RTHERM3 5 4 5.0e−2
RTHERM4 4 3 8.5e−2
RTHERM5 3 2 1.0e−1
RTHERM6 2 tl 1.1e−1
RTHERM2
CTHERM1
6
CTHERM2
5
SABER Thermal Model
CTHERM3
RTHERM3
SABER thermal model HUF75345
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 6.3e−3
ctherm.ctherm2 6 5 = 1.5e−2
ctherm.ctherm3 5 4 = 2.0e−2
ctherm.ctherm4 4 3 = 3.0e−2
ctherm.ctherm5 3 2 = 8.0e−2
ctherm.ctherm6 2 tl = 1.5e−1
4
CTHERM4
RTHERM4
3
rtherm.rtherm1 th 6 = 5.0e−3
rtherm.rtherm2 6 5 = 1.8e−2
rtherm.rtherm3 5 4 = 5.0e−2
rtherm.rtherm4 4 3 = 8.5e−2
rtherm.rtherm5 3 2 = 1.0e−1
rtherm.rtherm6 2 tl = 1.1e−1
}
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
CASE
Figure 22. Thermal Model
PSPICE is a trademark of MicroSim Corporation.
Saber is a registered trademark of Sabremark Limited Partnership.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
A
DATE 31 JAN 2019
A
E
P1
P
A2
D2
Q
E2
S
B
D
1
2
D1
E1
2
3
L1
A1
L
b4
c
(3X) b
0.25 M
(2X) b2
B A M
DIM
(2X) e
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXX
XXXXXXX
XXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
A
A1
A2
b
b2
b4
c
D
D1
D2
E
E1
E2
e
L
L1
P
P1
Q
S
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
13.08
~
~
0.51 0.93 1.35
15.37 15.62 15.87
12.81
~
~
4.96 5.08 5.20
~
5.56
~
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
6.60 6.80 7.00
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK−3 (TO−263, 3−LEAD)
CASE 418AJ
ISSUE F
SCALE 1:1
GENERIC MARKING DIAGRAMS*
XX
XXXXXXXXX
AWLYWWG
IC
DOCUMENT NUMBER:
DESCRIPTION:
XXXXXXXXG
AYWW
Standard
98AON56370E
AYWW
XXXXXXXXG
AKA
Rectifier
XXXXXX
XXYMW
SSG
DATE 11 MAR 2021
XXXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y
= Year
WW
= Work Week
W
= Week Code (SSG)
M
= Month Code (SSG)
G
= Pb−Free Package
AKA
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
D2PAK−3 (TO−263, 3−LEAD)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
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