J308

J308 JFET VHF/UHF Amplifiers N− Channel — Depletion MAXIMUM RATINGS Rating Drain − Source Voltage Gate−Source Voltage Forward Gate Current Total Device Dissipation @ TA = 25°C Derate above 25°C Junction Temperature Range Storage Temperature Range Symbol VDS VGS IGF PD Value 25 25 10 350 2.8 − 65 to +125 − 65 to +150 Unit Vdc Vdc mAdc mW mW/°C °C °C http://onsemi.com 1 2 3 TJ Tstg CASE 29−11, STYLE 5 TO−92 (TO−226AA) 1 DRAIN 3 GATE 2 SOURCE ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Gate − Source Breakdown Voltage (IG = −1.0 μAdc, VDS = 0) Gate Reverse Current (VGS = −15 Vdc, VDS = 0, TA = 25°C) (VGS = −15 Vdc, VDS = 0, TA = +125°C) Gate Source Cutoff Voltage (VDS = 10 Vdc, ID = 1.0 nAdc) J308 J309 J310 V(BR)GSS IGSS − 25 — — Vdc — — − 1.0 − 1.0 − 2.0 — — — — — −1.0 −1.0 − 6.5 − 4.0 − 6.5 nAdc μAdc Vdc VGS(off) ON CHARACTERISTICS Zero − Gate −Voltage Drain Current(1) (VDS = 10 Vdc, VGS = 0) J308 J309 J310 IDSS mAdc 12 12 24 — — — — — 60 30 60 1.0 Vdc Gate−Source Forward Voltage (VDS = 0, IG = 1.0 mAdc) VGS(f) © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2 1 Publication Order Number: J308/D J308 Characteristic Symbol Min Typ Max Unit SMALL− SIGNAL CHARACTERISTICS Common−Source Input Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) J308 J309 J310 Re(yis) mmhos — — — — — 0.7 0.7 0.5 0.25 16 — — — — — mmhos dB Common−Source Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Common−Gate Power Gain (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) 1. Pulse Test: Pulse Width v 300 μs, Duty Cycle v 3.0%. Re(yos) Gpg SMALL− SIGNAL CHARACTERISTICS (continued) Common−Source Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Common−Gate Input Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 100 MHz) Common−Source Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) J308 J309 J310 Re(yfs) Re(yig) gfs — — 12 12 — — mmhos mmhos μmhos 8000 10000 8000 — — — — — 20000 20000 18000 250 Common−Source Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) Common−Gate Forward Transconductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) J308 J309 J310 J308 J309 J310 gos gfg μmhos μmhos — — — — — — — — 13000 13000 12000 150 100 150 1.8 4.3 — — — — — — 2.5 5.0 Common−Gate Output Conductance (VDS = 10 Vdc, ID = 10 mAdc, f = 1.0 kHz) gog μmhos Gate−Drain Capacitance (VDS = 0, VGS = −10 Vdc, f = 1.0 MHz) Gate−Source Capacitance (VDS = 0, VGS = −10 Vdc, f = 1.0 MHz) Cgd Cgs pF pF FUNCTIONAL CHARACTERISTICS Noise Figure (VDS = 10 Vdc, ID = 10 mAdc, f = 450 MHz) Equivalent Short−Circuit Input Noise Voltage (VDS = 10 Vdc, ID = 10 mAdc, f = 100 Hz) NF en — — 1.5 10 — — dB nV Hz http://onsemi.com 2 J308 50 Ω SOURCE U310 C3 L1 C5 C7 1.0 k +VDD C1 = C2 = 0.8 − 10 pF, JFD #MVM010W. C3 = C4 = 8.35 pF Erie #539−002D. C5 = C6 = 5000 pF Erie (2443−000). C7 = 1000 pF, Allen Bradley #FA5C. RFC = 0.33 μH Miller #9230−30. L1 = One Turn #16 Cu, 1/4″ I.D. (Air Core). L2P = One Turn #16 Cu, 1/4″ I.D. (Air Core). L2S = One Turn #16 Cu, 1/4″ I.D. (Air Core). RFC C1 C2 C4 C6 L2P L2S 50 Ω LOAD Figure 1. 450 MHz Common−Gate Amplifier Test Circuit 60 I D , DRAIN CURRENT (mA) VDS = 10 V 50 40 30 20 10 −5.0 IDSS +25 °C +25 °C TA = −55°C 60 50 40 +150°C +25 °C −55 °C 30 20 IDSS, SATURATION DRAIN CURRENT (mA) 70 70 Yfs , FORWARD TRANSCONDUCTANCE (mmhos) 35 30 25 20 15 10 +150°C −55 °C +150°C +25 °C VDS = 10 V f = 1.0 MHz TA = −55°C +25 °C +150°C 10 0 0 5.0 0 5.0 4.0 3.0 2.0 1.0 0 −1.0 −4.0 −3.0 −2.0 ID − VGS, GATE−SOURCE VOLTAGE (VOLTS) IDSS − VGS, GATE−SOURCE CUTOFF VOLTAGE (VOLTS) VGS, GATE−SOURCE VOLTAGE (VOLTS) Figure 2. Drain Current and Transfer Characteristics versus Gate−Source Voltage Figure 3. Forward Transconductance versus Gate−Source Voltage Yfs , FORWARD TRANSCONDUCTANCE (μmhos) 100 k Yfs 1.0 k Yos, OUTPUT ADMITTANCE (μ mhos) 10 RDS CAPACITANCE (pF) 7.0 120 R DS , ON RESISTANCE (OHMS) Yfs 10 k 96 100 72 Cgs 4.0 48 1.0 k Yos VGS(off) = −2.3 V = VGS(off) = −5.7 V = 10 Cgd 1.0 0 10 24 100 0.01 1.0 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 ID, DRAIN CURRENT (mA) 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 0 VGS, GATE SOURCE VOLTAGE (VOLTS) Figure 4. Common−Source Output Admittance and Forward Transconductance versus Drain Current http://onsemi.com 3 Figure 5. On Resistance and Junction Capacitance versus Gate−Source Voltage J308 |S21|, |S11| 30 VDS = 10 V ID = 10 mA TA = 25°C 3.0 0.85 0.45 S22 2.4 Y12 (mmhos) Y11 0.79 0.39 S21 1.8 0.73 0.33 VDS = 10 V ID = 10 mA TA = 25°C S11 0.6 Y12 0 100 200 300 500 f, FREQUENCY (MHz) 700 1000 0.55 0.15 100 0.61 0.21 S12 200 300 500 f, FREQUENCY (MHz) 700 1000 0.90 0.012 0.92 0.036 0.96 0.048 0.98 |S12|, |S22| 0.060 1.00 |Y11|, |Y21 |, |Y22 | (mmhos) 24 18 12 Y21 Y22 1.2 0.67 0.27 0.024 0.94 6.0 Figure 6. Common−Gate Y Parameter Magnitude versus Frequency θ21, θ11 180° 50° θ22 170° 160° 150° 140° 130° 40° 30° 20° 10° 0° 100 θ21 θ12, θ22 −2 0° 87° −20 ° −40 ° −60 ° −80 ° −100 ° θ12 θ11 VDS = 10 V ID = 10 mA TA = 25°C 700 −120 ° 84° −140 ° −160 ° 83° −180 ° −200 ° 82° 1000 85° 86° Figure 7. Common−Gate S Parameter Magnitude versus Frequency θ11, θ12 −20 ° 120° −40 ° 100° −60 ° 80° −80 ° 60° θ12 −100 ° 40° −120 ° 20° 100 VDS = 10 V ID = 10 mA TA = 25°C 200 300 500 f, FREQUENCY (MHz) θ11 −80 ° −100 ° 1000 θ21 θ21, θ22 θ11 θ22 0 −20 ° −40 ° −60 ° θ21 200 300 500 f, FREQUENCY (MHz) 700 Figure 8. Common−Gate Y Parameter Phase−Angle versus Frequency Figure 9. S Parameter Phase−Angle versus Frequency 8.0 7.0 NF, NOISE FIGURE (dB) 6.0 5.0 Gpg 4.0 NF 3.0 2.0 1.0 0 4.0 6.0 8.0 10 12 14 16 18 ID, DRAIN CURRENT (mA) 20 22 VDD = 20 V f = 450 MHz BW ≈ 10 MHz CIRCUIT IN FIGURE 1 24 21 G pg , POWER GAIN (dB) NF, NOISE FIGURE (dB) 18 15 12 9.0 6.0 3.0 0 24 7.0 26 6.0 5.0 Gpg 4.0 3.0 2.0 1.0 2.0 0 50 100 200 300 f, FREQUENCY (MHz) 500 700 1000 VDS = 10 V ID = 10 mA TA = 25°C CIRCUIT IN FIGURE 1 NF 6.0 18 14 10 G pg , POWER GAIN (dB) 22 Figure 10. Noise Figure and Power Gain versus Drain Current http://onsemi.com 4 Figure 11. Noise Figure and Power Gain versus Frequency J308 C1 S G L1 INPUT RS = 50 Ω C2 L2 C3 U310 D C4 L3 C5 L4 C6 OUTPUT RL = 50 Ω VS SHIELD VD Figure 12. 450 MHz IMD Evaluation Amplifier BW (3 dB) − 36.5 MHz ID − 10 mAdc VDS − 20 Vdc Device case grounded IM test tones − f1 = 449.5 MHz, f2 = 450.5 MHz C1 = 1−10 pF Johanson Air variable trimmer. C2, C5 = 100 pF feed thru button capacitor. C3, C4, C6 = 0.5−6 pF Johanson Air variable trimmer. L1 = 1/8″ x 1/32″ x 1−5/8″ copper bar. L2, L4 = Ferroxcube Vk200 choke. L3 = 1/8″ x 1/32″ x 1−7/8″ copper bar. Amplifier power gain and IMD products are a function of the load impedance. For the amplifier design shown above with C4 and C6 adjusted to reflect a load to the drain resulting in a nominal power gain of 9 dB, the 3rd order intercept point (IP) value is 29 dBm. Adjusting C4, C6 to provide larger load values will result in higher gain, smaller bandwidth and lower IP values. For example, a nominal gain of 13 dB can be achieved with an intercept point of 19 dBm. +40 OUTPUT POWER PER TONE (dBm) +20 0 −20 −40 −60 −80 −100 −120 −120 U310 JFET VDS = 20 Vdc ID = 10 mAdc F1 = 449.5 MHz F2 = 450.5 MHz 3RD ORDER INTERCEPT POINT FUNDAMENTAL OUTPUT 3RD ORDER IMD OUTPUT −100 −40 −20 −60 −80 INPUT POWER PER TONE (dBm) 0 +20 Example of intercept point plot use: Assume two in−band signals of −20 dBm at the amplifier input. They will result in a 3rd order IMD signal at the output of −90 dBm. Also, each signal level at the output will be −11 dBm, showing an amplifier gain of 9.0 dB and an intermodulation ratio (IMR) capability of 79 dB. The gain and IMR values apply only for signal levels below comparison. Figure 13. Two Tone 3rd Order Intercept Point http://onsemi.com 5 J308 PACKAGE DIMENSIONS TO−92 (TO−226AA) CASE 29−11 ISSUE AL A R P L SEATING PLANE B NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. CONTOUR OF PACKAGE BEYOND DIMENSION R IS UNCONTROLLED. 4. LEAD DIMENSION IS UNCONTROLLED IN P AND BEYOND DIMENSION K MINIMUM. INCHES MIN MAX 0.175 0.205 0.170 0.210 0.125 0.165 0.016 0.021 0.045 0.055 0.095 0.105 0.015 0.020 0.500 −−− 0.250 −−− 0.080 0.105 −−− 0.100 0.115 −−− 0.135 −−− MILLIMETERS MIN MAX 4.45 5.20 4.32 5.33 3.18 4.19 0.407 0.533 1.15 1.39 2.42 2.66 0.39 0.50 12.70 −−− 6.35 −−− 2.04 2.66 −−− 2.54 2.93 −−− 3.43 −−− K XX H V 1 D G J C N N SECTION X−X DIM A B C D G H J K L N P R V STYLE 5: PIN 1. DRAIN 2. SOURCE 3. GATE Thermal Clad is a trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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