LC898301XA-MH

DATA SHEET www.onsemi.com Liner Vibrator Driver IC CMOS LSI LC898301XA WLCSP8, 0.78 x 1.58 CASE 567HA Overview The LC898301XA is a Linear Vibrator Driver IC dedicated to haptic feedback actuator and vibrator employed in mobile equipment. Due to the product superior technology, the drive frequency is automatically adjusted to the resonance frequency of the linear vibrator without the use of other external parts. As a result of this very effective drive, the vibration is as powerful as possible using very limited amount of energy compared to classical solutions. The start time and brake time are fully configurable through the I2C setting. Moreover, an automatic braking function has been implemented allowing to optimize the braking time. Finally, a self test mode allows to detect various possible functional defaults during assembly. • Automatic Adjustment to the Resonance Frequency for LRA • • • • • 301 YMW 301 Y M W (150 Hz to 385 Hz) Programmable or Automatic Braking Initial Drive Frequency Adjustment Function Adjustable Drive Voltage through I2C IF Setting EN IF or PWM IF Driving Mode Available by Automatic Detection Support Various Drive Pattern through I2C (1.8 V IF) Low Power Consumption Thanks to the Highly Effective Drive and the Low Power Driving Mode Low Driving Noise (EMI, Audible Band) VBAT Compliant Thermal Shutdown Protection Self Test Mode for Defaults Detection (Open−circuit, Short−circuit and Weak Back EMF) This is a Pb−Free and Halogen Free Device = Specific Device Code = Year = Month = Week ORDERING INFORMATION Device LC898301XA−MH Features • • • • • • MARKING DIAGRAM Package Shipping† WLCSP8 (Pb−Free) 5000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • • • • Linear Vibrator (Vibration and Haptics) Mobile Phone Portable Game Mobile Equipment with Haptics Function © Semiconductor Components Industries, LLC, 2013 May, 2022 − Rev. 3 1 Publication Order Number: LC898301XA/D LC898301XA BLOCK DIAGRAM VBAT RSTB LDO TSD OUT1 EN / PWM Driver Drive signal Generator Linear Vibrator OUT2 SCL SDA Register setting POR OSC VSS Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Parameter Supply Voltage Range Input Voltage Output Voltage Symbol Rating Unit −0.3 to 6.0 V VI1 (Note 1) −0.3 to VDD +0.3 V VI2 (Note 2) −0.3 to 3.3 V VO (Note 3) −0.3 to 3.3 V H−bridge Drive Current IOmax Allowable Power Dissipation PDmax Operating Temperature Range Condition VDDmax Ta = 85°C (Note 4) 200 mA 140 mW Ta −30 to 85 °C Storage Temperature Range Tstsg −55 to 125 °C Input or Output Current II, IO ±20 mA (Note 5) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. RECOMMENDED OPERATING CONDITIONS (Ta = −30 to 85°C, VCC = 0 V) Parameter Symbol Condition Min Max Unit 3.0 5.5 V Supply Voltage Range VDD Input Voltage Range VIN1 (Note 1) 0 VDD V VIN2 (Note 2) 0 1.98 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 1. RSTB pin. 2. EN, SDA, SCL pins. 3. SDA pin. 4. Glass epoxy (50 mm × 40mm , t = 0.9 mm, FR−4). 5. Per an I/O buffer. www.onsemi.com 2 LC898301XA ELECTRIC CHARACTERISTICS DC CHARACTERISTICS (VSS = 0 V, VDD = 3.0 to 5.5 V, Ta = −30 to 85°C) Parameter High Level Input Voltage Symbol VIH Low Level Input Voltage VIL High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Voltage VIH Low Level Input Voltage VIL Low Level Output Voltage VOL Input Leakage Current IIL Min Typ Max Unit Applicable Pins CMOS Conditions 1.40 − − V EN − − 0.32 V CMOS Schmitt 1.50 − − V − − 0.24 V CMOS Schmitt 1.50 − − V − − 0.36 V − − 0.4 V SDA −10 − +10 mA RSTB, EN, SDA, SCL IOL = 4 mA VI = VDD, VSS SDA, SCL RSTB AC INPUT CHARACTERISTICS (VSS = 0 V, VDD = 3.0 to 5.5 V, Ta = −30 to 85°C) Parameter Input PWM Frequency Symbol Ifrq Condition 1% < PWM Duty < 99% Min Typ Max Unit 10.0 − 50.0 kHz Min Typ Max Unit POWER COMSUMPTION (VSS = 0 V, VDD = 3.0 to 5.5 V, Ta = 25°C) Parameter Symbol Condition Stand−by Current Pstb RSTB = “0” − 0.04 2.0 mA Idle Current Pidl RSTB = “1”, EN = “0” − 2.7 − mA Min Typ Max Unit − 2.7 − Vpp − 2.9 − Vpp −10 − +10 % ANALOG CHARACTERISTICS (VSS = 0 V, VDD = 3.7 V, Ta = 25°C) Parameter Symbol Output Voltage Difference OUT1 from OUT2 Vout12 Adjustable Resonance Frequency Range Condition HBPW = max, VOSEL = “00” HBPW = max, VOSEL = “01” Fmo vs typ value Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LC898301XA PIN ASSIGNMENT PIN LIST No Name I/O No 1A OUT1 O 2A OUT2 O 3A GND 4A SCL NOTE: Name I/O 1B VDD P 2B RSTB I P 3B EN I I 4B SDA B I/O → I : input, O: output, B: bi−direction, P: power supply, NC: not connected Pin Layout (PKG: WLP8, 0.4 mm pitch) SDA SCL 4 EN GND 3 RSTB OUT2 2 VDD OUT1 1 B A Bottom View Figure 2. Pin Layout PIN DESCRIPTION ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Signal Name I/O OUT1 O Motor drive pin H−bridge output OUT2 O Motor drive pin H−bridge output RSTB I Reset and Standby control L : enable, H : disable EN I Motor drive ON/OFF EN control or PWM control input I I2C I/F clock pin SDA B I2C I/F data pin VDD P Power supply pin VSS P GND pin SCL NOTE: Function Remarks Open drain I/O → I : input, O: output, B: bi−direction, P: power supply, NC: not connected www.onsemi.com 4 LC898301XA TIMING CHART Motor Drive Timing The EN or PWM input mode is detected automatically after RSTB pin is set to “H”. IF the input mode detection is completed, the result is maintained until RSTB is set to “L”. EN Control Mode The Motor is controlled by EN signal, and the driving time is controlled by keeping EN pin “H”. The High speed start UP time, driving power and Brake time can be modified by I2C setting. The initial driving frequency must be set by I2C I/F at the center of resonance frequency of the linear vibrators, when the initial driving frequency is inadequate. The minimum width of EN signal must be larger than the cycle of initial driving frequency setting. EN OUT1 OUT2 High speed Start UP Time Driving Time (Driving power is adjusted by driving voltage.) Brake Time Figure 3. Stand−by Control (EN Control Mode) The Stand−by mode is controlled by RSTB pin. (RSTB=”L” → Stand−by mode is ON.) When the stand−by mode is “ON”, the register value is set to initial value. So, the register must be set again after the stand−by mode is “OFF”. And, the “EN” signal and I2C command must wait over 200 ms after “RSTB” pin is set to “H”. RSTB 30 ms (min) 200 ms EN Stand−by Driving off I2C Driving ON Brake Driving off Stand−by This period isn’t need, if the brake is not used. Set the registers again Figure 4. EN Control The minimum time of EN = “H” is (1/ the frequency: RESOFRQ). ex) 0 x 02 RESOFRQ = 0 x 0 A (175 Hz) → (min) 5.71 ms EN = “L” just after EN = “H” means brake works. So the minimum time of EN = “L” depends on the remains of vibration. Then when drive time until just before EN = “L”(time of EN= “H” before EN = “L”) is over 30 ms, the minimum time of EN − “L” is 30 ms. When drive time until just before EN = “L”(time of EN = “H” before EN = “L”) is less than 30 ms, the minimum time of EN = “L” is the same time as drive time until just before EN = “L”. (min) the same time as the last drive time when the last drive < 30 ms (min) 30 ms when the last drive ≥ 30 ms EN (min) 1/(the frequency: RESOFRQ) Figure 5. www.onsemi.com 5 LC898301XA PWM Control Mode On this mode the motor is controlled by “PWM” signal, and it is automatically detected. The driving or brake mode is judged by the duty of “PWM” signal. Also the driving power is judged by it. The judgment rule is decided by the table as below. On this mode, 0 × 05 to 0 × 09 registers are available, and the PWM input duty is limited between1% to 99%.When the duty is 0%, the driving is stopped. NOTES: PWM input frequency must be set 128*(Resonance frequency of LRA) in case 0 × 08: RFSEL is set to “0”. The actual driving frequency of the LRA is calculated by Auto Tune function. The period of input PWM detection is about 170 ms after a signal input. NOTE: Duty (%) Driving Mode Resolution 99.00 to 50.39 Forward 127 steps 50.39 to 49.62 Stop − 49.62 to 1.00 Reverse 127 steps Duty: 99.0% is maximum driving, on the other hand, Duty: 1.0% is maximum braking. PWM freq = 128 * (LRA Freq) in case 0 × 08: RFSEL = 0 EN (PWM) OUT1 OUT2 Forward driving Reverse driving Figure 6. Stand−by Control (PWM Control Mode) The Stand−by mode is controlled by RSTB pin. (RSTB=”L” → Stand−by mode is ON.) When the stand−by mode is “ON”, the register value is set to initial value. So, the register must be set again after the stand−by mode is “OFF”. And, the “EN” signal and I2C command must wait over 200 ms after “RSTB” pin is set to “H”. RSTB (min) 200 ms EN PWM input Stand−by Driving off I2C Driving ON Set the registers again Figure 7. www.onsemi.com 6 Driving off Stand−by LC898301XA I2C Serial Interface Writing Format (Sequential Writing is Possible) After the start condition, slave address (7bit) and “L”(Write mode) are received , the flag “ACK = L” is replied. Next, after the 8 bit address is received, the flag “ACK = L” is replied. Next, after the 8 bit write data is received, the flag “ACK = L” is replied. Next, when the stop condition is received, the write data can be written in the specified address. Moreover, it is possible to write data in the incremental address by the continuous input of the 8 bit data confirming the flag “ACK = L” after the every 8 bit write data input. START SLAVE ADDRESS L AC ADDR(N) K AC K ADDR(N) WRITE DATA AC ADDR(N+1)WRITE DATA AC K K ADDR(N+2) WRITE AC K STOP SDA SCL Figure 8. Reading Format (Sequential Reading is Possible) After the dummy writing, the start condition, slave address (7 bit) and “H”(Read mode) are received, the flag “ACK = L” is replied. Next, the 8 bit read data is output. After them, when the stop condition is not received, and the read condition is continued, the read data of incremental address is output one by one. The read condition is end when the end condition is received after the flag “ACK = H”. Dummy writing START SLAVE ADDRESS L AC ADDR(N) K AC K START SLAVE ADDRESS H AC K ADDR(N) READ DATA AC K *1 SDA SCL *1 ADDR(N+1) READ DATA AC ADDR(N+2) READ DATA AC ADDR(N+3) READ DATA AC K SDA SCL Figure 9. Slave Address The Slave Address is as follows. Slave Address 1001001 www.onsemi.com 7 K K END LC898301XA AC CHARACTERISTICS (I2C SERIAL INTERFACE) (VSS = 0 V, VDD = 3.0 to 5.5 V, TA = −30 to 85°C) Parameter Symbol Pin SCL Clock Frequency Min Typ Max Unit Comment fSCL SCL − − 400 kHz tHD; STA SCL SDA 0.6 − − ms SCL Clock Low Width tLOW SCL 1.3 − − ms SCL Clock High Width tHIGH SCL 0.6 − − ms RE−START Condition Setup Time tSU; STA SCL SDA 0.6 − − ms SDA Hold Time tHD; DAT SCL SDA 0 − − ms SDA Setup Time tSU; DAT SCL SDA 0.2 − − ms (Note 6) SDA, SCL Rise Time tr SCL SDA − − 0.3 ms (Note 6) SDA, SCL Fall Time tf SCL SDA − − 0.3 ms (Note 6) STOP Condition Setup Time tSU; STP SCL SDA 0.6 − − ms STOP to START BUS Open Time tBUF SCL SDA 1.3 − − ms START Condition Hold Time 6. Design Assurance (Shipment test none). 90% SDA 90% 10% 10% tHD; DAT tLOW 10% tSU; DAT 10% tHD, STA tr 90% 90% 10% tHIGH 10% tSU; STP tHD; DAT 90% 90% tBUF tSU; DAT 90% SCL 90% 10% 90% 10% tf STOP CONDITION REPEATED CONDITION START CONDITION START CONDITION Figure 10. AC CHARACTERISTICS (POWER ON RESET) (VSS = 0 V, VDD = 3.0 to 5.5 V, Ta = −30°C to +85°C) Parameter VDD Rise Up Time Symbol Min Typ Max Unit Comment tVDDUP − − 100 ms − 90% VDD 10% tVDDUP Figure 11. VDD Rise Up Time Chart www.onsemi.com 8 LC898301XA APPLICATION INFORMATION A Vibration is Controlled by EN & RSTB Pin VBAT 0.1 mF Standby control VDD RSTB Enable control EN Application Processor OUT1 OUT2 SCL SDA I2C IF LRA GND Figure 12. A Vibration is Controlled by PWM Input RSTB Pin VBAT 0.1 mF Standby control PWM Control Application Processor I2C IF VDD RSTB EN OUT1 OUT2 SCL SDA GND Figure 13. www.onsemi.com 9 LRA LC898301XA A Vibration is Controlled by 0 y 09 ENON Register VBAT 0.1 mF Standby control VDD RSTB EN Application Processor Enable control OUT1 OUT2 SCL SDA LRA GND Figure 14. A Vibration is Controlled by RSTB Pin Only VBAT 0.1 mF Standby control VDD RSTB EN Application Processor OUT1 OUT2 SCL SDA 1.8 V GND Figure 15. www.onsemi.com 10 LRA LC898301XA A Vibration is Controlled by VDD Supply Only VDD (ON/OFF control) 1.8 V 0.1 mF RSTB VDD EN OUT1 OUT2 SCL SDA GND Figure 16. onsemi is licensed by the Philips Corporation to carry the I2C bus protocol www.onsemi.com 11 LRA MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP8, 0.78x1.58 CASE 567HA ISSUE O SCALE 4:1 E 2X 2X 0.05 C 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF THE SOLDER BALLS. A B ÈÈ ÈÈ PIN A1 REFERENCE DATE 30 APR 2013 D DIM A A1 b D E e TOP VIEW A 0.10 C 0.08 C A1 SIDE VIEW NOTE 3 MILLIMETERS MIN MAX 0.65 −−− 0.07 0.17 0.15 0.25 0.78 BSC 1.58 BSC 0.40 BSC RECOMMENDED SOLDERING FOOTPRINT* C SEATING PLANE PACKAGE OUTLINE 8X e/2 8X b 0.05 C A B 0.03 C e e/2 e B 2 3 4 BOTTOM VIEW DESCRIPTION: 0.20 0.40 PITCH DIMENSIONS: MILLIMETERS A 1 DOCUMENT NUMBER: 0.40 PITCH 98AON89204E WLCSP8, 0.78X1.58 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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