LM311D

LM211, LM311 Single Comparators The ability to operate from a single power supply of 5.0 V to 30 V or $15 V split supplies, as commonly used with operational amplifiers, makes the LM211/LM311 a truly versatile comparator. Moreover, the inputs of the device can be isolated from system ground while the output can drive loads referenced either to ground, the VCC or the VEE supply. This flexibility makes it possible to drive DTL, RTL, TTL, or MOS logic. The output can also switch voltages to 50 V at currents to 50 mA, therefore, the LM211/LM311 can be used to drive relays, lamps or solenoids. Features http://onsemi.com MARKING DIAGRAMS 8 PDIP−8 N SUFFIX CASE 626 1 1 LM311AN AWL YYWWG • Pb−Free Packages are Available 8 3.0 k VCC VCC 5.0 k 5 2 RL 6 87 Output 1 Inputs 2 + 3 VEE − 4 8 7 1 RL Output 8 1 8 SOIC−8 D SUFFIX CASE 751 1 LMx11 ALYW G + − Inputs 3 4 VEE Split Power Supply with Offset Balance Single Supply VCC 2 Inputs 3 VCC 2 7 Inputs Output 3 + − 4 VEE 8 1 + − 4 8 7 1 RL Output x A WL, L YY, Y WW, W G G = 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Pb−Free Package RL PIN CONNECTIONS GND Inputs 3 1 2 8 Input polarity is reversed when GND pin is used as an output. Ground−Referred Load VEE Input polarity is reversed when GND pin is used as an output. Load Referred to Negative Supply VCC Output Balance/Strobe Balance + − 7 6 5 VEE VCC 2 VCC 2 Inputs 3 4 VEE Load Referred to Positive Supply Strobe Capability Inputs 7 1 1.0 k RL Output 3 4 (Top View) 8 7 Output 1 6 TTL Strobe RL + − + − 8 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 4 VEE Figure 1. Typical Comparator Design Configurations © Semiconductor Components Industries, LLC, 2005 1 July, 2005 − Rev. 5 Publication Order Number: LM211/D LM211, LM311 ORDERING INFORMATION Device LM211D LM211DG LM211DR2 LM211DR2G LM311D LM311DG LM311DR2 LM311DR2G LM311N LM311NG Package SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) PDIP−8 PDIP−8 (Pb−Free) Shipping † 98 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 98 Units / Rail 98 Units / Rail 2500 Units / Tape & Reel 2500 Units / Tape & Reel 50 Units / Rail 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.) Rating Total Supply Voltage Output to Negative Supply Voltage Ground to Negative Supply Voltage Input Differential Voltage Input Voltage (Note 2) Voltage at Strobe Pin Power Dissipation and Thermal Characteristics Plastic DIP Derate Above TA = +25°C Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature Range Symbol VCC +⎥VEE⎥ VO −VEE VEE VID Vin − PD RqJA TA TJ(max) Tstg −25 to +85 +150 −65 to +150 LM211 36 50 30 ±30 ±15 VCC to VCC−5 625 5.0 0 to +70 +150 −65 to +150 LM311 36 40 30 ±30 ±15 VCC to VCC−5 Unit Vdc Vdc Vdc Vdc Vdc Vdc mW mW/°C °C °C °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 2 LM211, LM311 ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted) Note 1 LM211 Characteristic Input Offset Voltage (Note 3) RS ≤ 50 kW, TA = +25°C RS ≤ 50 kW, Tlow ≤ TA ≤ Thigh* Input Offset Current (Note 3) TA = +25°C Tlow ≤ TA ≤ Thigh* Input Bias Current TA = +25°C Tlow ≤ TA ≤ Thigh* Voltage Gain Response Time (Note 4) Saturation Voltage VID ≤ −5.0 mV, IO = 50 mA, TA = 25°C VID ≤−10 mV, IO = 50 mA, TA = 25°C VCC ≥ 4.5 V, VEE = 0, Tlow ≤ TA ≤ Thigh* VID 6≤6.0 mV, Isink ≤ 8.0 mA VID 6≤10 mV, Isink ≤ 8.0 mA Strobe ”On” Current (Note 5) Output Leakage Current VID ≥ 5.0 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA VID ≥ 10 mV, VO= 35 V, TA = 25°C, Istrobe= 3.0 mA VID ≥ 5.0 mV, VO= 35 V, Tlow ≤ TA ≤ Thigh* Input Voltage Range (Tlow ≤ TA ≤ Thigh*) VICR VOL − − − − IS − − − − −14.5 0.75 − 0.23 − 3.0 0.2 − 0.1 −14.7 to 13.8 +2.4 −1.3 1.5 − 0.4 − − 10 − 0.5 +13.0 − − − − − − − − −14.5 − 0.75 − 0.23 3.0 − 0.2 − −14.7 to 13.8 +2.4 −1.3 − 1.5 − 0.4 − − 50 − +13.0 mA nA nA mA V Symbol VIO − − IIO IIB AV − − − − 40 − 0.7 − 1.7 − 45 − 200 200 3.0 4.0 10 20 100 150 − − − − − − − − 40 − 2.0 − 1.7 − 45 − 200 200 7.5 10 50 70 250 300 − − nA nA V/mV ns V Min Typ Max Min LM311 Typ Max Unit mV Positive Supply Current Negative Supply Current ICC IEE − − +6.0 −5.0 − − +7.5 −5.0 mA mA * LM211: Tlow = −25°C, Thigh = +85°C LM311: Tlow = 0°C, Thigh = +70°C 1. Offset voltage, offset current and bias current specifications apply for a supply voltage range from a single 5.0 V supply up to ±15 V supplies. 2. This rating applies for ±15 V supplies. The positive input voltage limit is 30 V above the negative supply. The negative input voltage limit is equal to the negative supply voltage or 30 V below the positive supply, whichever is less. 3. The offset voltages and offset currents given are the maximum values required to drive the output within a volt of either supply with a 1.0 mA load. Thus, these parameters define an error band and take into account the “worst case” effects of voltage gain and input impedance. 4. The response time specified is for a 100 mV input step with 5.0 mV overdrive. 5. Do not short the strobe pin to ground; it should be current driven at 3.0 mA to 5.0 mA. 8 VCC Balance Balance/Strobe 5 6 1.3 k 300 300 3.7 k 1.3 k 100 3.7 k 300 250 900 600 800 2 Inputs 3 730 340 1.3 k 1 1.3 k 5.4 k 4 VEE GND 5.0 k 7 200 Output 800 800 3.0 k Figure 2. Circuit Schematic http://onsemi.com 3 LM211, LM311 140 I IB , INPUT BIAS CURRENT (nA) 120 100 80 Normal Pins 5 & 6 Tied to VCC 5.0 I IO , INPUT OFFSET CURRENT (nA) VCC = +15 V VEE = −15 V VCC = +15 V VEE = −15 V Pins 5 & 6 Tied to VCC 4.0 3.0 2.0 40 0 −55 1.0 0 −55 Normal −25 0 25 50 75 100 125 −25 0 25 50 75 100 125 TA, TEMPERATURE (°C) TA, TEMPERATURE (°C) Figure 3. Input Bias Current versus Temperature Figure 4. Input Offset Current versus Temperature 140 I IB , INPUT BIAS CURRENT (nA) COMMON MODE LIMITS (V) 120 100 80 60 40 20 0 −16 −12 −8.0 −4.0 0 4.0 8.0 12 16 VCC = +15 V VEE = −15 V TA = +25°C VCC −0.5 −1.0 −1.5 Referred to Supply Voltages 0.4 0.2 VEE −55 −25 0 25 50 75 100 125 DIFFERENTIAL INPUT VOLTAGE (V) TA, TEMPERATURE (°C) Figure 5. Input Bias Current versus Differential Input Voltage Figure 6. Common Mode Limits versus Temperature Vin ,INPUT VOLTAGE (mV) VO , OUTPUT VOLTAGE (V) Vin ,INPUT VOLTAGE (mV) VO , OUTPUT VOLTAGE (V) +5.0 V 5.0 4.0 3.0 2.0 1.0 0 100 50 0 5.0 mV 20 mV Vin +5.0 V * ) 500 W VO 2.0 mV VCC = +15 V VEE = −15 V TA = +25°C 0 0.1 0.2 0.3 0.4 tTLH, RESPONSE TIME (ms) 0.5 0.6 5.0 4.0 3.0 2.0 1.0 0 0 −50 −100 5.0 mV 2.0 mV 20 mV Vin * ) 500 W VO VCC = +15 V VEE = −15 V TA = +25°C 0 0.1 0.2 0.3 0.4 tTHL, RESPONSE TIME (ms) 0.5 0.6 Figure 7. Response Time for Various Input Overdrives Figure 8. Response Time for Various Input Overdrives http://onsemi.com 4 LM211, LM311 Vin ,INPUT VOLTAGE (mV) VO , OUTPUT VOLTAGE (V) Vin ,INPUT VOLTAGE (mV) VO , OUTPUT VOLTAGE (V 15 10 5.0 0 −5.0 −10 −15 0 −50 20 mV 5.0 mV VCC Vin * ) VEE VO 2.0 k 2.0 mV 15 10 5.0 0 −5.0 −10 −15 100 50 0 0 VCC 5.0 mV 2.0 mV Vin * ) VEE VO 2.0 k 20 mV VCC = +15 V VEE = −15 V TA = +25°C −100 0 1.0 tTLH, RESPONSE TIME (ms) VCC = +15 V VEE = −15 V TA = +25°C 2.0 1.0 tTHL, RESPONSE TIME (ms) 2.0 Figure 9. Response Time for Various Input Overdrives Figure 10. Response Time for Various Input Overdrives OUTPUT SHORT CIRCUIT CURRENT (mA) 150 TA = +25°C 125 100 75 Short Circuit Current 50 25 0 Power Dissipation 0.90 PD , POWER DISSIPATION (W) V , SATURATION VOLTAGE (V) OL 0.75 0.60 0.45 0.30 0.15 0 15 0.90 0.75 0.60 0.45 0.30 0.15 0 0 8.0 16 24 32 40 48 56 IO, OUTPUT CURRENT (mA) TA = −55°C TA = +25°C TA = +125°C 0 5.0 10 VO, OUTPUT VOLTAGE (V) Figure 11. Output Short Circuit Current Characteristics and Power Dissipation Figure 12. Output Saturation Voltage versus Output Current OUTPUT LEAKAGE CURRENT (mA) 100 POWER SUPPLY CURRENT (mA) VCC = +15 V VEE = −15 V 10 3.6 TA = +25°C 3.0 Positive Supply − Output Low 2.4 1.8 Positive and Negative Power Supply − Output H igh 1.2 0.6 0 45 65 85 105 125 0 5.0 10 15 20 25 30 TA, TEMPERATURE (°C) VCC−VEE, POWER SUPPLY VOLTAGE (V) 1.0 Output VO = +50 V (LM211 only) 0.1 0.01 25 Figure 13. Output Leakage Current versus Temperature Figure 14. Power Supply Current versus Supply Voltage http://onsemi.com 5 LM211, LM311 3.0 2.6 2.2 1.8 1.4 1.0 −55 Positive and Negative Supply − Output High VCC = +15 V VEE = −15 V Postive Supply − Output Low SUPPLY CURRENT (mA) −25 0 25 50 75 TA, TEMPERATURE (°C) 100 125 Figure 15. Power Supply Current versus Temperature APPLICATIONS INFORMATION +15 V 3.0 k 33 k 0.1 mF 8 2 Input R1 C2 R2 3 + 5.0 k C1 0.002 6 mF 5 1 4 0.1 mF −15 V 7 4.7 k Input Output 100 R1 C2 100 R2 2 1.0 M −15 V 510 k 3 + LM311 − 4 0.1 mF 1 5 7 Output 0.1 mF 8 5.0 k C1 82 3.0 k 4.7 k +15 V 6 LM311 − Figure 16. Improved Method of Adding Hysteresis Without Applying Positive Feedback to the Inputs Figure 17. Conventional Technique for Adding Hysteresis VEE VCC = +15 V Balance Adjust Balance Input Inputs 3.0 k Inputs 5.0 k + LM311 VEE VEE = −15 V VCC GND 10 k GND Output to CMOS Logic VEE + LM311 VCC1 VCC Output VCC2 Balance/Strobe 2N2222 or Q1 Equivalent 1.0 k TTL Strobe *D1 *Zener Diode D1 protects the comparator from inductive kickback and voltage transients on the VCC2 supply line. Figure 18. Zero−Crossing Detector Driving CMOS Logic Figure 19. Relay Driver with Strobe Capability http://onsemi.com 6 LM211, LM311 TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS When a high speed comparator such as the LM211 is used with high speed input signals and low source impedances, the output response will normally be fast and stable, providing the power supplies have been bypassed (with 0.1 mF disc capacitors), and that the output signal is routed well away from the inputs (Pins 2 and 3) and also away from Pins 5 and 6. However, when the input signal is a voltage ramp or a slow sine wave, or if the signal source impedance is high (1.0 kW to 100 kW), the comparator may burst into oscillation near the crossing−point. This is due to the high gain and wide bandwidth of comparators like the LM211 series. To avoid oscillation or instability in such a usage, several precautions are recommended, as shown in Figure 16. The trim pins (Pins 5 and 6) act as unwanted auxiliary inputs. If these pins are not connected to a trim−pot, they should be shorted together. If they are connected to a trim−pot, a 0.01 mF capacitor (C1) between Pins 5 and 6 will minimize the susceptibility to AC coupling. A smaller capacitor is used if Pin 5 is used for positive feedback as in Figure 16. For the fastest response time, tie both balance pins to VCC. Certain sources will produce a cleaner comparator output waveform if a 100 pF to 1000 pF capacitor (C2) is connected directly across the input pins. When the signal source is applied through a resistive network, R1, it is usually advantageous to choose R2 of the same value, both for DC and for dynamic (AC) considerations. Carbon, tin−oxide, and metal−film resistors have all been used with good results in comparator input circuitry, but inductive wirewound resistors should be avoided. When comparator circuits use input resistors (e.g., summing resistors), their value and placement are particularly important. In all cases the body of the resistor should be close to the device or socket. In other words, there should be a very short lead length or printed−circuit foil run between comparator and resistor to radiate or pick up signals. The same applies to capacitors, pots, etc. For example, if R1 = 10 kW, as little as 5 inches of lead between the resistors and the input pins can result in oscillations that are very hard to dampen. Twisting these input leads tightly is the best alternative to placing resistors close to the comparator. Since feedback to almost any pin of a comparator can result in oscillation, the printed−circuit layout should be engineered thoughtfully. Preferably there should be a groundplane under the LM211 circuitry (e.g., one side of a double layer printed circuit board). Ground, positive supply or negative supply foil should extend between the output and the inputs to act as a guard. The foil connections for the inputs should be as small and compact as possible, and should be essentially surrounded by ground foil on all sides to guard against capacitive coupling from any fast high−level signals (such as the output). If Pins 5 and 6 are not used, they should be shorted together. If they are connected to a trim−pot, the trim−pot should be located no more than a few inches away from the LM211, and a 0.01 mF capacitor should be installed across Pins 5 and 6. If this capacitor cannot be used, a shielding printed−circuit foil may be advisable between Pins 6 and 7. The power supply bypass capacitors should be located within a couple inches of the LM211. A standard procedure is to add hysteresis to a comparator to prevent oscillation, and to avoid excessive noise on the output. In the circuit of Figure 17, the feedback resistor of 510 kW from the output to the positive input will cause about 3.0 mV of hysteresis. However, if R2 is larger than 100 W, such as 50 kW, it would not be practical to simply increase the value of the positive feedback resistor proportionally above 510 kW to maintain the same amount of hysteresis. When both inputs of the LM211 are connected to active signals, or if a high−impedance signal is driving the positive input of the LM211 so that positive feedback would be disruptive, the circuit of Figure 16 is ideal. The positive feedback is applied to Pin 5 (one of the offset adjustment pins). This will be sufficient to cause 1.0 mV to 2.0 mV hysteresis and sharp transitions with input triangle waves from a few Hz to hundreds of kHz. The positive−feedback signal across the 82 W resistor swings 240 mV below the positive supply. This signal is centered around the nominal voltage at Pin 5, so this feedback does not add to the offset voltage of the comparator. As much as 8.0 mV of offset voltage can be trimmed out, using the 5.0 kW pot and 3.0 kW resistor as shown. http://onsemi.com 7 LM211, LM311 PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE L NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 8 5 −B− 1 4 F NOTE 2 −A− L C −T− SEATING PLANE J N D K M M TA B H G 0.13 (0.005) M M http://onsemi.com 8 LM211, LM311 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AG −X− A 8 5 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M ZY S J X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 9 LM211, LM311 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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