LM555CMX

LM555 Single Timer Features Description • • • • • The LM555 is a highly stable controller capable of producing accurate timing pulses. With a monostable operation, the delay is controlled by one external resistor and one capacitor. With astable operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor. High-Current Drive Capability: 200 mA Adjustable Duty Cycle Temperature Stability of 0.005%/°C Timing From μs to Hours Turn off Time Less Than 2 μs 8-DIP Applications • • • • Precision Timing Pulse Generation Delay Generation Sequential Timing 1 8-SOIC 1 Ordering Information Part Number Operating Temperature Range Top Mark 0 ~ +70°C LM555CM LM555CN LM555CM LM555CMX © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 Package Packing Method LM555CN DIP 8L Rail LM555CM SOIC 8L Rail SOIC 8L Tape & Reel www.fairchildsemi.com 1 LM555 — Single Timer January 2013 LM555 — Single Timer Block Diagram R GND GND 1 Trigger Trigger 2 R Comp. Output Output Reset Reset 3 R 8 VCC Vcc 7 Discharge Discharge 6 Threshold Threshold 5 Control Control Threshold Voltage Voltage Discharging Tr. Discharging Transistor OutPut Stage F/F Comp. 4 VREF Vref Figure 1. Block Diagram Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. Symbol VCC TLEAD PD Parameter Value Unit Supply Voltage 16 V Lead Temperature (Soldering 10s) 300 °C Power Dissipation 600 mW 0 ~ +70 °C -65 ~ +150 °C TOPR Operating Temperature Range TSTG Storage Temperature Range © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 2 Values are at TA = 25°C, VCC = 5 ~ 15 V unless otherwise specified. Parameter Symbol Supply Voltage VCC Supply Current (Low Stable) (1) ICC Timing Error (Monostable) Initial Accuracy (2) ACCUR Drift with Temperature (3) Δt / ΔT Drift with Supply Voltage (3) Timing Error (Astable) InItial Accuracy (2) Drift with Temperature (3) Drift with Supply Voltage (3) Control Voltage Δt / ΔT Trigger Voltage 4.5 Trigger Current ITR VRST Reset Current IRST Low Output Voltage VOL V 6 mA VCC = 15 V, RL = ∞ 7.5 15.0 mA 1.0 3.0 % RA = 1 kΩ to100 kΩ C = 0.1 μF 50 0.1 RA = 1 kΩ to 100kΩ C = 0.1 μF VCC = 15 V 9.0 VCC = 5 V 2.60 VOH (3) Fall Time of Output Discharge Leakage Current 0.5 %/V 2.25 % 150 ppm / °C 0.3 %/V 10.0 11.0 3.33 4.00 V V 10.0 V VCC = 5V 3.33 V 0.10 0.25 μA VCC = 5 V 1.10 1.67 2.20 V VCC = 15 V 4.5 5.0 5.6 V 0.01 2.00 μA 0.7 1.0 V 0.1 0.4 mA ISINK = 10 mA 0.06 0.25 V ISINK = 50 mA 0.30 0.75 V 0.05 0.35 V VTR = 0 V 0.4 VCC = 15 V VCC = 15 V ISOURCE = 200 mA ISOURCE = 100 mA 12.5 V 12.75 13.30 V 2.75 3.30 V tR 100 ns tF 100 ILKG 20 VCC = 5 V, ISOURCE = 100 mA Rise Time of Output(3) ppm / °C VCC = 15 V VCC = 5 V, ISINK = 5 mA High Output Voltage Unit 16.0 ITH Reset Voltage Max. 3 Δt / ΔVCC VTR Typ. VCC = 5 V, RL = ∞ ACCUR VTH (4) Min. Δt / ΔVCC VC Threshold Voltage Threshold Current Conditions ns 100 nA Notes: 1. When the output is high, the supply current is typically 1 mA less than at VCC = 5 V. 2. Tested at VCC = 5.0 V and VCC = 15 V. 3. These parameters, although guaranteed, are not 100% tested in production. 4. This determines the maximum value of RA + RB for 15 V operation, the maximum total R = 20 MΩ, and for 5 V operation, the maximum total R = 6.7 MΩ. © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 3 LM555 — Single Timer Electrical Characteristics Table 1 below is the basic operating table of 555 timer. Table 1. Basic Operating Table Reset (PIN 4) VTR (PIN 2) VTH (PIN 6) Discharging Transistor (PIN 7) Output (PIN 3) Low X X Low ON High < 1/3 VCC X High OFF High > 1/3 VCC > 2/3 VCC Low ON High > 1/3 VCC < 2/3 VCC Previous State When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output again at high. 1. Monostable Operation 2 3 6 OUT C1 Ω 10 M Ω 10 kΩ 0 10 -1 10 -2 10 CONT 5 1 1M THRES 10 0k Ω 7 TRIG GND RL DISCH 1 =1 kΩ Vcc 10 A RESET Trigger RA 2 R 8 10 Capacitance(uF) 4 +Vcc C2 -3 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 Time Delay(s) Figure2. Monostable Circuit Figure 3. Resistance and Capacitance vs. Time Delay (tD) Figure 4. Waveforms of Monostable Operation © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 4 LM555 — Single Timer Application Information Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low, the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging the external capacitor C1 and setting the flip-flop output at the same time. The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takes for the VC1 to reach 2 VCC/3. In other words, the time constant RAC controls the output pulse width. When the applied voltage to the capacitor C1 reaches 2 VCC/3, the comparator on the trigger terminal resets the flipflop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low. In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant relationship based on RA and C. Figure 4 shows the general waveforms during the monostable operation. It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of VCC/3 before the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse remains at below VCC/3. Figure 5 shows such a timer output abnormality. Figure 5. Waveforms of Monostable Operation (abnormal) 2. Astable Operation +Vcc 100 RA 7 0.01 CONT 5 1 Ω RL Ω C1 GND 0.1 M 10 3 OUT 1M RB THRES 6 1 Ω 0k 10 TRIG kΩ 10 DISCH 2 10 Capacitance(uF) 8 Vcc Ω 1k 4 RESET (RA+2RB) C2 1E-3 100m 1 10 100 1k 10k 100k Frequency(Hz) Figure 6. A Stable Circuit Figure 7. Capacitance and Resistance vs. Frequency © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 5 LM555 — Single Timer 1. Monostable Operation LM555 — Single Timer Figure 8. Waveforms of Astable Operation An astable timer operation is achieved by adding resistor RB to Figure 2 and configuring as shown on Figure 6. In the astable operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi-vibrator. When the timer output is high, its internal discharging transistor. turns off and the VC1 increases by exponential function with the time constant (RA+RB)*C. When the VC1, or the threshold voltage, reaches 2 VCC/3; the comparator output on the trigger terminal becomes high, resetting the F/F and causing the timer output to become low. This turns on the discharging transistor and the C1 discharges through the discharging channel formed by RB and the discharging transistor. When the VC1 falls below VCC/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The discharging transistor turns off and the VC1 rises again. In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from VCC/3 to 2 VCC/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2 VCC/3 to VCC/3. When timer output is high, the equivalent circuit for charging capacitor C1 is as follows: RA RB Vcc C1 dv V – V ( 0- ) c1 cc C ------------- = ------------------------------1 dt R +R A B V C1 ( 0+ ) = V CC ⁄ 3 Vc1(0-)=Vcc/3 (1) (2) t  -  – -------------------------------------   ( R + R )C1   A B 2  1 – --- e  V (t) = V  C1 CC  3     (3) Since the duration of the timer output high state (tL) is the amount of time it takes for the VC1(t) to reach 2 VCC/3, tH    -  – -------------------------------------   ( R A + R B )C1    2 2 V ( t ) = --- V =V  1 – --- e  C1 3 CC 3 CC       t H = C ( R + R )In2 = 0.693 ( R + R )C 1 A B A B 1 (4) (5) © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 6 LM555 — Single Timer The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows: RB C1 VC1(0-)=2Vcc/3 RD dv C1 1 C --------------- + -----------------------V =0 1 dt C1 R +R A B V C1 2 ( t ) = --- V 3 CC e (6) t - ------------------------------------( R A + R D )C1 ( 7) Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach VCC/3, t L ------------------------------------- ( RA + RD )C1 1 2 --- V = ---V ( 8) 3 CC 3 CC e t = C ( R + R )In2 = 0.693 ( R + R )C L 1 B D B D 1 ( 9) Since RD is normally RB>>RD although related to the size of discharging transistor, tL = 0.693RBC1 (10) Consquently, if the timer operates in astable, the period is the same with 't = tH+tL = 0.693(RA+RB)C1+0.693RBC1 = 0.693(RA+2RB)C1' because the period is the sum of the charge time and discharge time. Since frequency is the reciprocal of the period, the following applies: frequency, 1 1.44 f = --- = ---------------------------------------t ( RA + 2RB )C1 ( 11 ) © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 7 By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. Figure 9. Waveforms of Frequency Divider Operation 4. Pulse Width Modulation The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the reference of the timer's internal comparators. Figure 10 illustrates the pulse width modulation circuit. When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to the signal applied to the control terminal. Sine wave, as well as other waveforms, may be applied as a signal to the control terminal. Figure 11 shows the example of pulse width modulation waveform. +Vcc 4 RA 8 RESET Vcc Trigger 7 DISCH 2 TRIG 6 THRES Output 3 OUT Input GND CONT 5 C 1 Figure 10. Circuit for Pulse Width Modulation Figure 11. Waveforms of Pulse Width Modulation © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 8 LM555 — Single Timer 3. Frequency Divider If the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in Figure 12, the timer becomes a pulse position modulator. In the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates the timer output according to the modulation signal applied to the control terminal. Figure 13 illustrates a sine wave for modulation signal and the resulting output pulse position modulation; however, any wave shape be used. +Vcc 4 RA 8 RESET Vcc 7 DISCH 2 TRIG RB 6 THRES Output 3 OUT Modulation GND CONT 5 C 1 Figure 13. Wafeforms of pulse position modulation Figure 12. Circuit for Pulse Position Modluation 6. Linear Ramp When the pull-up resistor RA in the monostable circuit shown in Figure 2 is replaced with constant current source, the VC1 increases linearly, generating a linear ramp. Figure 14 shows the linear ramp generating circuit and Figure 15 illustrates the generated linear ramp waveforms. +Vcc RE 2 4 8 RESET Vcc DISCH 7 THRES 6 R1 Q1 TRIG R2 Output 3 OUT GND C1 CONT 5 1 C2 Figure 15. Waveforms of Linear Ramp Figure 14. Circuit for Linear Ramp © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 9 LM555 — Single Timer 5. Pulse Position Modulation LM555 — Single Timer In Figure 14, current source is created by PNP transistor Q1 and resistor R1, R2, and RE. V CC – V E = --------------------------( 12 ) C R E Here, V E is R 2 V = V + ---------------------- V ( 13 ) E BE R + R CC 1 2 For example, if VCC = 15 V, RE = 20 kΩ, R1 = 5 kΩ, R2 = 10 kΩ, and VBE = 0.7 V, VE=0.7 V+10 V=10.7 V, and IC=(15-10.7) / 20 k=0.215 mA. I When the trigger starts in a timer configured as shown in Figure 14, the current flowing through capacitor C1 becomes a constant current generated by PNP transistor and resistors. Hence, the VC is a linear ramp function as shown in Figure 15. The gradient S of the linear ramp function is defined as follows: Vp – p S = ---------------- t ( 14 ) Here the Vp-p is the peak-to-peak voltage. If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows: V = Q/C (15) The above equation divided on both sides by t gives: Q§t V ---- = ------------C t ( 16 ) and may be simplified into the following equation: S = I/C (17) In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constant current flowing through the capacitor. If the constant current flow through the capacitor is 0.215 mA and the capacitance is 0.02 μF, the gradient of the ramp function at both ends of the capacitor is S = 0.215 m / 0.022 μ = 9.77 V/ms. © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 10 LM555 — Single Timer Physical Dimensions 8-DIP .400 10.15 .373 9.46 [ A ] .036 [0.9 TYP] (.092) [Ø2.337] (.032) [R0.813] PIN #1 .250±.005 [6.35±0.13] PIN #1 B TOP VIEW OPTION 1 TOP VIEW OPTION 2 [ ] .070 1.78 .045 1.14 .310±.010 [7.87±0.25] .130±.005 [3.3±0.13] .210 MAX [5.33] 7° TYP 7° TYP C .015 MIN [0.38] .140 3.55 .125 3.17 .021 0.53 .015 0.37 [ ] .001[.025] C .300 [7.62] [ ] .100 [2.54] .430 MAX [10.92] .060 MAX [1.52] NOTES: A. CONFORMS TO JEDEC REGISTRATION MS-001, VARIATIONS BA B. CONTROLING DIMENSIONS ARE IN INCHES REFERENCE DIMENSIONS ARE IN MILLIMETERS C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. D. DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS SHALL NOT EXCEED .010 INCHES OR 0.25MM. E. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. [ ] +0.127 .010+.005 -.000 0.254-0.000 N08EREVG Figure 16. 8-Lead, DIP, JEDEC MS-001, 300" WIDE Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf. © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 11 LM555 — Single Timer Physical Dimensions (continued) 8-SOIC Figure 17. 8-Lead, SOIC,JEDEC MS-012, 150" NARROW BODY Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. © 2002 Fairchild Semiconductor Corporation LM555 Rev. 1.1.0 www.fairchildsemi.com 12 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I63 © Fairchild Semiconductor Corporation www.fairchildsemi.com