LM833_05

LM833 Low Noise, Audio Dual Operational Amplifier The LM833 is a standard low−cost monolithic dual general−purpose operational amplifier employing Bipolar technology with innovative high−performance concepts for audio systems applications. With high frequency PNP transistors, the LM833 offers low voltage noise (4.5 nV/ Hz ), 15 MHz gain bandwidth product, 7.0 V/ms slew rate, 0.3 mV input offset voltage with 2.0 mV/°C temperature coefficient of input offset voltage. The LM833 output stage exhibits no dead−band crossover distortion, large output voltage swing, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink AC frequency response. For an improved performance dual/quad version, see the MC33079 family. Features 1 LM833N A WL YY WW G http://onsemi.com MARKING DIAGRAMS 8 PDIP−8 N SUFFIX CASE 626 1 = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package LM833N AWL YYWWG • • • • • • • • • Low Voltage Noise: 4.5 nV/ Hz High Gain Bandwidth Product: 15 MHz High Slew Rate: 7.0 V/ms Low Input Offset Voltage: 0.3 mV Low T.C. of Input Offset Voltage: 2.0 mV/°C Low Distortion: 0.002% Excellent Frequency Stability Dual Supply Operation Pb−Free Packages are Available 1 SOIC−8 D SUFFIX CASE 751 1 LM833 A L Y W G LM833 ALYW G MAXIMUM RATINGS Rating Supply Voltage (VCC to VEE) Input Differential Voltage Range (Note 1) Input Voltage Range (Note 1) Output Short Circuit Duration (Note 2) Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature ESD Protection at any Pin − Human Body Model − Machine Model Maximum Power Dissipation (Notes 2 and 3) Symbol VS VIDR VIR tSC TA TJ Tstg Vesd 600 200 PD 500 mW Value +36 30 ±15 Indefinite −40 to +85 +150 −60 to +150 °C °C °C V Unit V V V = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS Output 1 1 8 VCC Output 2 2 1 7 Inputs 1 3 2 6 Inputs 2 5 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Either or both input voltages must not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see power dissipation performance characteristic). 3. Maximum value at TA ≤ 85°C. VEE 4 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2005 1 December, 2005 − Rev. 5 Publication Order Number: LM833/D LM833 ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristic Input Offset Voltage (RS = 10 W, VO = 0 V) Average Temperature Coefficient of Input Offset Voltage RS = 10 W, VO = 0 V, TA = Tlow to Thigh Input Offset Current (VCM = 0 V, VO = 0 V) Input Bias Current (VCM = 0 V, VO = 0 V) Common Mode Input Voltage Range Large Signal Voltage Gain (RL = 2.0 kW, VO = ±10 V) Output Voltage Swing: RL = 2.0 kW, VID = 1.0 V RL = 2.0 kW, VID = 1.0 V RL = 10 kW, VID = 1.0 V RL = 10 kW, VID = 1.0 V Common Mode Rejection (Vin = ±12 V) Power Supply Rejection (VS = 15 V to 5.0 V, −15 V to −5.0 V) Power Supply Current (VO = 0 V, Both Amplifiers) Symbol VIO DVIO/DT IIO IIB VICR AVOL VO+ VO− VO+ VO− CMR PSR ID Min − − − − − −12 90 10 − 12 − 80 80 − Typ 0.3 2.0 10 300 +14 −14 110 13.7 −14.1 13.9 −14.7 100 115 4.0 Max 5.0 − 200 1000 +12 − − − −10 − −12 − − 8.0 dB dB mA Unit mV mV/°C nA nA V dB V AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.) Characteristic Slew Rate (Vin = −10 V to +10 V, RL = 2.0 kW, AV = +1.0) Gain Bandwidth Product (f = 100 kHz) Unity Gain Frequency (Open Loop) Unity Gain Phase Margin (Open Loop) Equivalent Input Noise Voltage (RS = 100 W, f = 1.0 kHz) Equivalent Input Noise Current (f = 1.0 kHz) Power Bandwidth (VO = 27 Vpp, RL = 2.0 kW, THD ≤ 1.0%) Distortion (RL = 2.0 kW, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0) Channel Separation (f = 20 Hz to 20 kHz) Symbol SR GBW fU qm en in BWP THD CS Min 5.0 10 − − − − − − − Typ 7.0 15 9.0 60 4.5 0.5 120 0.002 −120 Max − − − − − − − − − nV pA Unit V/ms MHz MHz ° Hz Hz kHz % dB PD , MAXIMUM POWER DISSIPATION (mW) 800 IIB , INPUT BIAS CURRENT (nA) 1000 800 600 400 200 0 −55 VCC = +15 V VEE = −15 V VCM = 0 V 600 400 200 0 −50 0 50 100 TA, AMBIENT TEMPERATURE (°C) 150 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 1. Maximum Power Dissipation versus Temperature Figure 2. Input Bias Current versus Temperature http://onsemi.com 2 LM833 800 I IB , INPUT BIAS CURRENT (nA) I S , SUPPLY CURRENT (mA) TA = 25°C 600 10 8.0 6.0 4.0 2.0 0 IS VCC RL = ∞ TA = 25°C VO VEE + 400 200 0 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 0 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 Figure 3. Input Bias Current versus Supply Voltage Figure 4. Supply Current versus Supply Voltage 110 AVOL, DC VOLTAGE GAIN (dB) 105 AVOL, DC VOLTAGE GAIN (dB) VCC = +15 V VEE = −15 V RL = 2.0 kW 110 RL = 2.0 kW TA = 25°C 100 100 90 95 90 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 80 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 Figure 5. DC Voltage Gain versus Temperature Figure 6. DC Voltage Gain versus Supply Voltage AVOL, OPEN LOOP VOLTAGE GAIN (dB) 100 45 80 60 40 20 0 1.0 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M VCC = +15 V VEE = −15 V RL = 2.0 kW TA = 25°C Phase 90 GBW, GAIN BANDWIDTH PRODUCT (MHz) 120 0 ∅ , EXCESS PHASE (DEGREES) 20 15 10 VCC = +15 V VEE = −15 V f = 100 kHz Gain 135 5.0 180 10 M 0 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 7. Open Loop Voltage Gain and Phase versus Frequency Figure 8. Gain Bandwidth Product versus Temperature http://onsemi.com 3 LM833 GBW, GAIN BANDWIDTH PRODUCT (MHz) 30 f = 100 kHz TA = 25°C 20 10 SR, SLEW RATE (V/ μ s) 8.0 Falling Rising 6.0 VCC = +15 V VEE = −15 V RL = 2.0 kW AV = +1.0 −25 − + 10 4.0 Vin VO RL 0 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 2.0 −55 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 9. Gain Bandwidth Product versus Supply Voltage Figure 10. Slew Rate versus Temperature 10 8.0 6.0 4.0 2.0 0 5.0 SR, SLEW RATE (V/ μ s) Falling Rising VO , OUTPUT VOLTAGE (Vpp ) RL = 2.0k W AV = +1.0 TA = 25°C 35 30 25 20 15 10 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 0 10 100 1.0 k 10 k 1.0 M f, FREQUENCY (Hz) 10 M 100 k VCC = +15 V VEE = −15 V RL = 2.0 kW THD v 1.0% TA = 25°C + − Vin VO RL Figure 11. Slew Rate versus Supply Voltage Figure 12. Output Voltage versus Frequency VO, OUTPUT VOLTAGE (Vpp ) 15 10 5.0 0 RL = 10 kW TA = 25°C VO + V sat , OUTPUT SATURATION VOLTAGE |V| 20 15 +Vsat 14 −Vsat −5.0 −10 −15 −20 5.0 10 15 VCC, |VEE|, SUPPLY VOLTAGE (V) 20 VO − VCC = +15 V VEE = −15 V RL = 10 kW 13 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 Figure 13. Maximum Output Voltage versus Supply Voltage Figure 14. Output Saturation Voltage versus Temperature http://onsemi.com 4 LM833 PSR, POWER SUPPLY REJECTION (dB) VCC = +15 V VEE = −15 V TA = 25°C DVCC ADM − CMR, COMMON MODE REJECTION (dB) 140 120 100 80 60 40 20 0 100 +PSR = 20 Log −PSR = 20 Log 1.0 k −PSR 160 140 120 100 80 60 40 20 100 DVCM − + D VO DVEE + ADM DV O DVCM × ADM DV 0 CMR = 20 Log +PSR ( DVCC ) V ( DDO/ADM ) VEE 10 k 100 k f, FREQUENCY (Hz) 1.0 M 10 M DVO/ADM VCC = +15 V VEE = −15 V VCM = 0 V DVCM = ±1.5 V TA = 25°C 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M 10 M Figure 15. Power Supply Rejection versus Frequency Figure 16. Common Mode Rejection versus Frequency THD, TOTAL HARMONIC DISTORTION (%) 1.0 − 10 VO RL + 0.1 VCC = +15 V VEE = −15 V RL = 2.0 kW TA = 25°C e n, INPUT NOISE VOLTAGE (nV/√ Hz ) 5.0 0.01 VO = 1.0 Vrms 2.0 VCC = +15 V VEE = −15 V RS = 100 W TA = 25°C 0.001 10 VO = 3.0 Vrms 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 1.0 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k Figure 17. Total Harmonic Distortion versus Frequency Figure 18. Input Referred Noise Voltage versus Frequency i n , INPUT NOISE CURRENT (pA/√ Hz ) 2.0 e n, INPUT NOISE VOLTAGE (nV/√ Hz ) VCC = +15 V VEE = −15 V TA = 25°C 100 1.0 0.7 0.5 0.4 0.3 0.2 10 VCC = +15 V VEE = −15 V Vn(total) = (inRS)2 +en2 + TA = 25°C 4KTRS 10 100 1.0 k f, FREQUENCY (Hz) 10 k 100 k 1.0 1.0 10 100 1.0 k 10 k 100 k 1.0 M RS, SOURCE RESISTANCE (W) Figure 19. Input Referred Noise Current versus Frequency Figure 20. Input Referred Noise Voltage versus Source Resistance http://onsemi.com 5 LM833 VO , OUTPUT VOLTAGE (5.0 V/DIV) VO , OUTPUT VOLTAGE (5.0 V/DIV) VCC = +15 V VEE = −15 V RL = 2.0 kW CL = 0 pF AV = −1.0 TA = 25°C VCC = +15 V VEE = −15 V RL = 2.0 kW CL = 0 pF AV = +1.0 TA = 25°C t, TIME (2.0 ms/DIV) t, TIME (2.0 ms/DIV) Figure 21. Inverting Amplifier Figure 22. Noninverting Amplifier Slew Rate VO , OUTPUT VOLTAGE (10 mV/DIV) VCC = +15 V VEE = −15 V RL = 2.0 kW CL = 0 pF AV = +1.0 TA = 25°C t, TIME (200 ns/DIV) Figure 23. Noninverting Amplifier Overshoot ORDERING INFORMATION Device LM833N LM833NG LM833D LM833DG LM833DR2 LM833DR2G Package PDIP−8 PDIP−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) SOIC−8 SOIC−8 (Pb−Free) 2500 / Tape & Reel 98 Units / Rail 50 Units / Rail Shipping † †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 LM833 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AG NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 −X− A 8 5 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 LM833 PACKAGE DIMENSIONS PDIP−8 N SUFFIX CASE 626−05 ISSUE L 8 5 −B− 1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC −−− 10 _ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC −−− 10_ 0.030 0.040 F NOTE 2 −A− L C −T− SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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