LV8968BBUW
Multi-purpose BLDC
Gate-driver for Automotive
Overview
The LV8968BB is a 3−phase BLDC/PMSM pre−driver with
integrated phase voltage sensing and logic level FET compatibility.
The wide operating voltage range and AEC−Q100 qualification make
this device ideal for automotive applications. Six gate drivers provide
400 mA (typ) gate current to external power bridges allowing use of
low resistance power FETs as well as logic level FETs. All FETs are
protected against over−current, short−circuit, over−temperature and
gate under−voltage. A multitude of protection and monitoring features
make this device suitable for ISO26262 applications. Three
independent low−side source pins allow multiple shunt measurement.
The device also includes a programmable linear regulator, a fast
current−sense amplifier and a window watchdog for microcontroller
support. The SPI interface allows for real time parameter setup and
diagnostics. Critical system parameters can be programmed into
non−volatile OTP memory.
Junction temperature tolerance up to 175°C and control via wide
level WAKE and PWM signals make the LV8968BB an ideal motor
pre−driver for automotive applications such as engine cooling fans,
fuel, oil, and hydraulic pumps.
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MARKING
DIAGRAM
SPQFP48
CASE 131AN
MP
WL
Y
WW
ORDERING INFORMATION
Device
Features
• Full Drive Power from 8 V to 28 V Supply Voltage with Transient
•
•
•
•
•
•
•
•
•
•
•
Tolerance from 4.5 V to 40 V
Extended Voltage Range from 6 V to 33 V Using Logic−level Mode
Up to 30 kHz Motor PWM with Individual Six Gate Control or
Drive−3 Mode with Integrated Programmable Dead−Time
5 V / 3.3 V Linear Regulator for External Loads up to 50 mA
Extensive System Protection Features Including:
♦ Drain−Source Short Detection for External FET
♦ Over−current Shutoff
♦ Low Gate Voltage Warning
♦ Over−temperature Warning and Shutoff
♦ Over / Under−voltage Protection
SPI Interface for Parameter Setup and Diagnostic Access, Dynamic
Access to Dead−Time, Amplifier Gain, and Short Circuit Levels
Non−Volatile (OTP) Memory for Storing Critical System Parameters
Wide Voltage Enable Line and PWM Interface
Integrated Window Watchdog Timer Function
AEC−Q100 Qualified and PPAP Capable
Thermally Efficient Exposed Die 48 Pin SQFP Package for Transient
Operation Up to 175°C
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2018
March, 2019 − Rev. 3
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
LV8968BBUWR2G
Package
Shipping†
SPQFP48K
(Pb−Free /
Halogen Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SAFETY DESIGN ASILB
ASILB Product developed in compliance with
ISO26262 for which a complete safety package is
available.
Typical Applications
• Automotive Fuel, Oil, Water or Hydraulic
•
•
•
•
Pumps
Automotive Actuators
Automotive HVAC and Cooling Fans
Battery Operated Hand Power Tools
White Goods
Publication Order Number:
LV8968BBUW/D
LV8968BBUW
INTERNAL EQUIVALENT BLOCK DIAGRAM AND APPLICATION CIRCUIT
BAT
Opt.
Reverse Polarity
Protection
Opt. Charge
Pump
KEY
PWM
V3RO V3RI
WAKE VS
VGIN VG
PWMIN
RX D
BS 1
BS 2
BS 3
VCC
VDH
EN
GH1
Microcontroller
VMCRES
DIAG
CSB
SCLK
SI
GH2
LV8968BB
GH3
SH 1
SO
AOUT
IH1
IL1
IH2
IL2
IH3
IL3
SH 2
SH 3
GL1
GL2
GL3
SL [1:3]
ISP
AGND
ISO
ISN
GND
Figure 1. Typical Application Diagram
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2
3
LV8968BBUW
SH3
GL3
GH3
BS3
SL2
SH2
GL2
GH2
BS2
SL1
GL1
SH1
PIN ASSIGNMENT
36
25
24
GH1
SL 3
BS1
NC
VDH
ISP
VG
ISN
NC
ISO
LV8968BB
SQFP48K (7 × 7)
7 mm × 7 mm
VGIN
VS
AOUT
AGND
WAKE
NC
NC
SO
EN
SI
V3RO
V3RI
SCLK
48
13
NC
PWMIN
RXD
DIAG
VMCRES
IL3
IH3
IL2
IH2
IL1
IH1
12
VCC
1
CSB
Figure 2. LV8968BB Pinout
Table 1. PIN ASSIGNMENTS & DESCRIPTION
Name
No.
VCC
1
5 V or 3.3 V linear regulator output. (Selected by SPI register setting) Can provide up to 50 mA.
IH1
2
Active high, digital control input to activate GH1.
IL1
3
Active low, digital control input to activate GL1.
IH2
4
Active high, digital control input to activate GH2.
IL2
5
Active low, digital control input to activate GL2.
IH3
6
Active high, digital control input to activate GH3.
Description
IL3
7
Active low, digital control input to activate GL3.
VMCRES
8
Open drain reset output for the microcontroller. Goes low for VCC under−voltage fault, optionally for
watchdog reset and thermal shutdown.
DIAG
9
Open drain error or diagnostic output to be connected to microcontroller interrupt line. DIAG
functionality is defined by internal register settings.
RXD
10
Open drain PWM data output to microcontroller.
NC
11
No connection.
PWMIN
12
Input for battery level control signal. The digital level of PWMIN appears on RXD.
CSB
13
High voltage level translator. Digital level is active low, digital SPI interface chip selection pin.
SCLK
14
SPI interface clock input pin. SI data is latched during the rising edge.
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LV8968BBUW
Table 1. PIN ASSIGNMENTS & DESCRIPTION (continued)
Name
No.
Description
SI
15
SPI interface serial data input pin.
SO
16
SPI interface serial data output pin. High level is pulled to VCC.
NC
17
No connection.
AGND
18
Ground pin.
AOUT
19
Output for various internal analog signals. Actual signal is selected via SPI register. Scaled to 2 V
full scale range.
ISO
20
Output pin for current sense amplifier. Connect to AD converter input of the microcontroller for
current sensing. Gain, reference, and over−current threshold is programmable via SPI register.
Full scale range = 2 V.
ISN
21
Current sense amp minus input pin. Connect this pin to the GND side of the shunt resistor with
Kelvin leads.
ISP
22
Current sense amp plus input pin. Connect this through to top side of shunt resistor with Kelvin
leads.
NC
23
No connection.
SL3
24
Low side source connection of the power stage. Return path for gate current of GL3.
Connect to source of FET controlled by IL3 or to common source of the power stage.
GL3
25
Gate driver output for low side FETs. Switches voltage level between VG and SL3.
Use at least 10 W gate resistors to protect against current spikes.
SH3
26
Connection for the motor phase terminal controlled by GH3 and GL3. Return path for high−side
drivers and input for back EMF sensing.
GH3
27
Gate driver output for high side FETs. Switches voltage level between BS3 and SH3.
Use at least 10 W gate resistors to protect against current spikes.
BS3
28
Supply pin for high side driver GH3. Needs a bootstrap capacitor to SH3 and a diode in reverse
connection to VG.
SL2
29
Low side source connection of the power stage. Return path for gate current of GL2.
Connect to source of FET controlled by IL2 or to common source of the power stage.
GL2
30
Gate driver output for low side FETs. Switches voltage level between VG and SL2.
Use at least 10 W gate resistors to protect against current spikes.
SH2
31
Connection for the motor phase terminal controlled by GH2 and GL2.
Return path for high−side drivers and input for back EMF sensing.
GH2
32
Gate driver output for high side FETs. Switches voltage level between BS2 and SH2.
Use at least 10 W gate resistors to protect against current spikes.
BS2
33
Supply pin for high side driver GH2. Needs a bootstrap capacitor to SH2 and a diode in reverse
connection to VG.
SL1
34
Low side source connection of the power stage. Return path for gate current of GL1.
Connect to source of FET controlled by IL1 or to common source of the power stage.
GL1
35
Gate driver output for low side FETs. Switches voltage level between VG and SL1.
Use at least 10 W gate resistors to protect against current spikes.
SH1
36
Connection for the motor phase terminal controlled by GH1 and GL1.
Return path for high−side drivers and input for back EMF sensing.
GH1
37
Gate driver output for high side FETs. Switches voltage level between BS1 and SH1.
Use at least 10 W gate resistors to protect against current spikes.
BS1
38
Supply pin for high side driver GH1. Needs a bootstrap capacitor to SH1 and a diode in reverse
connection to VG.
VDH
39
Sense input for supply voltage and short circuit detection of high side power FETs.
Connect through 100 W resistor to common drain of the power bridge.
VG
40
Power supply pin for low−side gate drive GL[1−3] directly and GH[1−3] through bootstrap circuit.
Connect decoupling capacitor between VG and GND.
NC
41
No Connection.
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LV8968BBUW
Table 1. PIN ASSIGNMENTS & DESCRIPTION (continued)
Name
No.
Description
VGIN
42
Gate supply input. Normally shorted to VS. Insert a charge pump circuit between VS and VGIN if
low voltage operation is required.
VS
43
Power supply pin.
WAKE
44
WAKE up pin for internal power supply. “H” => Operating mode, “L” or “Open” => Sleep mode.
NC
45
No connection.
EN
46
Active high digital input. A high on EN will activate the outputs. EN can be used as a hold input to
allow an external microcontroller to keep the IC operating even if WAKE is low.
A falling edge on EN clears the error flags.
V3RO
47
Internal regulator output pin. Connect capacitor between this pin and GND.
V3RI
48
Internal regulator feedback pin (Control circuit and Logic power supply).
Connect to V3RO pin. Do not load beyond 1 mA.
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LV8968BBUW
PIN FUNCTIONALITY
VS
VS
VS
V3RO
V3RI
VCC
TYPE1: V3RI
TYPE2: V3RO, VCC
VS
VS
VMCRES
DIAG
RXD
IH1
IH2
IH3
SCLK
SI
100 kW
TYPE3: IH1, IH2, IH3, SCLK, SI, EN
BS
VCC
GH[1−3]
30 kW
IL1
IL2
IL3
SH[1−3]
240 kW
TYPE4: VMCRES, DIAG, RXD
TYPE5: IL1, IL2, IL3, CSB
TYPE6: BS[1−3], GH[1−3], SH[1−3]
VG
V3RI
V3RI
AOUT
ISO
GL[1−3]
ISP
ISN
SL[1−3]
TYPE7: GL[1−3], SL[1−3]
TYPE8: AOUT, ISO
TYPE9: ISP, ISN
VS
VS
VS
SO
PWMIN
TYPE10: SO
100 kW
WAKE
TYPE11: WAKE
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TYPE12: PWMIN
LV8968BBUW
PIN FUNCTIONALITY (continued)
VGIN
VG
VDH
TYPE13: VDH
TYPE14: VGIN, VG
Figure 3. Pin Functionality
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Pins
Ratings
Unit
Supply Voltage
VS, VDH, VGIN
−0.3 to 40
V
Gate Voltage to GND
VG
−0.3 to 40
V
Bootstrap to GND
BS[1−3]
−0.3 to 40
V
Bootstrap to SH[1−3]
BS[1−3]
−0.3 to 40
V
Logic Power Supply
V3RI, V3RO
−0.3 to 3.6
V
5 V Regulator Voltage
VCC
−0.3 to 5.5
V
VS Level Signal Voltage
WAKE, PWMIN
−0.3 to 40
V
Digital Inputs
CSB, EN, SCLK, SI, IH[1−3], IL[1−3]
−0.3 to 40
V
Open Drain Voltage
VMCRES, RXD, DIAG
−0.3 to 40
V
Digital Output Voltage
SO
−0.3 to VVCC+0.3
V
Current Sense Input
ISP, ISN
−3 to VV3RI+0.3
V
Analog Output
ISO, AOUT
−0.3 to VV3RO+0.3
V
High−side Output to GND
GH[1−3]
−3 to 40
V
Motor Phase
SH[1−3]
−3 to 40
V
Low−side Output to GND
GL[1−3]
−3 to 40
V
Low−side Source Pin to GND
SL[1−3]]
−3 to 40
V
Voltage between HS Gate and Phase
GH[n] to SH[n] for n = {1,2,3}
−0.3 to 20
V
Allowable Power SQFP48K
at 70°C
2430
mW
Thermal Resistance
(JESD51−7)
JA = Junction Ambient
33
°C/W
JC = Junction Case
2
°C/W
Storage Temperature
−55 to 150
°C
Junction Temperature
−40 to 150
°C
150 to 175
°C
ESD Human Body Model
(Note 1)
AEC Q100_002
2
kV
ESD Charge Device Model
AEC Q100_011
750
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Operation outside the Operating Junction temperature is not guaranteed. Operation above 150°C should not be considered without a written
agreement from ON Semiconductor Engineering staff.
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LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
12
INTERNAL REGULATOR
VS supply voltage range
VS supply current
WAKE input voltage
VSNO
Normal mode (Note 2)
8
28
V
VSLO
Logic level mode
6
33
V
4.5
40
V
11
16
mA
25
50
mA
1.3
V
VSLOF
Full logic functionality, driver stage
off. (t < 400 ms) (Note 3)
ISTBY
Standby mode
VS & VGIN shorted
VS = 6 V～25 V
ISLEEP
Sleep mode at 25°C
VS & VGIN shorted
7
VTHWKL
Low level
0
VTHWKH
High level
2.7
WAKE pulldown resistor
RPDWK
50
PWMIN switching levels
VTHPIL
Low level
0
VTHPIH
High level
0.6 × VS
PWMIN pulldown resistor
RPDPI
50
PWMIN frequency range
FPWMIN
0
V3RO
3.135
100
VS
V
200
kW
0.4 × VS
V
VS
V
200
kW
30
kHz
3.3
3.465
V
100
INTERNAL REGULATOR
V3RO output voltage
VCC CONSTANT VOLTAGE OUTPUT
Output voltage 5V
VC5RO
REGSEL = 1, No load
4.9
5.0
5.1
V
Output voltage 3.3V
VC3RO
REGSEL = 0, No load
3.23
3.3
3.37
V
VC3RL
VS = 4.5 V, IVCC = −50 mA
3.0
Voltage regulation
VCCVR
Load regulation
VCCLR
Output current limit
V
Io = −5 mA to −50 mA
VCCILIM
50
50
mV
80
mV
180
mA
GATE DRIVERS
Low−side Rdson to SL[1−3]
RONLSSK
“L” level Io = 10 mA
6
15
W
Low−side Rdson to SH[1−3]
RONLSSC
“H” level Io = −10 mA
12
22
W
High−side Rdson to SH[1−3]
RONHSSK
“L” level Io = 10 mA
6
15
W
High−side Rdson to BS[1−3]
RONHSSC “H” level Io = −10 mA
22
W
Propagation delay ON
PDON
50% IHx to 20% GHx.
Cload = 0 nF
12
120
nS
Propagation delay OFF
PDOFF
50% IHx to 80% GHx.
Cload = 0 nF
120
nS
Propagation delay ON
Difference
GH[1−3],GL[1−3]
DPDON
a.3 phase difference of GH1, GH2
and GH3
b.3 phase difference of GL1, GL2
and GL3
−20
20
nS
Propagation delay OFF
Difference
GH[1−3],GL[1−3]
DPDOFF
a.3 phase difference of GH1, GH2
and GH3
b.3 phase difference of GL1, GL2
and GL3
−20
20
nS
800
mA
BS VOLTAGE
BS internal current
IBSC
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LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
GATE VOLTAGE OUTPUT (VG)
VG output voltage
VG current limit
VGNO
Normal mode, IVG < 40 mA
7.0
11.0
12.0
V
VGLO
Logic level mode
5
6
7
V
VGOL
VS = 6 V, IVG < 30 mA
5
180
mA
VGILIM
40
BEMF DETECTION
BEMF divider ratio
BEMFDR
BEMF divider mismatch
BEMFDM
BEMF divider settling time
(20% − 80% FSR)
BEMFST
0.5
VDH divider ratio
VDHDR
1/32
VDH divider settling time
(20% − 80% FSR)
VDHST
0.5
Thermal voltage
VTMPH
Thermal slope
VTEMPSL
AOUT full scale range
AOFLSCR
AOUT output resistance
RONAO
AOUT output current
1/16
−2
2
%
2
ms
2
ms
Tj = 155° (Note 4)
705
mV
(Note 4)
−1.9
mV/°C
IAOUT = ±100 mA
IAO
−100
2.1
V
200
W
100
mA
CURRENT SENSING (ISP, ISN, ISO)
ISP, ISN input current
IISP/N
50
mA
Reference voltage ISO
VRCSA0
OCVR = 0, GAIN = 30,
ISP = ISN = 0.2 V
1.425
1.5
1.575
V
VRCSA1
OCVR = 1, GAIN = 30,
ISP = ISN = 0.2 V
0.125
0.2
0.275
V
CSAG00
OCGAIN = 00
6.53
7.5
8.63
CSAG01
OCGAIN = 01 (Note 4)
15
CSAG10
OCGAIN = 10 (Note 4)
22.5
CSAG11
OCGAIN = 11
Gain
−0.2 V ≦ VISP, VISN ≦ 2 V
−50
26
30
1
34.3
Common mode range
CSACMR
−0.2
2
V
ISN, ISP differential voltage
DVCSAIN
−200
200
mV
ISO full scale range
CSAFLSC
R
0.1
2.9
V
Amplifier settling time
(20% − 80% FSR)
CSAOST
Gain = 7.5, 0.25 V < VISO < 3 V
5400
ns
ISO output resistance
RCSAO
IISO = ±100 mA
200
W
ISO output current
ICSAO
100
mA
Over−current voltage level
VISP−VISN
−100
VTHCSA00 OCDL = 00
180
200
220
mV
VTHCSA01 OCDL = 01
130
150
170
mV
VTHCSA1X OCDL = 10,11
80
100
120
mV
ACTIVE HIGH DIGITAL INPUTS (EN, SCLK, SI, IH[1−3])
High−level input voltage
VTAHH
Low−level input voltage
VTAHL
Pull−down resistance
RPDAH
0.8 × V3RO
50
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V
100
0.2 × V3RO
V
200
kW
LV8968BBUW
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(Valid at a junction temperature range from −40°C to 150°C, for supply Voltage 8.0 V ≤ VS ≤ 25 V unless otherwise specified.
Typical values at 25°C and VS = 12 V unless specified otherwise)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ACTIVE LOW DIGITAL INPUTS (CSB, IL[1−3])
High−level input voltage
VTALH
Low−level input voltage
VTALL
Pull−up resistance to VCC
RPDAL
V
0.8 × V3RO
15
30
0.2 × V3RO
V
60
kW
DIGITAL OUTPUTS (SO)
Output voltage
VSOH
Io = −1 mA
VSOL
Io = 1 mA
VVCC −0.2
V
0.2
V
OPEN DRAIN OUTPUTS (VMCRES, DIAG, RXD)
Output voltage
VODL
Io = 1 mA
0.2
V
Pin leakage current
ILKOD
Vo = 5.5 V
10
mA
TWT0
TSTS = 0
125
150
WARNING AND PROTECTION
Thermal warning (Note 4)
(Junction temperature)
°C
TWT1
TSTS = 1
HYSTW
Hysteresis
TSDT0
TSTS = 0
150
°C
TSDT1
TSTS = 1
175
°C
HYSTSD
Hysteresis
VSOVTH
Over−voltage
16
17
18
V
VSUVTH
Under−voltage
7
7.5
8
V
VDH voltage warning
VDHOVTH
Over−voltage
25
26.5
28
V
VG under−voltage
VGNUVTH
Normal mode
5
6
7
V
VGLUVTH
Logic level mode
3.5
4
4.5
V
VC3UVTH
REGSEL = 0
2.3
2.7
V
VC5UVTH
REGSEL = 1
3.8
4.2
V
2.7
V
Thermal shutdown (Note 4)
(Junction temperature)
VS voltage warning
VCC under−voltage
V3R Power on Reset
FET short protection level
°C
25
°C
25
VPOR
°C
FSDL0000
FSDL = 0000
75
100
125
mV
FSDL0010
FSDL = 0010
240
300
360
mV
FSDL0100
FSDL = 0100
400
500
600
mV
FSDL1000
FSDL = 1000
720
900
1080
mV
FSDL1111
FSDL = 1111
1280
1600
1920
mV
WATCHDOG
WDFOW
WDWT[2:0] typical values
3.2
409.6
ms
WD closed window time
WDCW
WDWT[2:0] typical values
0.8
102.4
ms
WD open window time
WDOW
WDWT[2:0] typical values
1.6
204.8
ms
WD reset duration
WDRD
WD first open window
400
ms
SPI INTERFACE
SPI clock frequency
FSPI
4.5
MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. VDH over voltage warning will be issued. See the specification of the VDH over voltage warning threshold voltage VDHOVTH.
3. Valid for limited time duration of 400 ms (Load dump)
4. Not tested in production. Verified during qualification only.
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LV8968BBUW
DETAILED FUNCTIONAL DESCRIPTION
PWMIN
RXD
WAKE
V3RO V3RI
WAKE
V3RO
PWMIN PWM
Interface
RX
LVSD
VCC
VGIN
VS
2
VGIN
VG
VG
Gate Voltage
Regulator
Internal
Regulator
LDO 3.3 V / 5 V
VCC
VS
BS 1
BS 2
BS 3
POR
VDH
BS1
GH1
SH1
EN
VMCRES
System State
Machine
EN
MCRESWindow−Watchdog
DIAG
DIAG
CSB
CSB
SCLK
GL1
GH 1
SL1
GH 2
BS2
Diag Control
GH 3
GH2
Registers
SH2
Gate−Drive
SCLK
SI
SI
SO
SO
AOUT
VDH
OTP
SPI Interface
LV
89031
SH 1
SH 2
AOUT
IH1
IH1
IL1
IL1
IH2
IH2
IL2
IL2
IH3
IH2
IL3
IL2
SH 3
Thermal Monitor
Motor Control
Logic
GL1
Short−Circuit
Monitor
Drive 3
Drive 6
GL2
GL3
Overcurrent
Monitor
SL [1:3]
Digital Circuit
GL2
SL2
BS3
GH3
SH3
GL3
SL3
ISP
ISP
ISO
OP−AMP
LV8968BB
ISN
AGND
ISO
AGND
Figure 4. Block Diagram
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11
ISN
LV8968BBUW
Chip Activation, System States and Shutdown (EN, WAKE)
Once the supply voltage VS rises above 4.5 V(min), the
LV8968BB enters Sleep mode. In Sleep mode system states
are controlled with pin WAKE.
Table 4. OPERATION MODES
Mode
WAKE
EN
V3RO
Logic
VCC
VG
SPI
Drivers
Sleep
L
NA
Disable
Reset
Disable
Disable
Disable
High−Z
Standby
H
L
Enable
Active
Enable
Enable
Enable
Low
Normal
NA
H
Enable
Active
Enable
Enable
Enable
Active
activated to display internal errors. During Standby mode
full SPI access is possible.
Note that if the CPU watchdog was enabled via OTP, a
VMCRES low will be asserted after 410 ms(typ) unless the
watchdog is being triggered properly. See section
“Watchdog”.
A high on EN takes the LV8968BB from Standby to
Normal mode. Normal mode allows motor control and the
IC accepts control inputs via the motor control pins IH[1−3],
IL[1−3]. A low on EN disables the motor stage regardless of
the PWM input and returns the part back to Standby mode.
The IC is shut down by taking WAKE below 1.3 V(min)
if EN is low. If EN is high, a low on WAKE will be ignored
until the microcontroller pulls EN low.
A high level on WAKE > 2.7 V(max) activates the IC from
sleep mode and enables the internal linear regulator at
V3RO. Once the voltage on V3RO as sensed on V3RI has
passed the power on reset (POR) threshold the system
oscillator starts, and after 3.2 ms(typ) releases the internal
digital reset. OTP register contents are loaded into the
system registers defining the power on state of the
LV8968BB and the VCC regulator voltage.
VCC is powering up next, holding the CPU reset line
VMCRES low until VCC passes its under−voltage level.
During the entire wake−up sequence of 1.05 ms(typ) DIAG
is masked for VG under−voltage. After wake−up is
complete, the IC enters Standby mode and DIAG is
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12
LV8968BBUW
WAKE
1 ms (Max)
V3RO , V3RI
Power On Reset
Reset
Active
Reset
Analog &
Driver Standby
Standby
Active
Standby
Download
125 ms
(Max)
OTP Download
VCC Standby
Standby
Execute MRODL Command
Download
125 ms
(Max)
(Protections are masked)
Active
Standby
VCC
1.05 ms (Max)
VCC Under
Voltage Mask
Mask
Active
Mask
VMCRES
VG Standby
Standby
Active
Standby
VG
1.05 ms (Max)
VG Under
Voltage Mask
Mask
Active
Mask
EN
Over−current &
FET Short Mask
Mask
Other Protection
Mask
SMOD[1:0]
Register
Mask
SO Pin = Hi-Z
(Sleep Mode)
Driver Output
OFF
NOTE:
Active
Mask
Active
SMOD[1:0] = 1h
(Start Up Time) × 1
Mask
SMOD[1:0] = 2h
(Standby Mode)
SMOD[1:0] = 3h
(Normal Mode)
If EN = H, driver can drive according to input
Even if EN = H, driver status is not changed to normal mode.
Figure 5. Powerup and Shutdown Timing
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13
SMOD[1:0] = 2h
(Standby Mode)
SO Pin = Hi-Z
(Sleep Mode)
LV8968BBUW
• A linear regulator to provide 5 V or 3.3 V for external
Operating Voltage Range
Normal operation with full functionality is guaranteed
from 8 V to 25 V. The device will operate from 4.5 V to
40 V with limited performance:
•
Shutdown: VS < 4.5 V
The IC will be off. Gate drivers is Hi−Z.
loads such as a microcontroller
The VG regulator for the gate voltages of the inverter
stage
Internal Regulator (V3RO, V3RI)
The internal regulator provides 3.3 V at V3RO and takes
its feedback from V3RI. V3RO and V3RI need to be
connected externally and bypassed to GND for stability.
This regulator may be used for pullup resistors on the open
drain outputs, but the load should not exceeding 1 mA.
Under−voltage: 4.5 V < VS < 6 V
VS under−voltage warning will be flagged. VG
under−voltage warning may be asserted. If VCC is
programmed to provide 3.3 V to the microcontroller, it will
be supplied. If motor operation is required during
Undervoltage, see section below ”Motor Operation during
Under−voltage”.
LDO 3.3 / 5 V (VCC)
VCC becomes active during Standby mode and can be
configured via registers to provide 5 V or 3.3 V. VMCRES
low is asserted if the output voltage drops below the
threshold levels. VCC may power external loads up to
50 mA (max) and must be bypassed to GND with an external
capacitor. The voltage level is programmed in register
VCVSEL with OTP backup.
Low Voltage: 6 V < VS < 8 V
VS under−voltage warning will be flagged. VG
under−voltage warning may be asserted. VCC will provide
power to the microcontroller. The motor can operate but may
be in low gate enhancement mode if standard level FETs are
used. If full enhancement is required, see section below
”Gate Voltage Regulator (VGIN, VG)”
Gate Voltage Regulator (VGIN,VG)
The gate voltage regulator is supplied by VGIN and
regulates to either 11 V (typ) or 6 V (typ) at VG. The voltage
level is programmed in register VGVSEL with OTP backup.
VG provides the drive voltage for the low−side drivers
GL[1−3] directly and for the high side drivers BS[1−3]
through the bootstrap circuitry. The output is current limited
to 40 mA(min). The output at VG should be bypassed with
a capacitor CVG to GND which should be at least 20 times
the maximum gate charge of the power FETs.
Normal: 8 V < VS < 16 V
Normal operation.
High Voltage: Operation 16 V < VS < 25 V
Normal operation. VS over−voltage warning will be
flagged.
Over−voltage: 25 V < VS < 40 V
VDH over−voltage warning will be flagged. The driver
stage can be programmed to let the motor freewheel to
protect the bootstrap circuitry at BS[1−3] from overstress.
This works if the motor is not operating in field weakening.
In case of active braking, or field weakening operation,
the microcontroller will have to react to a VDH
over−voltage warning by either disabling the driver stage or
activating all low side FETs to brake the motor. The
maximum allowable VS level for motor operation is 40 V −
VVGmax = 28 V or 33 V depending on the state of register
VGVSEL. For additional protection add zener diodes to the
bootstrap pins.
Motor Control Inputs
Once the LV8968BB is in standby mode with the supplies
running, a microcontroller can facilitate motor control via
the inputs EN, IL[1−3], IH[1−3]. All are VS compatible.
Additionally, PWMIN a supply level compatible level
shifter can bring a high voltage control such as a PWM
signal or a crash indicator to microcontroller supply level.
PWM Interface (PWMIN, RXD)
The PWM interface translates a VS level signal with a
threshold of 50%(typ) VS to a digital signal appearing at
RXD. This signal can be used for input PWM translation or
for CRASH signal communication from outside the
application to the microcontroller.
Motor Operation during Under−voltage
An under−voltage charge pump is not included into the
LV8968BB to save cost. If under−voltage operation of the
motor is desired either an external charge pump must be
inserted between VS and VGIN, or it is possible to use the
device in logic level mode by setting MRCONF0[1]. In the
latter case logic level FETs must be used for the inverter
stage.
Drive Enable (EN)
Taking EN high enables the output drivers GH[1−3] and
GL[1−3] for control by the microcontroller, taking EN low
disables them by switching all of them to the sources of the
corresponding external FETs. In addition, a high on EN will
override a low on WAKE allowing the microcontroller to
keep the motor running even after the WAKE line has gone
low.
System Power Supplies
Three power supplies are integrated into the LV8968BB,
all are supplied by VS:
• An internal 3.3 V regulator which provides power to
the digital and interface section
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14
LV8968BBUW
Drive 6 Mode
In drive 6 mode, each input independently controls its
corresponding output requiring 6 independent PWM
channels in the microcontroller. A “high” on IH1 will result
in a “high” on GH1. A “high” on IL1 will result in a “low”
on GL1, and so forth. Trying to force a short by driving IH1
high and IL1 low will be ignored by the logic of the
LV8968BB.
Motor Control (IL[1−3] IH[1−3])
The individual motor phases are controlled by inputs
IL[1−3] and IH[1−3]. IH[1−3] are active high, while IL[1−3]
are active low allowing for parallel control with only three
PWM outputs using internal dead time. To control the driver
stage with GH [1−3] and GL[1−3] EN has to be “high”. The
LV8968BB will insert an adjustable dead time during output
transitions to prevent short circuiting the FETs. Two drive
modes exist:
Table 5. DRIVE 6 MODE
Input
IH[1−3]
Output
IL[1−3]
GH[1−3]
GL[1−3]
L
L
L
H
L
H
L
L
H
L
L
L
H
H
H
L
Drive 3 Mode
This mode is suitable for small microcontrollers which do
not have 6 dedicated PWM control lines. IL[1−3] serve as
enable signals for the phase drivers GH[1−3] and GL[1−3]
while IH[1− 3] serve as their PWM inputs. Connect the
microcontroller’s PWM line to IH[1−3] and the phase select
lines to the individual IL inputs 1−3 respectively.
Table 6. DRIVE 3 MODE
Input
Output
IH[1−3]
IL[1−3]
GH[1−3]
GL[1−3]
L
L
L
L
L
H
L
H
H
L
L
L
H
H
H
L
implemented that begins counting after one driver has been
turned off, and blocks the turning−on of the complementary
driver for a programmable time tFDTI from (typ) 200 ns <
tFDTI < 3.2 ms (typ).
Gate Drive
The gate drive circuit of the LV8968BB includes 3
half−bridge drivers which control six external N−Channel
FETs. The high side gate drivers GH[1−3] switch their gate
connection either to corresponding BS[1−3] pin or the
respective phase connection SH[1−3]. The low−side gate
drivers GL[1−3] are switched from VG to the corresponding
source connection SL[1−3]. Both high and low side switches
are hard switching, but saturate around 400 mA (typ) for
pullup/down currents. Slope control has to be implemented
with gate resistors.
Dead−time Counter
The dead−time counter uses a fixed minimum dead−time
which can be programmed into 4bit parameter FDTILIM.
The dead−time is never allowed to fall below that value.
A dynamic dead time register FDTI allows dead time
variation during motor operation. This register is uploaded
at the beginning of every dead time measurement. Flag
FDTIBSY is high when a dead time value has been written
to register FDTI but was not uploaded to the counter, yet.
Two consecutive writes to FDTI before a counter upload are
flagged as an SPI error by setting bit SACF in the SPI status
register GSDAT.
“Through Current Prevention Function”
Current shoot−through protection of the bridge−drivers is
implemented by ignoring inputs at IH[n] and IL[n] that
would result in turning on of both high−and low−side FET
at the same time. In addition a dead−time counter is
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15
LV8968BBUW
SPI write
FDTIBSY
FDTI = 4 H write is ignored by
FDTIBSY = H.
FDTI
0h
2h
6h
FDTI and FDTILIM are compared and
smaller (longer deadtime) one is selected.
FDTILIM
5h
Gx_FDTI_LT
0h
2h
5h
Gx_EDGE
DEADTIME
3.2 us
2.8 us
2.2 us
Figure 6. Dead Time Programming
Short Protection
To protect against FET shorts the drain−source voltage of
the active external power FETs is monitored. The drain
source voltage of the high side FETs is monitored between
VDH and the corresponding source SH[1−3]. While the low
side FETs are monitored between SH[1−3] and SL[1−3].
After activation of the FET the short detection is masked for
time tFSFT to allow for signal settling. If after the masking
time tFSFT the FET voltage exceeding VFSDL continues for
tFSDT, a FET short error is flagged. For details see “System
Errors and Warnings” on page 18.
4 bit register FSDL selects the short−circuit shutoff
voltage between 1.6 V > VFSLD > 100 mV(typ). The
masking time can be between 0.8 ms < tFSF < 3.2 ms(typ) as
defined by register FSFT, and the debounce time is between
3.2 ms < tFSDT < 12.8 ms(typ) as selected by FSDT. These
registers are dynamic and FSDL can be changed during
motor operation, though FSFT and FSDT can be changed at
EN = L.
operation. The offset is determined by CSOFEN relative to
an internal reference which can be either 200 mV(typ) for
single ended sensing, or 1.5 V(typ) for sensing current in
both directions. The output of the current sense amplifier
appears on ISO with a full scale range of 3 V.
Current Sensing and Over−current Shutoff
Single shunt current sensing can be implemented with the
integrated high speed sense amplifier. It amplifies the
voltage across ISP – ISN with a programmable gain defined
by register CSGAIN to be 7.5, 15, 22.5 or 30. Access to this
register is dynamic, allowing gain adjustment during motor
Temperature Sensing
The LV8968BB monitors internal junction temperature
Tj. The voltage representing this temperature (VPTAT) can be
sampled at AOUT as described below. Thermal warnings
and errors are issued if TJ exceeds the levels defined by
THTSEL:
Over−current Shutoff
A parallel path implements fast over−current shutoff of
the driver stage. Over−current shutoff is triggered if the
voltage across ISP − ISN exceeds a programmable level of
100, 150 or 200 mV(typ) − as defined by register OCDL. In
over−current shutoff all gate drivers go to Hi−Z, turning the
power FETs high−impedance and letting the motor
freewheel – this reaction is maskable. For more information
on masking and recovery see section “System Errors and
Warnings” on page 18.
To suppress switching transients from causing an
over−current masking time 0.2 ms < tOCMASK < 3.2 ms can
be programmed into register OCMASK.
Table 7. THERMAL THRESHOLDS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
THTSEL
Thermal Warning
Thermal Shutoff
0
125°C
150°C
1
150°C
175°C
If thermal error shutoff is activated, VG and VCC turn off,
and the driver stage goes high impedance. As a result
VMCRES goes low and SPI communication is disabled as
well. The exact failure modes and masks are described in
section “System Errors and Warnings”.
Back EMF and other Measurements
The LV8968BB includes a multiplexer for measuring the
phase voltages, the motor voltage and the IC temperature.
Depending on the state of AOUTSEL the following voltages
appear on AOUT:
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LV8968BBUW
Table 8. AOUT SELECTION
MRAOSEL[2:0]
Pin
Formula
0
VDH
VVDH = 32 VAOUT
Motor Supply Voltage
Comment
1
SH1
VSH1 = 16 VAOUT
Phase Voltage 1
2
SH2
VSH2 = 16 VAOUT
Phase Voltage 2
3
SH3
VSH2 = 16 VAOUT
Phase Voltage 3
4, 5
−
TJ = (VAOUT − 995.7 mV) / 2 mV °C
6, 7
−
High Impendance
Internal junction temperature
during closed window time or the watchdog time expires.
Watchdog error effects can be customized. For detailed error
behavior a masking see section “System Errors and
Warnings”.
After a watchdog induced microcontroller reset, the error
register contents of registers MRDIAG[0] remain conserved
until an SPI read access. This helps the microcontroller
identify the fault condition.
Watchdog
The LV8968BB includes a window watchdog to monitor
the microcontroller. The size of the watchdog window is
defined by register WDTWT. For detailed timing
information see Figure 7: Window Watchdog Timing.
A write access to register MRRST during open window time
resets the watchdog timer and it starts counting again. The
watchdog will issue an error whenever MRRST is written to
WAKE
MCRES
Twt
Tcw
Tcw
Tfow
WDT
Status
First Open
Window
Standby
Twt
Closed
Open
Window
Window
Reset by
MRRST= 00h command
Closed
Window
Open
Window
DIAG
WAKE
MCRES
Tmr
Tcw
Tcw
Twt (Not reset)
WDT
Status
Open
Window
Closed
Window
Tfow
Open
Window
First Open
Window
Closed
Window
Reset
microcontroller
DIAG
Read MRDIAG0
DIAGS ,
WDTPO
Register
WAKE
VMCRES
Tmr
Tcw
Tcw
Tcw
Tfow
Twt
WDT
Status
Closed
Window
Open
Window
Closed
Window
Reset timing
is too first
DIAG
First Open
Window
Reset
microcontroller
Read MRDIAG0
DIAGS ,
WDTPO
Register
Figure 7. Window Watchdog Timing
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17
Closed
Window
LV8968BBUW
Table 9. WINDOW WATCHDOG TIMING OPTIONS (TJ = −40 to 150 °C, VS = 4.5 to 40 V)
Symbol
TFOW
TCW
TWT
TMR
Min
Typ
Max
Unit
WDT first open window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
WDTWT[2:0] = 7h
Characteristic
390.0
195.0
:
3.0
409.6
204.8
: (1/2 step)
3.2
431.2
215.6
:
3.4
ms
WDT closed window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
WDTWT[2:0] = 7h
97.4
48.7
:
0.7
102.4
51.2
:(1/2 step)
0.8
107.8
53.9
:
0.9
ms
WDT window time
WDTWT[2:0] = 0h
WDTWT[2:0] = 1h
: (1/2 step)
WDTWT[2:0] = 7h
195.0
97.4
:
1.4
204.8
102.4
:(1/2 step)
1.6
215.6
107.8
:
1.7
ms
333
400
422
ms
WDT microcontroller reset time
System Errors and Warnings
case the LV8968BB will keep the output stage disabled until
the latch is cleared by one of the following actions:
• Power on reset
• EN low
• SPI write of FFh to MRRST
Table 10 explains the error behaviour. ”Error” names the
type of error that is covered. ”Reaction Settings Option”
lists which options exists for this error and the
corresponding register. ”Reaction names what happens if
the error occurs. Some reactions depend on the ”Setting
Options” and are described in Notes below.
System errors and warnings are always flagged in their
corresponding register MRDIAG0 and MRDIAG1 and their
presence is indicated in SPI status register GSDAT. The
LV8968BB gives great flexibility in modifying the error
response. Error response definition can be backed up into
OTP.
All system errors and warnings can cause a transition on
DIAG. The polarity of this transition is selected in bit
DIAGPOL. DIAG should be connected to an interrupt input
of the microcontroller. Errors that can cause serious damage
such as short−circuit and over−current may be latched by
enabling the corresponding latch bit in MRCONF7. In this
Table 10. SYSTEM ERROR AND WARNING RESPONSE MATRIX
Reaction Setting Options
Reaction
Setup
Register
Mask
Error
Report on
DIAG
Auto
Recover
Latch
Off
VG
DRV
VCC
MC
RES
VS
Under
Voltage
VSUVPS
[1:0]
Yes
Yes
Yes
No
ON
(Note 5)
ON
H
VS voltage
recovers
After OTP
download
VS Over
Voltage
VSOVPS
[1:0]
Yes
Yes
Yes
No
ON
(Note 5)
ON
H
VS voltage
recovers
After OTP
download
VDH
Over
Voltage
VDOVPS
[1:0]
Yes
Yes
Yes
No
ON
(Note 5)
ON
H
VDH voltage
recovers
After OTP
download
VG
Under
Voltage
VGUVPS
[1:0]
Yes
Yes
Yes
No
ON
(Note 5)
ON
H
VG voltage
recovers
After VG
start−up
time
VCC
Under
Voltage
−
No
No
Yes
No
ON
OFF
ON
L
VCC voltage
recovers
After VCC
start−up
time
Error
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18
Recovery
Condition
Protection
Enabled
LV8968BBUW
Table 10. SYSTEM ERROR AND WARNING RESPONSE MATRIX
Reaction Setting Options
5.
6.
7.
8.
Reaction
Error
Setup
Register
Mask
Error
Report on
DIAG
Auto
Recover
Latch
Off
VG
DRV
VCC
MC
RES
Recovery
Condition
Over
Current
OCPS
[1:0]
Yes
Yes
Yes
Yes
ON
(Note 5)
ON
H
[Latch Off]
EN = L or
execute
MRRST = Ffh
command
[Auto Recover]
EN = L or after
ecovery time
[Report]
EN = L or motor
current is down
EN = H
(Normal
mode)
FET
Short
FSPS
[1:0]
Yes
Yes
Yes
Yes
ON
(Note 5)
ON
H
[Latch Off] EN =
L or execute
MRRST = FFh
command
[Auto Recover]
EN = L or after
recovery time
[Report] EN = L
or FET short current is down
EN = H
(Normal
mode)
Thermal
Warning
THWPS
Yes
Yes
No
No
ON
ON
ON
H
Temperature is
down
After OTP
download
Thermal
Shut
Down
THSPS
Yes
No
Yes
No
(Note 6)
(Note 6)
(Note 6)
(Note 7)
Temperature is
down
After OTP
download
Watch
Dog
Timer
WDTPS
Yes
No
Yes
No
ON
(Note 6)
ON
(Note 8)
After output
reset pulse from
VMCRES pin
VMCRES
=H
Protection
Enabled
Report or Ignore = ON, Latch Off or Auto Recover = OFF
Ignore = ON, Auto Recover = OFF
Ignore = H, Auto Recover = L
Ignore = Fixed H, Auto Recover = Output L pulse
SPI Interface
In the LV8968BB the SPI Interface is used to perform
general communications for status reporting, control and
programming.
CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
SI
WEN
ADDR [6:0]
WDAT [7:0]
GSDAT [6:0]
RDAT [7:0]
(previous data)
SO
Hi-Z
Figure 8. SPI Format in Write Mode
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19
Hi-Z
LV8968BBUW
CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
SI
WEN
ADDR [6:0]
WDAT [7:0]
(ignored)
GSDAT [6:0]
RDAT [7:0]
SO
Hi-Z
Hi-Z
Figure 9. SPI Format in Read Mode
• It is important the system master have the clock and
SPI communications with the LV8968BB follows
established industry standard practices including the use of
WEN and start and stop bits as shown above. Data is
transferred MSB first and both clock and data are transferred
as ’true’ data with the higher level indicating a logical 1 or
true state.
There are two items to be especially careful of with the
general communication scheme:
• Communications must be full duplex and simultaneous.
It is not allowed to send one transaction and then read
data on a second transaction as the status register
information will be updated on the first transaction and
then be out of date for the second. Some systems break
transactions into separate read and write operations
which is not acceptable
data polarities and phases as shown above. Both the
clock and data on some systems can be inverted for
various reasons but must arrive at the LV8968BB per
the above drawing. Common errors include SCLK
inversion such that the leading edge arrives as
a downward transition rather than a rising edge,
or having the data to clock phase incorrect. Data phase
must be such that the data only changes during a clock
falling edge and is completely stable during a clock
rising edge. This means a good margin of one half a bit
time exists to eliminate transmission delay hazards.
The first byte returned on all transactions is always the
status register GSDAT, and contains information such as the
busy flag during programming operations
Table 11.
GSDAT[7:0]
Bit 7
6
5
4
3
2
0
ORBEN
SACF
DIAGS
LATCH
OBSY
NA
NA
NA
NA
NA
NA
NA
NA
Sleep mode
NA
NA
NA
NA
NA
NA
0
1
Device start up time
NA
NA
NA
NA
NA
NA
1
0
Standby mode
NA
NA
NA
NA
NA
NA
1
1
Normal mode
NA
0
0
0
0
0
NA
NA
Normal Operation
NA
NA
NA
NA
NA
1
NA
NA
OTP download of default
values
NA
NA
NA
NA
1
NA
NA
NA
Latched shutdown condition
NA
NA
NA
1
NA
NA
NA
NA
Failure Condition
NA
NA
1
NA
NA
NA
NA
NA
Last SPI access failed*
NA
1
NA
NA
NA
NA
NA
NA
OTP integrity test mode
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20
1
Bit 0
SMOD[1:0]
LV8968BBUW
The following SPI failures are detectable and reported
collectively by a high on SACF in GSDAT[5] as general SPI
failures:
♦ Any access to an address which is not assigned.
♦ The number of SCLK edges is not 16 within one
word transfer
♦ Any access to MRCONF and ORCONF while
OBSY = 1, (During write operations)
♦ Write access to MRODL register while OBSY = 1,
(during write operations)
♦ Write access to any of the main registers after
setting MSAENB = 1 (Implies Reg. address 04 h to
07 h are locked)
♦
♦
♦
♦
Write access to any of the OTP registers after
OSAENB = 1 (Implies Reg. address 40 h to 43 h are
locked)
Write access attempt to a read only or locked
register
SI signal changed at positive edge of SCLK
(Incorrect data/sclk phase setup)
Write access to dead−time register FDTI while
FDTIBSY is still high (last value has not been
uploaded)
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21
LV8968BBUW
SPI Timing
90%
CSB
10%
10%
Tcss
SCLK
1/Tfck
10%
Tckn
10%
Tcssod
Tsis
90%
10%
10%
Tckp
Tcsh
90%
90%
10%
90%
90%
Tcsp
Tsih
90% 90%
SI
10% 10%
Tcksod
Tcssoo
SO
Tcssoz
90%
10%
10%
Figure 10. SPI Timing Diagram
Table 12. SPI TIMING (TJ = −40 to 150°C, VS = 4.5 to 40 V, SO load = 50 pF)
Symbol
Comment
Min
Typ
Max
Unit
4.5
MHz
TFCK
SCLK Clock Frequency
TCKP
SCLK High Pulse Width
90
ns
TCKN
SCLK Low Pulse Width
90
ns
TCSS
CSB Setup Time
90
ns
TCSH
CSB Hold Time
0
ns
TCSP
CSB High Pulse Width
90
ns
TSIS
SI Setup Time
45
ns
TSIH
SI Hold Time
45
ns
TCKSOD
SCLK Fall Edge to SO Delay Time
75
ns
TCSSOD
CSB Fall Edge to SO Delay Time
75
ns
TCSSOO
CSB Fall Edge to SO Data Out Time
TCSSOZ
CSB Rise Edge to SO Hi−Z Out Time
0
ns
75
ns
NOTE: SPI−Interface can be used after the data download of the OTP has been completed. However it can not be used during VMCRES = L.
transition). This operation takes up to 125 ms. A high OBSY
flag in the first returned byte during a SPI transaction
indicates this.
OTP Programming
The OTP register data is typically transferred into the
main registers at device startup (From sleep to standby
POR Ready
Download Data
WAKE
OBSY
Figure 11. OTP Data Download Timing at Startup
access (MRCONF0 ~ 3, ORCONF0 ~ 3,
MRODL) until the OBSY flag is cleared.
An OTP download can also actively be initiated by
writing 00h to register MRODL. This command requires
monitoring the OBSY flag. Don’t perform specific register
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22
MRORB,
LV8968BBUW
Write MRODL Register
OBSY
Download Data
Figure 12. OTP Data Download Timing after an MRODL Command
OTP Programming Overall
Figure 13 shows overall of the OTP memory write and
verify flow. It consists of preparation, write and three times
of data integrity verification.
START
Set LV8968BB
standby
Apply VS> 14V
Write Data
Set mode to
L side read check
Verify
Set mode to
H side read check
Verify
Set mode to
Normal
Verify
END
Figure 13. OTP Memory Write and Verify Flow
The OBSY flag will be reset at the end of the write cycle.
OBSY is in GSDAT register. To get GSDAT, SPI accesses
to the register MRACK is recommended. MRACK doesn’t
interfere with the programming operation.
MRCONF0 ~ 3, ORCONF0 ~ 3, MRORB, MRODL
registers cannot be accessed during an OTP write cycle.
OTP Programming
The OTP registers can be programmed in Standby mode
only while the write lock bit OSAENB is set 0. And, the
supply voltage at pin VS must be more than 14 V. The actual
write operation to the OTP memory will be done, when the
state change from 0 to 1 is commanded. Once the bit state is
changed to 1, it cannot be change back to 0. The number of
writing is limited to one per bit.
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23
LV8968BBUW
Write OTP Data
OBSY
Internal Write Time
Figure 14. OTP Programming Timing
The programming takes 4 ms maximum. To simplify
operation, a waiting for 4 ms plus margin can be applicable
instead of a polling of the flag OBSY. (Figure 15)
START
WRITE DATA
Write data to address 40h
Wait for 4 ms or more
Write data to address 41h
Wait for 4 ms or more
Write data to address 42h
Wait for 4 ms or more
Write data to address 43h
Wait for 4 ms or more
END
Figure 15. OTP Memory Write and Verify Flow
3. Verify that the main register contents are
consistent with the programmed OTP data
4. Set OTP readout threshold “high” by setting
ORBEN = 1 and ORBLV = 1 in register MRORB
5. Execute OTP download command by writing 00h
to MRODL
6. Verify that the main register contents are
consistent with the programmed OTP data
7. Return OTP threshold to normal by setting
ORBEN = 0 and ORBLV = 0
8. Execute OTP download command
9. Verify that the main register contents are
consistent with the programmed OTP data
OTP Data Integrity Verification
In order to verify that the OTP programming operation
was successful. It is strongly recommended to do an OTP
margin check: To do this, the OTP registers are downloaded
into the main register bank with minimum and maximum
readout thresholds. This OTP download is forced by writing
00h to register MRODL. The readout threshold is set in
register MRORB.
OTP Margin read check sequence after programmed:
1. Set OTP readout threshold “low” by setting
ORBEN = 1 and ORBLV = 0 in register MRORB
2. Execute OTP download command by writing 00h
to MRODL
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24
LV8968BBUW
Locking OTP Register Contents
MSAENB bit and OSAENB bit are used in order to
prevent write−access of main− and OTP registers
respectively.
CAUTION: Inadvertent writing of these bits will
permanently lock the corresponding register
blocks from any further write access.
Should only be set at end of development
cycles.
Table 13. REGISTER MAP
WENB
WTIM
Always NG
Always NG
OSAENB
(Note 9)
EN=L
ADDR
[6:0]
Data
Name
D[7]
D[6]
−
GSDAT
0
ORBEN
SACF
DIAGS
LATCH
OBSY
00h
MRCONF0
0
0
THTSEL
DFCSEL
DIAGLTO
DIAGPOL
01h
MRCONF1
0
0
0
WDTPS
THSPS
THWPS
02h
MRCONF2
0
0
0
D[5]
D[4]
D[3]
VDOVPS[1:0]
Read Only
03h
MRCONF3
0
MSAENB
(Note 9)
EN=L
04h
MRCONF4
0
05h
MRCONF5
0
0
06h
MRCONF6
0
0
0
07h
MRCONF7
08h
MRCONF8
0
0
0
0
0
10h
MRAOSEL
0
0
0
0
0
0
Always OK
Always OK
EN=L
Read Only
OSAENB
(Note 9)
Read Only
EN=L
0
WDTWT[2:0]
D[0]
SMOD[1:0]
VGVSEL
VCVSEL
VGUVPS[1:0]
VSUVPS[1:0]
0
0
0
CSOFEN
OCDL[1:0]
FSPS[1:0]
D[1]
VSOVPS[1:0]
Read Only
Always OK
0
D[2]
0
OSAENB
AWODLEN
D3MDEN
OCMASK[3:0]
0
FSFT[1:0]
FSDT[1:0]
OCPS[1:0]
FDTILIM[3:0]
0
0
MSAENB
AOUTSEL[2:0] (Default=7h)
11h
MRCSG
0
0
0
0
12h
MRFSDL
0
0
0
0
0
FSDL[3:0]
13h
MRFDTI
0
0
0
0
FDTI[3:0]
14h
MRFDTIF
0
0
0
0
15h
MRRST
16h
MRORB
17h
MRODL
20h
MRDIAG0
0
0
0
WDTPO
21h
MRDIAG1
0
0
0
22h
MRACK
0
1
0
40h
ORCONF0
THTSEL
41h
ORCONF1
42h
ORCONF2
43h
ORCONF3
0
CSGAIN[1:0]
0
0
FDTIBSY
0
ORBEN
ORBLV
THSPO
THWPO
FSPO
OCPO
VCUVPO
VGUVPO
VDOVPO
VSOVPO
VSUVPO
1
0
1
0
1
DFCSEL
DIAGLTO
DIAGPOL
VGVSEL
VCVSEL
WDTPS
THSPS
THWPS
Write 00h: Reset WDT / Write FFh: Reset latch off
0
0
0
0
0
Write 00h: Execute OTP data download
ORCONF0[7:6]
ORCONF1[7:5]
ORCONF2[7:6]
VDOVPS[1:0]
ORCONF3[7:1]
NOTE: SPI access to addresses not listed here will result in an SPI access failure error (SACF).
9. At Test mode, ENB = 1 setting is ignored.
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25
VSOVPS[1:0]
VGUVPS[1:0]
VSUVPS[1:0]
OSAENB
LV8968BBUW
MRCONF0 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
00h
MRCONF0
0
0
THTSEL
DFCSEL
DIAGLTO
DIAGPOL
VGVSEL
VCVSEL
THTSEL
Temperature warning threshold and error selection.
♦ THTSEL = 0: Thermal warning = 125°C, Thermal shut down = 150°C
♦ THTSEL = 1: Thermal warning = 150°C, Thermal shut down = 175°C
DFCSEL
Defines the condition under which the error registers are reset, by error condition removed only, or by error condition
removed and subsequent SPI read access of the register in question.
♦ DFCSEL = 0: If error was cleared, DIAGS flag of GSDAT and MRDIAG0, 1 flag are reset by MRDIAG0, 1 read
♦ DFCSEL = 1: DIAGS flag of GSDAT and MRDIAG0,1 flag are reset by recovery condition
DIAGLTO
If this bit is set, only latched errors result in a transition on DIAG. Otherwise all errors (and warnings) will be flagged.
♦ DIAGLTO = 0: At the time of detecting auto recover or latch off error, DIAG output is on
♦ DIAGLTO = 1: At the time of detecting latch off error, DIAG output is on
DIAGPOL
Decides the polarity of the DIAG output.
♦ DIAGPOL = 0: At the time of detecting diagnostic error, DIAG output is L
♦ DIAGPOL = 1: At the time of detecting diagnostic error, DIAG output is H
VGVSEL
Selects if the IC is in logic level mode or normal mode which modifies the gate voltage of the drive section.
♦ VGVSEL = 0: VG normal mode (VG = 11 V)
♦ VGVSEL = 1: VG logic level mode (VG = 6 V)
VCVSEL
Selects the output voltage of VCC to be either 3.3 V or 5 V. The wrong bit selection has a possibility to damage the
microcontroller. Please make sure the appropriate selection.
♦ VCVSEL = 0: VCC = 3.3 V
♦ VCVSEL = 1: VCC = 5.0 V
MRCONF1 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
01h
MRCONF1
0
0
0
WDTPS
THSPS
THWPS
WDTPS
Watchdog error results in error response or is ignored.
♦ WDTPS = 0: Ignore WDT error
♦ WDTPS = 1: Emergency off and report a WDT error (Auto recover)
THSPS
Thermal shutdown error results in error response or is ignored.
♦ THSPS = 0: Ignore thermal shut down error
♦ THSPS = 1: Emergency off and report at thermal shut down error (Auto recover)
THWPS
♦ THWPS = 0: Ignore thermal warning error
♦ THWPS = 1: Report thermal warning error
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26
D[1]
D[0]
VGUVPS[1:0]
LV8968BBUW
VGUVPS[1:0]
♦ VGUVPS[1:0] = 0h: Ignore VG under voltage error
♦ VGUVPS[1:0] = 1h: Report VG under voltage error
♦ VGUVPS[1:0] = 2h, 3h: Emergency off and report at VG under voltage error (Auto recover)
MRCONF2 (Default: 00h)
(Write Access Only when EN = Low. OTP Backup Possible)
ADDR
Data Name
D[7]
D[6]
02h
MRCONF2
0
0
D[5]
D[4]
VDOVPS[1:0]
D[3]
D[2]
VSOVPS[1:0]
D[1]
D[0]
VSUVPS[1:0]
VDOVPS[1:0]
♦ VDOVPS[1:0] = 0h: Ignore VDH over voltage error
♦ VDOVPS[1:0] = 1h: Report VDH over voltage error
♦ VDOVPS[1:0] = 2h, 3h: Emergency off and report at VDH over voltage error (Auto recover)
VSOVPS[1:0]
♦ VSOVPS[1:0] = 0h: Ignore VS over voltage error
♦ VSOVPS[1:0] = 1h: Report VS over voltage error
♦ VSOVPS[1:0] = 2h, 3h: Emergency off and report at VS over voltage error (Auto recover)
VSUVPS[1:0]
♦ VSUVPS[1:0] = 0h: Ignore VS under voltage error
♦ VSUVPS[1:0] = 1h: Report VS under voltage error
♦ VSUVPS[1:0] = 2h, 3h: Emergency off and report at VS under voltage error (Auto recover)
MRCONF3 (Default: 00h)
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
03h
MRCONF3
0
0
0
0
0
0
0
OSAENB
OSAENB
Setting this bit disables all write access to the configuration registers MRCONF0, MRCONF1 and MRCONF2 and the OTP
backup register. Set to prevent system parameters from being modified.
♦ OSAENB = 0: Enable write access of MRCONF0~2 and ORCONF0~3
♦ OSAENB = 1: Disable write access of MRCONF0~2 and ORCONF0~3
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27
LV8968BBUW
MRCONF4 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
04h
MRCONF4
0
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
CSOFEN
AWODLEN
D3MDEN
WDTWT[2:0]
WDTWT[2:0]
Defines the watchdog timer window sizes.
♦ WDTWT[2:0] = 0h: TFOW = 409.6 ms, TCW = 102.4 ms, TWT = 204.8 ms
♦ WDTWT[2:0]=1h: TFOW = 204.8 ms, TCW = 51.2 ms, TWT = 102.4 ms
:
: (1/2 step)
:
♦ WDTWT[2:0] = 7h: TFOW = 3.2 ms, TCW = 0.8 ms, TWT = 1.6 ms
CSOFEN
Selects the offset of the current sense amplifier.
♦ CSOFEN = 0: Current sense amp offset = 1.5 V
♦ CSOFEN = 1: Current sense amp offset = 0.2 V
AWODLEN
Periodical (200 ms) OTP download during EN = H.
♦ AWODLEN = 0: Not download OTP data in normal mode
♦ AWODLEN = 1: Download OTP data periodically in normal mode
D3MDEN
Chooses how the output drivers are addressed, with six PWM channels, or with three PWM channels and three enables.
♦ D3MDEN = 0: Drive 6 mode
♦ D3MDEN = 1: Drive 3 mode
MRCONF5 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
05h
MRCONF5
0
0
D[5]
D[4]
D[3]
OCDL[1:0]
OCDL[1:0]
Defines the over−current detection threshold voltage between ISN and ISP.
♦ OCDL[1:0] = 0h: Over−current detect level = 200 mV
♦ OCDL[1:0] = 1h: Over−current detect level = 150 mV
♦ OCDL[1:0] = 2h, 3h: Over−current detect level = 100 mV
OCMASK[3:0]
Masking time for the over−current detection after every output transition.
♦ OCMASK[3:0] = 0h: Over−current mask time = 0.2 ms
♦ OCMASK[3:0] = 1h: Over−current mask time = 0.4 ms
:
: (0.2 ms step)
:
♦ OCMASK[3:0] = Eh: Over−current mask time = 3.0 ms
♦ OCMASK[3:0] = Fh: Over−current mask time = 3.2 ms
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28
D[2]
D[1]
OCMASK[3:0]
D[0]
LV8968BBUW
MRCONF6 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
06h
MRCONF6
0
0
0
0
D[3]
D[2]
D[1]
FSFT[1:0]
D[0]
FSDT[1:0]
FSFT[1:0]
External FET short detection debounce time. A short condition hast to remain valid during this time.
♦ FSFT[1:0] = 0h: FET short detect time = 0.8 ms
♦ FSFT[1:0] = 1h: FET short detect time = 1.6 ms
♦ FSFT[1:0] = 2h: FET short detect time = 2.4 ms
♦ FSFT[1:0] = 3h: FET short detect time = 3.2 ms
FSDT[1:0]
External FET short circuit detection masking time, starts after turn−on of the FET.
♦ FSDT[1:0] = 0h: FET short masking time = 3.2 ms
♦ FSDT[1:0] = 1h: FET short masking time = 6.4 ms
♦ FSDT[1:0] = 2h: FET short masking time = 9.6 ms
♦ FSDT[1:0] = 3h: FET short masking time = 12.8 ms
MRCONF7 (Default: 00h)
(Write Access Only when EN = Low)
ADDR
Data Name
07h
MRCONF7
D[7]
D[6]
FSPS[1:0]
D[5]
D[4]
D[3]
OCPS[1:0]
FSPS[1:0]
Short circuit error decision mask.
♦ FSPS[1:0] = 0h: Ignore FET short error
♦ FSPS[1:0] = 1h: Report FET short error
♦ FSPS[1:0] = 2h: Emergency off and report at FET short error (Auto recover)
♦ FSPS[1:0] = 3h: Emergency off and report at FET short error (Latched off)
OCPS[1:0]
Over−current error decision mask.
♦ OCPS[1:0] = 0h: Ignore over−current error
♦ OCPS[1:0] = 1h: Report over−current error
♦ OCPS[1:0] = 2h: Emergency off and report at over−current error (Auto recover)
♦ OCPS[1:0] = 3h: Emergency off and report at over−current error (Latched off)
FDTILIM[3:0]
Minimum Dead time programming register.
♦ FDTILIM[3:0] = 0h: FET dead time = 3.2 ms
♦ FDTILIM[3:0] = 1h: FET dead time = 3.0 ms
:
: (−0.2 ms step)
:
♦ FDTILIM[3:0] = Eh: FET dead time = 0.4 ms
♦ FDTILIM[3:0] = Fh: FET dead time = 0.2 ms
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29
D[2]
D[1]
FDTILIM[3:0]
D[0]
LV8968BBUW
MRCONF8 (Default: 00h)
(Write access only when EN = Low)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
08h
MRCONF8
0
0
0
0
0
0
0
MSAENB
D[1]
D[0]
MSAENB
Setting this bit disables all write access to the configuration registers MRCONF4 to MRCONF7.
♦ MSAENB = 0: Enable write access of MRCONF4 ~ 7
♦ MSAENB = 1: Disable write access of MRCONF4 ~ 7
MRAOSEL (Default: 07h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
10h
MRAOSEL
0
0
0
0
0
D[2]
AOUTSEL[2:0]
AOUTSEL[2:0]
Select the internal nodes brought out on AOUT.
♦ AOUTSEL[2:0] = 0h: AOUT = Output VDH voltage level
♦ AOUTSEL[2:0] = 1h: AOUT = Output SH1 voltage level
♦ AOUTSEL[2:0] = 2h: AOUT = Output SH2 voltage level
♦ AOUTSEL[2:0] = 3h: AOUT = Output SH3 voltage level
♦ AOUTSEL[2:0] = 4h, 5h: AOUT = Output thermal monitor voltage level
♦ AOUTSEL[2:0] = 6h, 7h: AOUT = Hi−Z
MRCSG (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
11h
MRCSG
0
0
0
0
0
0
D[3]
D[2]
D[1]
D[0]
CSGAIN[1:0]
CSGAIN[1:0]
Programs the gain of the current sense amplifier.
♦ CSGAIN[1:0] = 0h: Current sense amp gain = 7.5
♦ CSGAIN[1:0] = 1h: Current sense amp gain = 15
♦ CSGAIN[1:0] = 2h: Current sense amp gain = 22.5
♦ CSGAIN[1:0] = 3h: Current sense amp gain = 30
MRFSDL (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
12h
MRFSDL
0
0
0
0
FSDL[3:0]
Defines the maximum allowable drain source voltage across a power FET.
♦ FSDL[3:0] = 0h: FET short detect level = 100 mV
♦ FSDL[3:0] = 1h: FET short detect level = 200 mV
:
: (100 mV step)
:
♦ FSDL[3:0] = Eh: FET short detect level = 1500 mV
♦ FSDL[3:0] = Fh: FET short detect level = 1600 mV
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30
D[1]
FSDL[3:0]
D[0]
LV8968BBUW
MRFDTI (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
13h
MRFDTI
0
0
0
0
D[3]
D[2]
D[1]
D[0]
FDTI[3:0]
FDTI[3:0]
Dead time programming register. This dead time will be applied unless it is smaller than FDTILIM[3:0] in MRCONF7.
♦ FDTI[3:0] = 0h: FET dead time = 3.2 ms
♦ FDTI[3:0] = 1h: FET dead time = 3.0 ms
:
: (−0.2 ms step)
:
♦ FDTI[3:0] = Eh: FET dead time = 0.4 ms
♦ FDTI[3:0] = Fh: FET dead time = 0.2 ms
MRFDTIF (Default: 00h)
(Full Dynamic Access)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
14h
MRFDTIF
0
0
0
0
0
0
0
FDTIBSY
FDTIBSY
FDTIBSY goes high after the dead−time register was written to via SPI but not uploaded into the dead−time counter. Upload
happens at the beginning of every dead time measuring period (falling edge of a gate signal) and clears the FDTIBSY flag.
A write access MRFDTIF = 01h also clears the FDTIBSY flag.
MRRST
(Full Dynamic Access)
ADDR
Data Name
15h
MRRST
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Write 00h: Reset WDT / Write FFh: Reset latch off
MRRST[7:0]
Write access to this register resets the Watchdog or the Error latch.
♦ Write MRRST[7:0] = 00h: Reset WDT
♦ Write MRRST[7:0] = FFh: Reset latch off
MRORB (Default: 00h)
(Register for OTP Programming Integrity Check. Write During EN = Low Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
16h
MRORB
0
0
0
0
0
0
ORBEN
ORBLV
ORBEN
Setting this bit puts the device into OTP integrity check mode.
♦ ORBEN = 0: Normal
♦ ORBEN = 1: OTP bias read mode
ORBLV
Changes the OTP readout thresholds to high and low, to verify data integrity.
♦ ORBLV = 0: OTP low bias read mode at ORBEN = 1
♦ ORBLV = 1: OTP high bias read mode at ORBEN = 1
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31
LV8968BBUW
MRODL
(Write Access During EN = Low Only)
ADDR
Data Name
17h
MRODL
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Write 00h: Execute OTP data download
MRODL[7:0]
A write initiates an OTP data download into the main registers in standby mode. In Normal mode, OTP download can be
initiated only when AWODLEN is set regardless of MRODL.
♦ Write MRODL[7:0] = 00h: Execute OTP data download
MRDIAG0
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
20h
MRDIAG0
0
0
0
WDTPO
THSPO
THWPO
FSPO
OCPO
WDTPO
Watchdog error flag.
♦ WDTPO = 0: Normal
♦ WDTPO = 1: Detect WDT error
THSPO
Over temperature shutoff flag.
♦ THSPO = 0: Normal
♦ THSPO = 1: Detect thermal shut down error
THWPO
Thermal warning flag.
♦ THWPO = 0: Normal
♦ THWPO = 1: Detect thermal warning error
FSPO
FET short circuit detection flag.
♦ FSPO = 0: Normal
♦ FSPO = 1: Detect FET short error
OCPO
Over−current error flag.
♦ OCPO = 0: Normal
♦ OCPO = 1: Detect over−current error
MRDIAG1
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
21h
MRDIAG1
0
0
0
VCUVPO
VGUVPO
VDOVPO
VSOVPO
VSUVPO
VCUVPO
VCC under−voltage flag.
♦ VCUVPO = 0: Normal
♦ VCUVPO = 1: Detect VCC under voltage error
VGUVPO
VG under−voltage flag.
♦ VGUVPO = 0: Normal
♦ VGUVPO = 1: Detect VG under voltage error
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32
LV8968BBUW
VDOVPO
VDH over−voltage flag.
♦ VDOVPO = 0: Normal
♦ VDOVPO = 1: Detect VDH over voltage error
VSOVPO
VS over−voltage flag.
♦ VSOVPO = 0: Normal
♦ VSOVPO = 1: Detect VS over voltage error
VSUVPO
VS under−voltage flag.
♦ VSUVPO = 0: Normal
♦ VSUVPO = 1: Detect VS under voltage error
MRACK
(Read Only)
ADDR
Data Name
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
22h
MRACK
0
1
0
1
0
1
0
1
MRACK[7:0]
For SPI data verification. A read must result in 55h.
♦ MRACK[7:0] read data is fixed 55h
ORCONF0 ~ 3 (Default: 00h)
(OTP Backup for Critical System Registers. Programmable During EN = L Only)
ADDR
Data Name
D[7]
D[6]
40h
ORCONF0
ORCONF0[7:6]
41h
ORCONF1
42h
ORCONF2
43h
ORCONF3
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
THTSEL
DFCSEL
DIAGLTO
DIAGPOL
VGVSEL
VCVSEL
WDTPS
THSPS
THWPS
ORCONF1[7:5]
ORCONF2[7:6]
VDOVPS[1:0]
VSOVPS[1:0]
VGUVPS[1:0]
VSUVPS[1:0]
ORCONF3[7:1]
ORCONF0 ~ 3
♦ ORCONF0 ~ 3 data is transferred to MRCONF0 ~ 3 at OTP data download
♦ ORCONF0[7:6], ORCONF1[7:5], ORCONF2[7:6], ORCONF3[7:1] data is not transferred to MRCONF
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33
OSAENB
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPQFP48 7x7 / SQFP48K
CASE 131AN
ISSUE A
DOCUMENT NUMBER:
DESCRIPTION:
98AON78439F
SPQFP48 7X7 / SQFP48K
DATE 08 NOV 2013
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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