MC100EP101MNG

3.3 V/5 V ECL Quad 4-Input OR/NOR MC100EP101 Description The MC100EP101 is a Quad 4−input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. www.onsemi.com MARKING DIAGRAMS* Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • • • MC100 EP101 AWLYYWWG with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant LQFP−32 FA SUFFIX CASE 561AB 1 1 MC100 EP101 AWLYYWWG G 32 QFN32 MN SUFFIX CASE 488AM A WL YY WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device © Semiconductor Components Industries, LLC, 2006 April, 2021 − Rev. 12 1 Package Shipping MC100EP101FAG LQFP−32 (Pb−Free) 250 Units / Tray MC100EP101MNG QFN−32 (Pb−Free) 74 Units / Tube Publication Order Number: MC100EP101/D MC100EP101 D0d D1a D1b D1c D1d D2a D2b D2c VCC VCC Q0 24 23 22 21 20 19 18 32 17 31 30 Q0 VEE D0a D0b D0c 29 28 27 26 25 D0c 25 16 D2d VCC 1 24 D0d D0b 26 15 D3a Q1 2 23 D1a D0a 27 14 D3b Q1 3 22 D1b VEE 28 13 VCC Q2 4 21 D1c Q0 29 12 D3c Q2 5 Q0 30 11 D3d Q3 6 19 D2a VCC 31 10 VEE Q3 7 18 D2b VCC 32 9 NC VCC 8 17 D2c MC100EP101 1 2 3 4 5 6 7 8 MC100EP101 9 10 11 12 13 14 20 D1d 15 16 NC VEE D3d D3c VCC D3b D3a D2d VCC Q1 Q1 Q2 Q2 Q3 Q3 VCC Figure 2. 32−Lead QFN Pinout (Top View) Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN D0a FUNCTION D0a*−D3d* ECL Data Inputs D0b Q0 D0c Q0 D0d Q0−Q3, Q0−Q3 ECL Data Outputs VCC Positive Supply D1a VEE Negative Supply D1b Q1 NC No Connect D1c Q1 EP for QFN−32, only The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat− sinking conduit. The pad is electrically connected to VEE. D1d D2a D2b Q2 D2c Q2 D2d * Pins will default LOW when left open. D3a Table 2. TRUTH TABLE D3b D3c Dna Dnb Dnc Dnd Qn Qn L H X X X H L X H X X H L X X H X H L X X X H H L H H H H H H L L L L L D3d VEE Figure 3. Logic Diagram www.onsemi.com 2 Q3 Q3 MC100EP101 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg LQFP−32 QFN−32 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in Transistor Count 173 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ±0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard 32 LQFP 12 to 17 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm QFN−32 QFN−32 31 27 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W Tsol Wave Solder (Pb−Free) 265 °C VI ≤ VCC VI ≤ VEE Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 3 MC100EP101 Table 5. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 55 75 40 58 75 45 60 85 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 −150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 3. All loading with 50 W to VCC − 2.0 V. Table 6. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 4) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 58 75 40 61 75 45 64 85 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 5) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note5) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 −150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 4. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 5. All loading with 50 W to VCC − 2.0 V. Table 7. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 6) −40°C Symbol Characteristic VCC = −3.3V VCC = −5.0 V 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 40 40 55 58 75 75 40 40 58 61 75 75 45 45 60 64 85 85 mA 50 63 80 55 67 85 60 70 88 mA IEE Power Supply Current IEE Power Supply Current VOH Output HIGH Voltage (Note 7) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 7) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV IIH Input HIGH Current 150 mA IIL Input LOW Current 150 −150 150 −150 −150 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 6. Input and output parameters vary 1:1 with VCC. 7. All loading with 50 W to VCC − 2.0 V. www.onsemi.com 4 MC100EP101 Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 8) −40°C Symbol Characteristic Min fmax Maximum Frequency (See Figure 4. Fmax/JITTER) tPLH, tPHL Propagation Delay tSKEW Within Device Skew Device to Device Skew (Note 9) tJITTER Cycle−to−Cycle Jitter (See Figure 4. Fmax/JITTER) tr tf 25°C Max Min >3 D to Q, Q 10 100 Output Rise/Fall Times (20% − 80%) Typ Max Min >3 Typ Max >3 Unit GHz ps 125 180 225 280 325 380 250 300 370 400 15 50 200 20 0.2