MC100EP105FAR2

3.3 V/5 V ECL Quad 2-Input Differential AND/NAND MC10EP105, MC100EP105 Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. www.onsemi.com Features LQFP−32 FA SUFFIX CASE 561AB • 275 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V MARKING DIAGRAMS* • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Safety Clamp on Inputs • These Devices are Pb-Free, Halogen Free and are RoHS Compliant MCxxx EP105 AWLYYWWG xxx A WL YY WW G = 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping† MC10EP105FAG LQFP−32 250 Units / Tray (Pb−Free) MC100EP105FAG LQFP−32 250 Units / Tray (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 April, 2021 − Rev. 12 1 Publication Order Number: MC10EP105/D MC10EP105, MC100EP105 D0b D1a D1a D1b D1b D2a D2a D2b 24 23 22 21 20 19 18 17 D0b 25 16 D2b D0a 26 15 D3a D0a 27 14 D3a VEE 28 13 VCC Q0 29 12 D3b Q0 30 11 D3b VCC 31 10 VEE VCC 32 9 NC MC10EP105 MC100EP105 1 2 VCC Q1 3 4 5 6 7 8 Q1 Q2 Q2 Q3 Q3 VCC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. 32−Lead LQFP Pinout (Top View) D0a Table 1. PIN DESCRIPTION Q0 D0a D0b PIN Q0 D0b D1a Q1 D1a D1b Q1 D1b FUNCTION Dna*, Dnb*, Dna*, Dnb* ECL Data Inputs Qn, Qn ECL Data Outputs VCC Positive Supply VEE Negative Supply NC No Connect * Pins will default LOW when left open. D2a Q2 D2a D2b D2b Table 2. TRUTH TABLE Q2 D3a Q3 D3a D3b Q3 D3b Dna Dnb Dna L L H H L H L H H H L L VEE Figure 2. Logic Diagram www.onsemi.com 2 Dnb Qn Qn H L H L L L L H H H H L MC10EP105, MC100EP105 Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 4 kV > 100 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg LQFP−32 Level 2 Flammability Rating Oxygen Index: 28 to 34 UL−94 V−0 @ 0.125 in Transistor Count 444 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V Iout Output Current Continuous Surge 50 100 mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 32 LQFP 32 LQFP 80 55 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W Tsol Wave Solder (Pb−Free) 3 175 325 Within Device Skew Device to Device Skew (Note 21) 10 Cycle−to−Cycle Jitter (See Figure 3 Fmax/JITTER) Output Rise/Fall Times (20% − 80%) Q Max Min >3 250 Input Voltage Swing (Differential Configuration) 85°C Typ 200 Typ Max >3 275 350 50 10 0.2