MC100EP51DTR2

3.3 V/5 V ECL D Flip-Flop with Reset and Differential Clock MC10EP51, MC100EP51 Description www.onsemi.com The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2. The 100 Series contains temperature compensation. 8 8 1 SOIC−8 D SUFFIX CASE 751 8 HP51 ALYWG G HEP51 ALYW G • 350 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V 1 1 8 8 with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V • • • with VEE = −3.0 V to −5.5 V Open Input Default State Safety Clamp on Inputs These Devices are Pb−Free and are RoHS Compliant 1 DFN8 MN SUFFIX CASE 506AA MARKING DIAGRAMS* 8 Features 1 TSSOP−8 DT SUFFIX CASE 948R 1 5S MG G KP51 ALYWG G KEP51 ALYW G 1 1 H K 5S M A L Y W G = MC10 = MC100 = MC10 = Date Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. © Semiconductor Components Industries, LLC, 2012 April, 2021 − Rev. 11 1 Publication Order Number: MC10EP51/D MC10EP51, MC100EP51 Table 1. PIN DESCRIPTION RESET 1 8 PIN VCC R D 2 7 D Q Flip-Flop CLK 3 6 Q CLK 4 5 VEE FUNCTION CLK*, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset D* ECL Data Input Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8−Lead Pinout (Top View) and Logic Diagram D L H X R L L H CLK Z Z X Q L H L Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor N/A ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb−Free Pkg SOIC−8 TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 165 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2 MC10EP51, MC100EP51 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W Tsol Wave Solder 265 265 °C VI v VCC VI w VEE Pb Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1430 1755 1490 1815 mV 2.0 3.3 2.0 3.3 2.0 3.3 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 5) IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 4. All loading with 50 W to VCC − 2.0 V. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 3 MC10EP51, MC100EP51 Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV 2.0 5.0 2.0 5.0 2.0 5.0 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 8) IIH Input HIGH Current IIL Input LOW Current 150 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 7. All loading with 50 W to VCC − 2.0 V. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 9) −40°C Symbol Characteristic IEE Power Supply Current IEE Power Supply Current 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 23 30 40 23 30 40 23 30 40 mA 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 10) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 10) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 11) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current VEE + 2.0 0.0 VEE + 2.0 150 0.5 0.0 VEE + 2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC − 2.0 V. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 4 MC10EP51, MC100EP51 Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV 2.0 3.3 2.0 3.3 2.0 3.3 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 14) IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 W to VCC − 2.0 V. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 26 34 44 26 35 45 28 37 47 mA VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV 2.0 5.0 2.0 5.0 2.0 5.0 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 17) IIH Input HIGH Current IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 16. All loading with 50 W to VCC − 2.0 V. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. www.onsemi.com 5 MC10EP51, MC100EP51 Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 18) −40°C Characteristic Symbol 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 26 34 44 26 35 45 28 37 47 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 19) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 19) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 20) 0.0 V 150 mA IIH Input HIGH Current IIL Input LOW Current VEE + 2.0 0.0 VEE + 2.0 150 0.5 0.0 VEE + 2.0 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC − 2.0 V. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) −40°C Min Characteristic Symbol Typ 25°C Max Min >3 Typ 85°C Max Min >3 Typ Max fmax Maximum Frequency (Figure 2) >3 tPLH, tPHL Propagation Delay to Output Differential CLK, CLK to Q, Q 10 100 250 275 300 340 350 425 270 300 320 375 370 450 300 350 350 425 420 500 RESET to Q, Q 300 380 450 325 400 475 350 425 500 Unit GHz ps tRR Reset Recovery 150 150 150 ps tS tH Setup Time Hold Time 100 100 100 100 80 40 100 100 ps Minimum Pulse Width RESET 500 500 440 500 tPW tJITTER tr tf Cycle−to−Cycle Jitter (Figure 2) Output Rise/Fall Times (20% − 80%) Q, Q 70 440 0.2