3.3 V 2:1:9 Differential
HSTL/PECL/LVDS to HSTL
Clock Driver with LVTTL
Clock Select and Enable
MC100EP809
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Description
The MC100EP809 is a low skew 2:1:9 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
one differential HSTL and one differential LVPECL. Both input pairs
can accept LVDS levels. They are selected by the CLK_SEL pin
which is LVTTL. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE), which is LVTTL,
is synchronous ensuring the outputs will only be enabled/disabled
when they are already in LOW state (Figure 8).
The MC100EP809 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. The MC100EP809 output structure uses open
emitter architecture and will be terminated with 50 to ground
instead of a standard HSTL configuration (Figure 6). To ensure the
tight skew specification is realized, both sides of the differential output
need to be terminated identically into 50 even if only one output is
being used. If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
Designers can take advantage of the EP809’s performance to
distribute low skew clocks across the backplane of the board. Both
clock inputs may be single−end driven by biasing the non−driven pin
in an input pair (Figure 7).
Features
• 100 ps Typical Device−to−Device Skew
• 15 ps Typical within Device Skew
• HSTL Compatible Outputs Drive 50 to GND with no
•
•
•
•
•
•
March, 2021 − Rev. 11
32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
MC100
EP809
AWLYYWWG
G
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Offset Voltage
Maximum Frequency > 750 MHz
850 ps Typical Propagation Delay
Fully Compatible with Micrel SY89809L
PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V
with GND = 0 V, VCCO = 1.6 V to 2.0 V
Open Input Default State
This Device is Pb−Free and is RoHS Compliant
© Semiconductor Components Industries, LLC, 2015
1
1
Device
Package
Shipping
MC100EP809MNG
QFN32
(Pb−Free)
74 Units / Rail
Publication Order Number:
MC100EP809/D
MC100EP809
VCCO
Q0
Q0
Q1
Q1
Q2
Q2
VCCO
32
31
30
29
28
27
26
25
Exposed Pad
(EP)
VCCI
1
24 V
CCO
HSTL_CLK
2
23 Q3
HSTL_CLK
3
22 Q3
CLK_SEL
4
21 Q4
MC100EP809
LVPECL_CLK
5
LVPECL_CLK
6
19 Q5
GND
7
18 Q5
OE
8
17
12
13
VCCO
Q8
Q8
Q7
Q7
14
15
16
VCCO
11
Q6
10
Q6
9
20 Q4
VCCO
Figure 1. 32−Lead QFN Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
HSTL_CLK*,
HSTL_CLK**
LVPECL_CLK*,
LVPECL_CLK**
CLK_SEL**
OE**
Q0 − Q8,
Q0 − Q8
Table 2. TRUTH TABLE
FUNCTION
HSTL or LVDS Differential Inputs
LVPECL or LVDS Differential Inputs
LVCMOS/LVTTL Input CLK Select
CLK_SEL
Q0 − Q8
Q0 − Q8
L
L
L
H
L
H
L
H
H
L
HSTL_CLK
HSTL_CLK
H
H
LVPECL_CLK
LVPECL_CLK
*The OE (Output Enable) signal is synchronized with the rising edge
of the HSTL_CLK and LVOCL_CLK signals.
LVCMOS/LVTTL Output Enable
HSTL Differential Outputs
VCC1
Positive Supply_Core
(3.0 V − 3.6 V)
VCC0
Positive Supply_HSTL Outputs
(1.6 V − 2.0 V)
GND
Ground
EP
OE*
The exposed pad (EP) on the QFN−32
package bottom is thermally connected to
the die for improved heat transfer out of the
package. THe exposed pad must be
attached to a heat−sinking conduit.
The pad is electrically connected to GND.
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
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2
MC100EP809
CLK_SEL
HSTL_CLK
0
9
HSTL_CLK
9
Q0−Q8 (HSTL)
Q0−Q8 (HSTL)
LVPECL_CLK
1
LVPECL_CLK
VCCI
GND
VCCO
Q
D
OE
Figure 2. Logic Diagram
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
37.5 k
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb−Free Pkg
QFN−32
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
478 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC1
Core Power Supply
GND = 0 V
VCC0 = 1.6 to 2.0 V
4
V
VCC0
HSTL Output Power Supply
GND = 0 V
VCC1 = 3.0 to 3.6 V
4
V
VI
Input Voltage
GND = 0 V
VI v VCC1
4
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
31
27
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
2S2P
12
°C/W
Tsol
Wave Solde
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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3
MC100EP809
Table 5. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
75
95
115
75
95
115
75
95
115
mA
ICC
Core Power Supply Current
VIH
Input HIGH Voltage (Single−Ended)
VCCI −
1.165
VCCI −
0.88
VCCI −
1.165
VCCI −
0.88
VCCI −
1.165
VCCI −
0.88
V
VIL
Input LOW Voltage (Single−Ended)
VCCI −
1.945
VCCI −
1.6
VCCI −
1.945
VCCI −
1.6
VCCI −
1.945
VCCI −
1.6
V
1.2
VCCI
1.2
VCCI
1.2
VCCI
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 2) (Figure 4)
LVPECL_CLK/LVPECL_CLK
IIH
Input HIGH Current
−150
150
−150
150
−150
150
A
IIL
Input LOW Current
−150
150
−150
150
−150
150
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
2. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
2.0
Min
Typ
85°C
Max
2.0
Min
Typ
Max
2.0
Unit
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
IIH
Input HIGH Current
−150
150
−150
150
−150
150
A
IIL
Input LOW Current
−300
300
−300
300
−300
300
A
0.8
V
0.8
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 7. HSTL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V
0°C
Characteristic
Min
VOH
Output HIGH Voltage (Note 3)
VOL
Output LOW Voltage (Note 3)
VIH
Min
1.0
1.2
0.1
0.4
Input HIGH Voltage (Figure 5)
VX +
0.1
VIL
Input LOW Voltage (Figure 5)
−0.3
VX
HSTL Input Crossover Voltage
0.68
0.9
0.68
0.9
0.68
0.9
V
IIH
Input HIGH Current
−150
150
−150
150
−150
150
A
IIL
Input LOW Current
−300
300
−300
300
−300
300
A
0.6
VCCI
− 1.2
0.6
VCCI
− 1.2
0.6
VCCI
− 1.2
V
VIHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
HSTL_CLK/HSTL_CLK
−
Typ
85°C
Max
Symbol
Typ
25°C
Max
Min
1.0
1.2
0.1
0.4
1.6
VX +
0.1
VX −
0.1
−0.3
−
Typ
Max
Unit
1.0
1.2
V
0.1
0.4
V
1.6
VX +
0.1
1.6
V
VX −
0.1
−0.3
VX −
0.1
V
−
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. All outputs loaded with 50 to GND (Figure 6).
4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal.
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4
MC100EP809
Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
85°C
Min
Typ
Max
600
600
450
850
750
575
700
700
820
850
950
1000
Min
Typ
Max
600
600
450
850
750
575
780
790
920
950
1070
1110
ps
ps
Unit
VOpp
Differential Output Voltage (Figure 3)
fout < 100 MHz
fout < 500 MHz
fout < 750 MHz
600
600
450
850
750
575
tPLH
tPHL
Propagation Delay
(Differential Configuration)
LVPECL_CLK to Q
HSTL_CLK to Q
680
690
800
830
930
990
tskew
Within−Device Skew (Note 6)
Device−to−Device Skew (Note 7)
15
100
50
200
15
100
50
200
15
100
50
200
ps
ps
tJITTER
Random Clock Jitter (Figure 3) (RMS)
1.4
3.0
1.4
3.0
1.4
3.0
ps
VPP
Input Swing (Differential Configuration)
(Note 8) (Figure 4)
LVPECL
HSTL
200
200
200
200
200
200
mV
mV
mV
mV
mV
tS
OE Set Up Time (Note 9)
0.5
0.5
0.5
ns
tH
OE Hold Time
0.5
0.5
0.5
ns
tr/tf
Output Rise/Fall Time
(20% − 80%)
350
ps
600
350
450
600
350
600
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to GND (Figure 6).
6. Skew is measured between outputs under identical transitions and conditions on any one device.
7. Device−to−Device skew for identical transitions and conditions.
8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein.
9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (Figure 8).
900
9
800
8
VOPP
7
600
6
500
5
400
4
300
3
RMS JITTER
200
2
100
0
tJITTER ps (RMS)
VOPP (mV)
700
1
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
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5
MC100EP809
VCCI
VCCO(HSTL)
VCCI(LVPECL)
VPP
VIHCMR
VIH(DIFF)
VX
VIH(DIFF)
VIL(DIFF)
VIL(DIFF)
VPP
GND
Figure 4. LVPECL Differential Input Levels
GND
Figure 5. HSTL Differential Input Levels
Z = 50
Q
HSTL OUTPUT Q
50
50
GROUND
Figure 6. HSTL Output Termination and AC Test Reference
CLK/CLK
D.C. Bias*
*Must be CLK/CLK common mode voltage: ((VIH + VIL)/2).
Figure 7. Single−Ended CLK/CLK Input Configuration
CLK
CLK
OE
Q
Q
Figure 8. Output Enable (OE) Timing Diagram
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6
MC100EP809
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
1 32
SCALE 2:1
A
D
PIN ONE
LOCATION
ÉÉ
ÉÉ
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
B
DATE 23 OCT 2013
L1
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
0.15 C
0.15 C
EXPOSED Cu
A
DETAIL B
0.10 C
(A3)
A1
0.08 C
DETAIL A
9
32X
L
ALTERNATE
CONSTRUCTION
GENERIC
MARKING DIAGRAM*
K
D2
1
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
17
8
MOLD CMPD
DETAIL B
SEATING
PLANE
C
SIDE VIEW
NOTE 4
ÉÉ
ÉÉ
ÇÇ
TOP VIEW
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.18
0.30
5.00 BSC
2.95
3.25
5.00 BSC
2.95
3.25
0.50 BSC
0.20
−−−
0.30
0.50
−−−
0.15
E2
1
32
25
e
e/2
32X
b
0.10
M
C A B
0.05
M
C
BOTTOM VIEW
XXXXX = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
5.30
32X
0.63
3.35
3.35 5.30
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON20032D
QFN32 5x5 0.5P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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