MC100LVEL16DR2G

MC100LVEL16 3.3V ECL Differential Receiver Description The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V supply. The LVEL16 exhibits a wider VIHCMR range than its EL16 counterpart. With output transition times and propagation delays comparable to the EL16 the LVEL16 is ideally suited for interfacing with high frequency sources at 3.3 V supplies. Under open input conditions, the Q input will be pulled down to VEE and the Q input will be biased to VCC/2. This condition will force the Q output low. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • • • • • • • • 300 ps Propagation Delay High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors on D, Pullup and Pulldown Resistors on D Q Output will Default LOW with Inputs Open or at VEE These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAMS* 8 8 KVL16 ALYW G 1 SOIC−8 D SUFFIX CASE 751 1 8 8 1 TSSOP−8 DT SUFFIX CASE 948R KV16 ALYWG G 1 1 4BMG G DFN8 MN SUFFIX CASE 506AA A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2015 July, 2015 − Rev. 7 1 Publication Order Number: MC100LVEL16/D MC100LVEL16 Table 1. PIN DESCRIPTION NC 1 8 VCC D 2 7 Q D 3 6 Q VBB 4 5 VEE PIN FUNCTION D, D Q, Q VBB VCC VEE NC EP ECL Data Inputs ECL Data Outputs Reference Voltage Output Positive Supply Negative Supply No Connect (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. Logic Diagram and Pinout Assignment Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time out of Drypack, Pb−Free Packages (Note 1) Flammability Rating SOIC−8 TSSOP−8 DFN8 Oxygen Index: 28 to 34 Transistor Count > 4 KV > 400 V > 2 kV Level 1 Level 3 Level 1 UL 94 V−0 @ 0.125 in 79 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information. www.onsemi.com 2 MC100LVEL16 Table 3. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM SO−8 SO−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SO−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder