MC100LVEL39
3.3V ECL ÷2/4, ÷4/6 Clock
Generation Chip
Description
The MC100LVEL39 is a low skew ÷2/4, ÷4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single-ended input signal. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen with
an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state;
therefore, for systems which utilize multiple LVEL39s, the Master Reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one LVEL39, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and the
÷4/6 outputs of a single device.
The VBB pin, an internally generated voltage supply, is available to this
device only. For single-ended input conditions, the unused differential
input is connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via
a .01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, VBB should be left open.
Features
•
•
•
•
•
•
•
•
•
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•
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SOIC−20 WB
DW SUFFIX
CASE 751D
MARKING DIAGRAM*
20
100LVEL39
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
*For additional marking information, refer to
Application Note AND8002/D.
50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
ORDERING INFORMATION
Master Reset for Synchronization
ESD Protection: Human Body Model; > 2 kV
Device
Package
Shipping†
The 100 Series Contains Temperature Compensation
MC100LVEL39DWR2G SOIC−20 WB 1000/Tape & Reel
(Pb-Free)
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
†For information on tape and reel specifications, including part orientation and tape sizes, please refer
NECL Mode Operating Range:
to our Tape and Reel Packaging Specifications
VCC = 0 V with VEE = −3.0 V to −3.8 V
Brochure, BRD8011/D.
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
♦ For Additional Information, see Application Note
• Transistor Count = 419 devices
AND8003/D
• These Devices are Pb-Free, Halogen Free and are
Flammability Rating: UL 94 V−0 @ 0.125 in,
RoHS Compliant
Oxygen Index: 28 to 34
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 11
1
Publication Order Number:
MC100LVEL39/D
MC100LVEL39
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
VEE
20
19
18
17
16
15
14
13
12
11
1
VCC
2
3
4
EN DIVSELb CLK
5
6
7
8
CLK
VBB
MR
VCC
9
Table 1. PIN DESCRIPTION
Column Head
CLK, CLK
Q0, Q1; Q0, Q1
Q2, Q3; Q2, Q3
DIVSELa, DIVSELb
EN
MR
VBB
VCC
VEE
NC
10
NC DIVSELa
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
ECL Diff Clock Inputs
ECL Diff ÷2/4 Outputs
ECL Diff ÷4/6 Outputs
ECL Frequency Select Inputs
ECL Sync Enable
ECL Master Reset
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Figure 1. Pinout: SOIC−20 WB (Top View)
Table 2. FUNCTION TABLE
DIVSELa
Q0
CLK
÷2/4
CLK
R
Q0
÷4/6
R
MR
EN
MR
Z
ZZ
X
L
H
X
L
L
H
Function
Divide
Hold Q0−3
Reset Qo−3
Z = Low-to-High Transition
ZZ = High-to-Low Transition
X = Don’t Care
Q1
Q1
EN
CLK
Q2
DIVSELa
Q0, Q1 Outputs
Q2
L
H
Divide by 2
Divide by 4
DIVSELb
Q2, Q3 Outputs
L
H
Divide by 4
Divide by 6
Q3
Q3
DIVSELb
VBB
Figure 2. Logic Diagram
CLK
Q (÷2)
Q (÷4)
Q (÷6)
Figure 3. Timing Diagrams
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2
MC100LVEL39
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
Condition 1
Condition 2
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
± 0.5
mA
VI v VCC
VI w VEE
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction-to-Ambient)
0 lfpm
500 lfpm
SOIC−20 WB
90
60
°C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
SOIC−20 WB
30 to 35
°C/W
Tsol
Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. LVPECL DC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V (Note 1))
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
50
59
Min
85°C
Typ
Max
50
59
Min
Typ
Max
Unit
54
61
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single-Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
VPP < 500 mV
VPP ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
V
1.3
1.5
2.9
2.9
1.2
1.4
150
0.5
2.9
2.9
1.2
1.4
150
0.5
2.9
2.9
150
0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V.
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3
MC100LVEL39
Table 5. LVNECL DC CHARACTERISTICS (VCC = 0.0 V; VEE = −3.3 V (Note 1))
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
50
59
Min
85°C
Typ
Max
50
59
Min
Typ
Max
Unit
54
61
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 2)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single-Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single-Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 3)
VPP < 500 mV
VPP ≥ 500 mV
IIH
Input HIGH Current
IIL
Input LOW Current
V
−2.0
−1.8
−0.4
−0.4
−2.1
−1.9
−0.4
−0.4
150
0.5
−2.1
−1.9
−0.4
−0.4
150
0.5
150
0.5
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V.
Table 6. AC CHARACTERISTICS (VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 1))
−40°C
Symbol
Characteristic
Min
fmax
Maximum Toggle Frequency
1000
tPLH
tPHL
Propagation Delayed Output
CLK to Q (Diff)
CLK to Q (S.E.)
MR to Q
850
850
600
tSKEW
tJITTER
Typ
25°C
Max
Min
Typ
Max
1000
1150
1150
900
Within-Device Skew (Note 2)
Q0 − Q3
Part-to-Part
Q0 − Q3 (Diff)
2.0
Min
900
900
610
1200
1200
910
2.0
3.0
2.0
Setup Time
EN to CLK
DIVSEL to CLK
250
400
250
400
250
400
tH
Hold Time
CLK to EN
CLK to Div_Sel
100
150
100
150
100
150
Input Swing (Note 3)
CLK
250
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
CLK
MR
500
700
tr, tf
Output Rise/Fall Times Q (20% − 80%)
280
1000
250
100
1000
250
100
500
700
550
1250
1250
930
50
200
3.0
280
Max
280
ps
50
200
ps
3.0
ps
ps
ps
1000
mV
100
ps
ps
500
700
550
Unit
MHz
950
950
630
tS
VPP
Typ
1000
50
200
Random CLOCK Jitter (RMS) @
1000 MHz
85°C
550
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. VEE can vary ±0.3 V. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
2. Skew is measured between outputs under identical transitions.
3. VPP(min) is minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to
100 mV.
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4
MC100LVEL39
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
ECLinPS is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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