MC10EP31D

MC10EP31, MC100EP31 3.3V / 5V ECL D Flip-Flop with Set and Reset Description MARKING DIAGRAMS* 8 8 1 SOIC−8 D SUFFIX CASE 751 Features The 100 Series contains temperature compensation. • 340 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: • http://onsemi.com 1 8 8 1 VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State TSSOP−8 DT SUFFIX CASE 948R 1 KEP31 ALYW G 1 8 HP31 ALYWG G 1 KP31 ALYWG G 5O MG G • • Q Output Will Default LOW with Inputs Open or at VEE • Pb−Free Packages are Available 8 HEP31 ALYW G DFN8 MN SUFFIX CASE 506AA H K 5O 3J M = MC10 = MC100 = MC10 = MC100 = Date Code 3J MG G The MC10/100EP31 is a D flip−flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip−flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK. 1 4 1 4 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2008 August, 2008 − Rev. 10 1 Publication Order Number: MC10EP31/D MC10EP31, MC100EP31 Table 1. PIN DESCRIPTION SET 1 8 VCC Pin S D 2 7 D Q Flip Flop CLK 3 6 Q R RESET 4 5 Function CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset Set* ECL Asynchronous Set D* ECL Data Input Q, Q ECL Data Outputs VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. VEE *Pins will default LOW when left open. Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. TRUTH TABLE D SET RESET CLK Q L H X X X L L H L H L L L H H Z Z X X X L H H L UNDEF Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V > 2 kV Pb Pkg Pb−Free Pkg Level 1 Level 1 Level 1 Level 1 Level 3 Level 1 UL 94 V−0 @ 0.125 in 75 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC10EP31, MC100EP31 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder 3 Max >3 Unit fmax Maximum Frequency (Figure 2) GHz tPLH, tPHL Propagation Delay to Output Differential tRR Set/Reset Recovery 225 225 225 ps tS tH Setup Time Hold Time 100 150 100 150 100 150 ps tPW Minimum Pulse width tJITTER Cycle−to−Cycle Jitter (Figure 2) tr tf Output Rise/Fall Times (20% − 80%) ps CLK to Q, Q S, R to Q, Q 250 300 330 380 400 450 270 330 340 400 410 470 300 360 370 430 440 500 ps 550 SET, RESET Q, Q 50 450 550 0.2