MC34152, MC33152,
NCV33152
MOSFET Driver,
High Speed, Dual
The MC34152/MC33152 are dual noninverting high speed drivers
specifically designed for applications that require low current digital
signals to drive large capacitive loads with high slew rates. These
devices feature low input current making them CMOS/LSTTL logic
compatible, input hysteresis for fast output switching that is
independent of input transition time, and two high current totem pole
outputs ideally suited for driving power MOSFETs. Also included is
an undervoltage lockout with hysteresis to prevent system erratic
operation at low supply voltages.
Typical applications include switching power supplies, dc−to−dc
converters, capacitor charge pump voltage doublers/inverters, and
motor controllers.
This device is available in dual−in−line and surface mount packages.
Features
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
8
PDIP−8
P SUFFIX
CASE 626
8
1
1
8
SOIC−8
D SUFFIX
CASE 751
8
Two Independent Channels with 1.5 A Totem Pole Outputs
Output Rise and Fall Times of 15 ns with 1000 pF Load
CMOS/LSTTL Compatible Inputs with Hysteresis
Undervoltage Lockout with Hysteresis
Low Standby Current
Efficient High Frequency Operation
Enhanced System Performance with Common Switching Regulator
Control ICs
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Controls
These are Pb−Free and Halide−Free Devices
VCC
1
x
A
WL, L
YY, Y
WW, W
G or G
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
8 N.C.
Logic Input A 2
+
5.7V
7 Drive Output A
GND 3
6 VCC
Logic Input B 4
Drive Output A
Logic
Input A 2
3x152
ALYWG
G
1
N.C. 1
6
MC3x152P
AWL
YYWWG
5 Drive Output B
(Top View)
7
100k
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Drive Output B
Logic
Input B 4
5
100k
GND
3
Figure 1. Representative Diagram
© Semiconductor Components Industries, LLC, 2014
September, 2014− Rev. 14
1
Publication Order Number:
MC34152/D
MC34152, MC33152, NCV33152
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
VCC
20
V
Logic Inputs (Note 1)
Vin
−0.3 to +VCC
V
Drive Outputs (Note 2)
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to VCC)
IO
IO(clamp)
1.5
1.0
PD
RqJA
0.56
180
W
°C/W
PD
RqJA
1.0
100
W
°C/W
TJ
+150
°C
TA
0 to +70
−40 to +85
−40 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Electrostatic Discharge Sensitivity (ESD) (Note 3)
Human Body Model (HBM)
Machine Model (MM)
Charged Device Model (CDM)
ESD
A
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package Case 751
Maximum Power Dissipation @ TA = 50°C
Thermal Resistance, Junction−to−Air
P Suffix, Plastic Package, Case 626
Maximum Power Dissipation @ TA = 50°C
Thermal Resistance, Junction−to−Air
Operating Junction Temperature
Operating Ambient Temperature
Operating Ambient Temperature
Operating Ambient Temperature
MC34152
MC33152
MC33152V, NCV33152
V
2000
200
1500
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. ESD protection per following tests:
JEDEC Standard JESD22−A114−F for HBM
JEDEC Standard JESD22−A115−A for MM
JEDEC Standard JESD22−C101D for CDM.
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2
MC34152, MC33152, NCV33152
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA is the operating ambient
temperature range that applies [Note 4], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
VIH
VIL
−
0.8
1.75
1.58
2.6
−
IIH
IIL
−
−
100
20
300
100
VOL
−
−
−
10.5
10.4
10
0.8
1.1
1.8
11.2
11.1
10.8
1.2
1.5
2.5
−
−
−
RPD
−
100
−
tPLH (IN/OUT)
tPHL (IN/OUT)
−
−
55
40
120
120
Unit
LOGIC INPUTS
Input Threshold Voltage
V
Output Transition High−to−Low State
Output Transition Low−to−High State
mA
Input Current
High State (VIH = 2.6 V)
Low State (VIL = 0.8 V)
DRIVE OUTPUT
Output Voltage
Low State (Isink = 10 mA)
Low State (Isink = 50 mA)
Low State (Isink = 400 mA)
High State (Isource = 10 mA)
High State (Isource = 50 mA)
High State (Isource = 400 mA)
V
VOH
Output Pull−Down Resistor
kW
SWITCHING CHARACTERISTICS (TA = 25°C)
Propagation Delay (CL = 1.0 nF)
Logic Input to: Drive Output Rise (10% Input to 10% Output)
Drive Output Fall (90% Input to 90% Output)
ns
Drive Output Rise Time (10% to 90%)
Drive Output Rise Time (10% to 90%)
CL = 1.0 nF
CL = 2.5 nF
tr
−
−
14
36
30
−
ns
Drive Output Fall Time (90% to 10%)
Drive Output Fall Time (90% to 10%)
CL = 1.0 nF
CL = 2.5 nF
tf
−
−
15
32
30
−
ns
−
−
6.0
10.5
8.0
15
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
ICC
Operating Voltage
VCC
6.1
−
18
V
Vth
−
5.8
6.1
V
VCC(min)
−
5.3
−
V
mA
UNDERVOLTAGE LOCKOUT
Startup Threshold
Minimum Operating Voltage After Turn−On (VCC)
4. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34152, −40°C for MC33152, −40°C for MC33152V
Thigh = +70°C for MC34152, +85°C for MC33152, +125°C for MC33152V
NCV33152: Tlow = −40°C, Thigh = +125°C. Guaranteed by design.
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MC34152, MC33152, NCV33152
12V
4.7
0.1
+
6
+
+
-
5.7V
Logic Input
Drive Output
7
100k
2
50
5V
CL
90%
Logic Input
tr, tf ≤ 10 ns
10%
0V
5
tPHL
tPLH
100k
4
10%
Drive Output
90%
3
tr
Figure 3. Switching Waveform Definitions
Figure 2. Switching Characteristics Test CIrcuit
2.2
2.4
Iin , INPUT CURRENT (mA)
Vth , INPUT THRESHOLD VOLTAGE (V)
VCC=12V
TA=25°C
2.0
1.6
1.2
0.8
0.4
0
0
2.0
4.0
6.0
8.0
Vin, INPUT VOLTAGE (V)
10
VCC=12V
2.0
1.8
Upper Threshold
Low State Output
1.6
Lower Threshold
High State Output
1.4
1.2
1.0
-55
12
200
160
VCC=12V
CL=1.0nF
TA=25°C
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
120
80
40
0
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
Figure 5. Logic Input Threshold Voltage
versus Temperature
tPHL(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns)
Figure 4. Logic Input Current versus Input Voltage
tPLH(In/Out) , DRIVE OUTPUT PROPAGATION DELAY (ns)
tf
Vth(lower)
-1.6
-1.2
-0.8
-0.4
0
Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
Figure 6. Drive Output High to Low Propagation
Delay versus Logic Input Overdrive Voltage
200
Overdrive Voltage is with Respect VCC=12V
to the Logic InputUpperThreshold CL=1.0nF
TA=25°C
160
120
80
40
0
Vth(upper)
0
1
2
3
4
Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
Figure 7. Drive Output Low to High Propagation
Delay versus Logic Input Overdrive Voltage
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MC34152, MC33152, NCV33152
V
clamp, OUTPUT CLAMP VOLTAGE (V)
3.0
High State Clamp (Drive
Output Driven Above VCC)
VCC = 12 V
80 ms Pulsed Load
120 Hz Rate
TA = 25°C
2.0
1.0
VCC
0
0
Low State Clamp (Drive
Output Driven Below Ground)
GND
-1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IO, OUTPUT CLAMP CURRENT (A)
0
VCC
-1.0
-2.0
V
sat, OUTPUT SATURATION VOLTAGE (V)
V
sat, OUTPUT SATURATION VOLTAGE (V)
Figure 8. Drive Output Clamp Voltage
versus Clamp Current
Source Saturation VCC = 12 V
(Load to Ground) 80 ms Pulsed Load
120 Hz Rate
TA = 25°C
-3.0
3.0
2.0
1.0
Sink Saturation
(Load to VCC)
0
0
0.2
0.4
0.6
0.8
GND
1.0
1.2
0
-0.5
-0.7
-0.9
-1.1
Source Saturation
(Load to Ground)
VCC = 12 V
1.9
1.7
1.5
1.0
0.8
0.6
0
-55
1.4
Isource = 10 mA
VCC
Isource = 400 mA
Isink = 400 mA
Isink = 10 mA
Sink Saturation
(Load to VCC)
-25
GND
0
25
50
75
100
IO, OUTPUT CLAMP CURRENT (A)
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Drive Output Saturation Voltage
versus Load Current
Figure 10. Drive Output Saturation Voltage
versus Temperature
VCC = 12 V
Vin = 0 V to 5.0 V
CL = 1.0 nF
TA = 25°C
90% -
90% -
VCC = 12 V
Vin = 0 V to 5.0 V
CL = 1.0 nF
TA = 25°C
10% -
10% -
10 ns/DIV
10 ns/DIV
Figure 11. Drive Output Rise Time
Figure 12. Drive Output Fall Time
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5
125
80
80
VCC = 12 V
VIN = 0 V to 5.0 V
TA = 25°C
60
ICC , SUPPLY CURRENT (mA)
t r -t f , OUTPUT RISE‐FALL TIME(ns)
MC34152, MC33152, NCV33152
40
tf
20
tr
0
0.1
1.0
40
f = 500 kHz
20
f = 50 kHz
1.0
CL, OUTPUT LOAD CAPACITANCE (nF)
Figure 13. Drive Output Rise and Fall Time
versus Load Capacitance
Figure 14. Supply Current versus Drive
Output Load Capacitance
10
8.0
TA = 25°C
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25°C
1 - VCC = 18 V, CL = 2.5 nF
2 - VCC = 12 V, CL = 2.5 nF
3 - VCC = 18 V, CL = 1.0 nF
4 - VCC = 12 V, CL = 1.0 nF
1
2
3
4
20
0
f = 200 kHz
CL, OUTPUT LOAD CAPACITANCE (nF)
ICC , SUPPLY CURRENT (mA)
ICC , SUPPLY CURRENT (mA)
40
60
0
0.1
10
80
60
VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25°C
10 k
100
4.0
Logic Inputs Grounded
Low State Drive Outputs
2.0
0
1.0 M
Logic Inputs at VCC
High State Drive Outputs
6.0
0
f, INPUT FREQUENCY (Hz)
Figure 15. Supply Current versus Input Frequency
4.0
8.0
12
VCC, SUPPLY VOLTAGE (V)
16
Figure 16. Supply Current versus Supply Voltage
APPLICATIONS INFORMATION
Description
Output Stage
The MC34152 is a dual noninverting high speed driver
specifically designed to interface low current digital
circuitry with power MOSFETs. This device is constructed
with Schottky clamped Bipolar Analog technology which
offers a high degree of performance and ruggedness in
hostile industrial environments.
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 W
at 1.0 A. The low ‘on’ resistance allows high output
currents to be attained at a lower VCC than with
comparative CMOS drivers. Each output has a 100 kW
pulldown resistor to keep the MOSFET gate low when VCC
is less than 1.4 V. No over current or thermal protection has
been designed into the device, so output shorting to VCC or
ground must be avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn−on
transition, and below ground during the turn−off transition.
With CMOS drivers, this mode of operation can cause a
destructive output latchup condition. The MC34152 is
immune to output latchup. The Drive Outputs contain an
internal diode to VCC for clamping positive voltage
transients. When operating with VCC at 18 V, proper power
supply bypassing must be observed to prevent the output
ringing from exceeding the maximum 20 V device rating.
Negative output transients are clamped by the internal NPN
pullup transistor. Since full supply voltage is applied across
Input Stage
The Logic Inputs have 170 mV of hysteresis with the
input threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible
with CMOS and LSTTL logic families over its entire
operating voltage range. Input hysteresis provides fast
output switching that is independent of the input signal
transition time, preventing output oscillations as the input
thresholds are crossed. The inputs are designed to accept a
signal amplitude ranging from ground to VCC. This allows
the output of one channel to directly drive the input of a
second channel for master−slave operation. Each input has
a 30 kW pulldown resistor so that an unconnected open
input will cause the associated Drive Output to be in a
known low state.
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MC34152, MC33152, NCV33152
the NPN pullup during the negative output transient, power
dissipation at high frequencies can become excessive.
Figures 19, 20, and 21 show a method of using external
Schottky diode clamps to reduce driver power dissipation.
aid in this calculation, power MOSFET manufacturers
provide gate charge information on their data sheets.
Figure 17 shows a curve of gate voltage versus gate charge
for the ON Semiconductor MTM15N50. Note that there are
three distinct slopes to the curve representing different
input capacitance values. To completely switch the
MOSFET ‘on,’ the gate must be brought to 10 V with
respect to the source. The graph shows that a gate charge
Qg of 110 nC is required when operating the MOSFET with
a drain to source voltage VDS of 400 V.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V
to the 5.8 V upper threshold. The lower UVLO threshold
is 5.3 V, yielding about 500 mV of hysteresis.
16
VGS , GATE-TO-SOURCE VOLTAGE (V)
Power Dissipation
Circuit performance and long term reliability are
enhanced with reduced die temperature. Die temperature
increase is directly related to the power that the integrated
circuit must dissipate and the total thermal resistance from
the junction to ambient. The formula for calculating the
junction temperature with the package in free air is:
0
80
120
Qg, GATE CHARGE (nC)
160
PC(MOSFET) = VCC Qg f
The flat region from 10 nC to 55 nC is caused by the
drain−to−gate Miller capacitance, occurring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34152 is able to quickly deliver the required gate
charge for fast power efficient MOSFET switching. By
operating the MC34152 at a higher VCC, additional charge
can be provided to bring the gate above 10 V. This will
reduce the ‘on’ resistance of the MOSFET at the expense
of higher driver dissipation at a given operating frequency.
The transition power dissipation is due to extremely
short simultaneous conduction of internal circuit nodes
when the Drive Outputs change state. The transition power
dissipation per driver is approximately:
PQ = VCC (ICCL [1−D] + ICCH [D])
ICCL = Supply Current with Low State Drive
Outputs
ICCH = Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related
to the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
PT ≈ VCC (1.08 VCC CL f − 8 x 10−4)
PT must be greater than zero.
PC = VCC (VOH − VOL) CL f
=
=
=
=
40
The capacitive load power dissipation is directly related to
the required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
PQ = Quiescent Power Dissipation
PC = Capacitive Load Power Dissipation
PT = Transition Power Dissipation
VOH
VOL
CL
f
DQg
CGS = DV
GS
2.0nF
Figure 17. Gate−to−Source Voltage
versus Gate charge
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:
where:
VDS=400V
8.9nF
0
PD = PQ + PC + PT
where:
VDS=100V
4.0
TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation
RqJA = Thermal Resistance Junction to Ambient
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
where:
12
8.0
TJ = TA + PD (RqJA)
where:
MTM15B50
ID = 15 A
TA = 25°C
Switching time characterization of the MC34152 is
performed with fixed capacitive loads. Figure 13 shows
that for small capacitance loads, the switching speed is
limited by transistor turn−on/off time and the slew rate of
the internal nodes. For large capacitance loads, the
switching speed is limited by the maximum output current
capability of the integrated circuit.
High State Drive Output Voltage
Low State Drive Output Voltage
Load Capacitance
Frequency
When driving a MOSFET, the calculation of capacitive
load power PC is somewhat complicated by the changing
gate to source capacitance CGS as the device switches. To
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MC34152, MC33152, NCV33152
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
imperative to prevent excessive output ringing and
overshoot. Do not attempt to construct the driver circuit
on wire−wrap or plug−in prototype boards. When
driving large capacitive loads, the printed circuit board
must contain a low inductance ground plane to minimize
the voltage spikes induced by the high ground ripple
currents. All high current loops should be kept as short as
possible using heavy copper runs to provide a low
impedance high frequency path. For optimum drive
performance, it is recommended that the initial circuit
design contains dual power supply bypass capacitors
connected with short leads as close to the VCC pin and
ground as the layout will permit. Suggested capacitors are
a low inductance 0.1 mF ceramic in parallel with a 4.7 mF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely
critical and cannot be over emphasized.
VCC
47
0.1
Vin
6
Vin
+
-
5.7V
7
Rg
TL494
or
TL594
100k
100k
2
D1
1N5819
5
100k
4
Series gate resistor Rg may be needed to damp high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance in the
gate-source circuit. Rg will decrease the MOSFET switching speed. Schottky diode
D1 can reduce the driver's power dissipation due to excessive ringing, by preventing
the output pin from being driven below ground.
3
The MC34152 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 18. Enhanced System Performance with
Common Switching Regulators
Figure 19. MOSFET Parasitic Oscillations
100k
7
4X
1N5819
5
100k
100k
Isolation
Boundary
3
Output Schottky diodes are recommended when driving inductive loads at high
frequencies. The diodes reduce the driver's power dissipation by preventing the
output pins from being driven above VCC and below ground.
Figure 20. Direct Transformer Drive
1N
5819
3
Figure 21. Isolated MOSFET Drive
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MC34152, MC33152, NCV33152
IB
Vin
+
0
Vin
-
Base
Charge
Removal
C1
100k
100k
Rg(on)
Rg(off)
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET's turn-on and
turn-off times.
The totem-pole outputs can furnish negative base current for
enhanced transistor turn-off, with the addition of capacitor C1.
Figure 22. Controlled MOSFET Drive
Figure 23. Bipolar Transistor Drive
VCC = 15V
47
+
+
0.1
6
+
5.7V
7
6.8
10
+
1N5819
+ VO ≈ 2 .0VCC
+
100k
2
47
VCC
100k
5
4
6.8
10
+
1N5819
- VO ≈ -VCC
100k
10k
2N3904
330
pF
47
+
3
Output Load Regulation
The capacitor's equivalent series resistance limits the Drive Output Current to 1.5 A. An
additional series resistor may be required when using tantalum or other low ESR capacitors.
Figure 24. Dual Charge Pump Converter
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IO (mA)
+VO (V)
−VO (V)
0
1.0
10
20
30
50
27.7
27.4
26.4
25.5
24.6
22.6
−13.3
−12.9
−11.9
−11.2
−10.5
−9.4
MC34152, MC33152, NCV33152
ORDERING INFORMATION
Package
Shipping†
MC34152DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC34152DR2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
MC34152PG
PDIP−8
(Pb−Free)
50 Units / Rail
MC33152DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33152DR2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
MC33152PG
PDIP−8
(Pb−Free)
50 Units / Rail
MC33152VDG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33152VDR2G
SOIC−8
(Pb−Free)
2500 Tape & Reel
NCV33152DR2G*
SOIC−8
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix is for automotive and other applications requiring site and change control.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
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Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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