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MC33204DG

MC33204DG

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    SOIC14

  • 描述:

    IC OPAMP GP 4 CIRCUIT 14SOIC

  • 数据手册
  • 价格&库存
MC33204DG 数据手册
DATA SHEET www.onsemi.com Low Voltage, Rail-to-Rail Operational Amplifiers MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 • Low Voltage, Single Supply Operation • • • (+1.8 V and Ground to +12 V and Ground) Input Voltage Range Includes both Supply Rails Output Voltage Swings within 50 mV of both Rails No Phase Reversal on the Output for Over−driven Input Signals High Output Current (ISC = 80 mA, Typ) Low Supply Current (ID = 0.9 mA, Typ) 600 W Output Drive Capability Extended Operating Temperature Ranges (−40° to +105°C and −55° to +125°C) Typical Gain Bandwidth Product = 2.2 MHz NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2014 October, 2021 − Rev. 19 14 Micro8 DM SUFFIX CASE 846A 1 SOIC−14 D, VD SUFFIX CASE 751A 1 14 1 TSSOP−14 DTB SUFFIX CASE 948G ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. DEVICE MARKING INFORMATION Features • • • • • • • 1 8 The MC33201/2/4 family of operational amplifiers provide rail−to−rail operation on both the input and output. The inputs can be driven as high as 200 mV beyond the supply rails without phase reversal on the outputs, and the output can swing within 50 mV of each rail. This rail−to−rail operation enables the user to make full use of the supply voltage range available. It is designed to work at very low supply voltages (± 0.9 V) yet can operate with a supply of up to +12 V and ground. Output current boosting techniques provide a high output current capability while keeping the drain current of the amplifier to a minimum. Also, the combination of low noise and distortion with a high slew rate and drive capability make this an ideal amplifier for audio applications. SOIC−8 D, VD SUFFIX CASE 751 8 1 See general marking information in the device marking section on page 10 of this data sheet. Publication Order Number: MC33201/D MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 PIN CONNECTIONS MC33204 All Case Styles MC33201 All Case Styles Inputs 2 7 VCC 3 6 Output VEE 4 Inputs 1 Inputs 2 (Top View) 2 4 12 Inputs 4 11 VEE 10 5 6 13 2 3 9 Inputs 3 8 Output 3 (Top View) 8 VCC 7 Output 2 1 3 VEE 4 1 3 Output 2 7 MC33202 All Case Styles Inputs 1 2 VCC 4 5 NC Output 1 1 14 Output 4 Output 1 1 8 NC NC 1 6 2 5 Inputs 2 (Top View) VCC VCC VEE VCC Vin- Vout VCC Vin+ VEE This device contains 70 active transistors (each amplifier). Figure 1. Circuit Schematic (Each Amplifier) www.onsemi.com 2 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 MAXIMUM RATINGS Rating Symbol Value Unit VS +13 V Input Differential Voltage Range VIDR Note 1 V Common Mode Input Voltage Range (Note 2) VCM VCC + 0.5 V to VEE − 0.5 V V Output Short Circuit Duration ts Note 3 sec Maximum Junction Temperature TJ +150 °C Storage Temperature Tstg − 65 to +150 °C Maximum Power Dissipation PD Note 3 mW Supply Voltage (VCC to VEE) DC ELECTRICAL CHARACTERISTICS (TA = 25°C) Characteristic VCC = 2.0 V VCC = 3.3 V VCC = 5.0 V Input Offset Voltage VIO (max) MC33201, NCV33201V MC33202, NCV33202, V MC33204, NCV33204, V ± 8.0 ±10 ±12 ± 8.0 ±10 ±12 ± 6.0 ± 8.0 ±10 Output Voltage Swing VOH (RL = 10 kW) VOL (RL = 10 kW) 1.9 0.10 3.15 0.15 4.85 0.15 Power Supply Current per Amplifier (ID) 1.125 1.125 1.125 Unit mV Vmin Vmax mA Specifications at VCC = 3.3 V are guaranteed by the 2.0 V and 5.0 V tests. VEE = GND. DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.) Figure Symbol Input Offset Voltage (VCM 0 V to 0.5 V, VCM 1.0 V to 5.0 V) MC33201/NCV33201V: TA = + 25°C MC33201: TA = − 40° to +105°C MC33201V/NCV33201V: TA = − 55° to +125°C MC33202/NCV33202, V: TA = + 25°C MC33202/NCV33202: TA = − 40° to +105°C MC33202V/NCV33202V: TA = − 55° to +125°C (Note 4) MC33204/NCV33204V: TA = + 25°C MC33204: TA = − 40° to +105°C MC33204V/NCV33204V: TA = − 55° to +125°C (Note 4) 3 ⎮VIO⎮ Input Offset Voltage Temperature Coefficient (RS = 50 W) TA = − 40° to +105°C TA = − 55° to +125°C 4 Characteristic Input Bias Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) TA = + 25°C TA = − 40° to +105°C TA = − 55° to +125°C 5, 6 DVIO/DT ⎮IIB⎮ Min Typ Max − − − − − − − − − − − − − − − − − − 6.0 9.0 13 8.0 11 14 10 13 17 − − 2.0 2.0 − − − − − 80 100 − 200 250 500 Unit mV mV/°C nA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The differential input voltage of each amplifier is limited by two internal parallel back−to−back diodes. For additional differential input voltage range, use current limiting resistors in series with the input pins. 2. The input common mode voltage range is limited by internal diodes connected from the inputs to both supply rails. Therefore, the voltage on either input must not exceed either supply rail by more than 500 mV. 3. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See Figure 2) 4. All NCV devices are qualified for Automotive use. www.onsemi.com 3 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 DC ELECTRICAL CHARACTERISTICS (cont.) (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.) Figure Symbol Input Offset Current (VCM = 0 V to 0.5 V, VCM = 1.0 V to 5.0 V) TA = + 25°C TA = − 40° to +105°C TA = − 55° to +125°C − ⎮IIO⎮ Common Mode Input Voltage Range − VICR Large Signal Voltage Gain (VCC = + 5.0 V, VEE = − 5.0 V) RL = 10 kW RL = 600 W 7 AVOL Characteristic Output Voltage Swing (VID = ± 0.2 V) RL = 10 kW RL = 10 kW RL = 600 W RL = 600 W Min Typ Max − − − 5.0 10 − 50 100 200 VEE − VCC Unit nA V kV/V 50 25 300 250 − − VOH VOL VOH VOL 4.85 − 4.75 − 4.95 0.05 4.85 0.15 − 0.15 − 0.25 60 90 − 500 25 − 50 80 − − − 0.9 0.9 1.125 1.125 8, 9, 10 V Common Mode Rejection (Vin = 0 V to 5.0 V) 11 CMR Power Supply Rejection Ratio VCC/VEE = 5.0 V/GND to 3.0 V/GND 12 PSRR Output Short Circuit Current (Source and Sink) 13, 14 ISC Power Supply Current per Amplifier (VO = 0 V) TA = − 40° to +105°C TA = − 55° to +125°C 15 ID dB mV/V mA mA AC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 V, VEE = Ground, TA = 25°C, unless otherwise noted.) Characteristic Slew Rate (VS = ± 2.5 V, VO = − 2.0 V to + 2.0 V, RL = 2.0 kW, AV = +1.0) Figure Symbol 16, 26 SR Min Typ Max 0.5 1.0 − Unit V/ms Gain Bandwidth Product (f = 100 kHz) 17 GBW − 2.2 − MHz Gain Margin (RL = 600 W, CL = 0 pF) 20, 21, 22 AM − 12 − dB Phase Margin (RL = 600 W, CL = 0 pF) 20, 21, 22 OM − 65 − Deg 23 CS − 90 − dB BWP − 28 − kHz − − 0.002 0.008 − − − 100 − Rin − 200 − kW Cin − 8.0 − pF − − 25 20 − − nV/ Hz − − 0.8 0.2 − − Channel Separation (f = 1.0 Hz to 20 kHz, AV = 100) Power Bandwidth (VO = 4.0 Vpp, RL = 600 W, THD ≤ 1 %) 24 Total Harmonic Distortion (RL = 600 W, VO = 1.0 Vpp, AV = 1.0) f = 1.0 kHz f = 10 kHz Open Loop Output Impedance (VO = 0 V, f = 2.0 MHz, AV = 10) THD ⎮ZO⎮ Differential Input Resistance (VCM = 0 V) Differential Input Capacitance (VCM = 0 V) Equivalent Input Noise Voltage (RS = 100 W) f = 10 Hz f = 1.0 kHz 25 Equivalent Input Noise Current f = 10 Hz f = 1.0 kHz 25 www.onsemi.com 4 en in % W pA/ Hz 2500 40 PERCENTAGE OF AMPLIFIERS (%) PD(max) , MAXIMUM POWER DISSIPATION (mW) MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 8 and 14 Pin DIP Pkg 2000 TSSOP-14 Pkg 1500 SO-14 Pkg 1000 SOIC-8 Pkg 500 0 -55 -40 -25 0 25 50 85 TA, AMBIENT TEMPERATURE (°C) 30 25 20 15 10 5.0 0 -10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0 6.0 VIO, INPUT OFFSET VOLTAGE (mV) 125 Figure 2. Maximum Power Dissipation versus Temperature I IB , INPUT BIAS CURRENT (nA) 30 160 120 20 10 0 -50 -40 -30 -20 -10 0 10 20 30 40 VCC = +5.0 V VEE = Gnd VCM = 0 V to 0.5 V 80 VCM > 1.0 V 40 0 -55 -40 -25 50 TCV , INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (mV/°C) IO A VOL , OPEN LOOP VOLTAGE GAIN (kV/V) 100 50 0 -50 -100 VCC = 12 V VEE = Gnd TA = 25°C -200 0 2.0 4.0 6.0 8.0 10 VCM, INPUT COMMON MODE VOLTAGE (V) 25 70 85 125 Figure 5. Input Bias Current versus Temperature 150 -150 0 TA, AMBIENT TEMPERATURE (°C) Figure 4. Input Offset Voltage Temperature Coefficient Distribution I IB , INPUT BIAS CURRENT (nA) 10 200 360 amplifiers tested from 3 (MC33204) wafer lots VCC = +5.0 V VEE = Gnd TA = 25°C DIP Package 40 -250 8.0 Figure 3. Input Offset Voltage Distribution 50 PERCENTAGE OF AMPLIFIERS (%) 360 amplifiers tested from 3 (MC33204) wafer lots VCC = +5.0 V VEE = Gnd TA = 25°C DIP Package 35 12 300 260 220 180 140 VCC = +5.0 V VEE = Gnd RL = 600 W DVO = 0.5 V to 4.5 V 100 -55 -40 -25 Figure 6. Input Bias Current versus Common Mode Voltage 0 25 70 85 TA, AMBIENT TEMPERATURE (°C) 105 Figure 7. Open Loop Voltage Gain versus Temperature www.onsemi.com 5 125 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 RL = 600 W TA = 25°C 10 8.0 6.0 4.0 2.0 0 ±1.0 VCC VSAT, OUTPUT SATURATION VOLTAGE (V) VO, OUTPUT VOLTAGE (Vpp ) 12 ±2.0 ±3.0 ±4.0 ±5.0 VCC,⎮VEE⎮ SUPPLY VOLTAGE (V) ±6.0 TA = -55°C TA = 125°C VCC - 0.4 V TA = -55°C CMR, COMMON MODE REJECTION (dB) VO, OUTPUT VOLTAGE (Vpp ) 6.0 VCC = +6.0 V VEE = -6.0 V RL = 600 W AV = +1.0 TA = 25°C 5.0 60 40 VCC = +6.0 V VEE = -6.0 V TA = -55° to +125°C 20 0 10 I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) PSR, POWER SUPPLY REJECTION (dB) PSR+ 80 60 PSR40 VCC = +6.0 V VEE = -6.0 V TA = -55° to +125°C 0 1.0 k 10 k f, FREQUENCY (Hz) 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M Figure 11. Common Mode Rejection versus Frequency 100 100 VEE 20 15 80 1.0 M 120 10 10 IL, LOAD CURRENT (mA) 100 Figure 10. Output Voltage versus Frequency 20 VEE + 0.2 V Figure 9. Output Saturation Voltage versus Load Current 9.0 10 k 100 k f, FREQUENCY (Hz) TA = 25°C TA = 125°C 0 12 0 1.0 k VEE + 0.4 V VCC = +5.0 V VEE = -5.0 V Figure 8. Output Voltage Swing versus Supply Voltage 3.0 VCC - 0.2 V TA = 25°C 100 k 1.0 M 100 Source 80 60 Sink 40 VCC = +6.0 V VEE = -6.0 V TA = 25°C 20 0 0 1.0 2.0 3.0 4.0 5.0 ⎮Vout⎮, OUTPUT VOLTAGE (V) Figure 12. Power Supply Rejection versus Frequency Figure 13. Output Short Circuit Current versus Output Voltage www.onsemi.com 6 6.0 I CC , SUPPLY CURRENT PER AMPLIFIER (mA) 150 125 VCC = +5.0 V VEE = Gnd 100 Source 75 Sink 50 25 0 -55 -40 -25 0 25 70 85 TA, AMBIENT TEMPERATURE (°C) 105 125 2.0 1.6 TA = 125°C 1.2 TA = 25°C 0.8 TA = -55°C 0.4 0 ±0 ±1.0 Figure 14. Output Short Circuit Current versus Temperature GBW, GAIN BANDWIDTH PRODUCT (MHz) +Slew Rate 1.0 -Slew Rate 0.5 25 70 85 105 0 -55 -40 -25 0 25 70 85 105 Figure 16. Slew Rate versus Temperature Figure 17. Gain Bandwidth Product versus Temperature 40 VS = ±6.0 V TA = 25°C RL = 600 W 80 30 120 1A 2A 10 A 1.0 TA, AMBIENT TEMPERATURE (°C) 50 -30 10 k 2.0 TA, AMBIENT TEMPERATURE (°C) 70 -10 VCC = +2.5 V VEE = -2.5 V f = 100 kHz 3.0 125 2B 1A - Phase, CL = 0 pF 1B - Gain, CL = 0 pF 2A - Phase, CL = 300 pF 2B - Gain, CL = 300 pF 100 k 1B 1.0 M 160 200 O , EXCESS PHASE (DEGREES) , OPEN LOOP VOLTAGE GAIN (dB) VOL 0 4.0 A VOL, OPEN LOOP VOLTAGE GAIN (dB) SR, SLEW RATE (V/μ s) VCC = +2.5 V VEE = -2.5 V VO = ±2.0 V 0 -55 -40 -25 ±6.0 Figure 15. Supply Current per Amplifier versus Supply Voltage with No Load 2.0 1.5 ±2.0 ±3.0 ±4.0 ±5.0 VCC, ⎮VEE⎮, SUPPLY VOLTAGE (V) 70 30 120 2A 10 -10 160 1A - Phase, VS = ±6.0 V 1B - Gain, VS = ±6.0 V 2A - Phase, VS = ±1.0 V 2B - Gain, VS = ±1.0 V f, FREQUENCY (Hz) 100 k 1B 2B 200 1.0 M f, FREQUENCY (Hz) Figure 18. Voltage Gain and Phase versus Frequency Figure 19. Voltage Gain and Phase versus Frequency www.onsemi.com 7 80 1A -30 10 k 240 10 M 40 CL = 0 pF TA = 25°C RL = 600 W 50 125 240 10 M O , EXCESS PHASE (DEGREES) I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 75 50 50 40 30 VCC = +6.0 V VEE = -6.0 V RL = 600 W CL = 100 pF 40 30 20 20 10 10 Gain Margin 0 -55 -40 -25 0 25 70 85 105 O M , PHASE MARGIN (DEGREES) 60 A , GAIN MARGIN (dB) M O M , PHASE MARGIN (DEGREES) 60 60 60 VCC = +6.0 V VEE = -6.0 V TA = 25°C 45 30 15 0 0 125 10 100 Gain Margin 12 10 40 8.0 30 6.0 20 4.0 10 2.0 0 10 THD, TOTAL HARMONIC DISTORTION (%) 14 10 1.0 0 1.0 k 100 AV = 10 60 VCC = +6.0 V VEE = -6.0 V VO = 8.0 Vpp TA = 25°C 30 1.0 k 10 k f, FREQUENCY (Hz) Figure 22. Gain and Phase Margin versus Capacitive Load Figure 23. Channel Separation versus Frequency VCC = +5.0 V TA = 25°C VO = 2.0 Vpp VEE = -5.0 V RL = 600 W AV = 100 AV = 10 0.01 0.001 10 90 CL, CAPACITIVE LOAD (pF) AV = 1000 0.1 AV = 100 120 0 100 AV = 1.0 100 1.0 k 10 k 100 k en , EQUIVALENT INPUT NOISE VOLTAGE (nV/ Hz) 50 0 100 k 150 CS, CHANNEL SEPARATION (dB) 60 10 k Figure 21. Gain and Phase Margin versus Differential Source Resistance 16 Phase Margin 1.0 k RT, DIFFERENTIAL SOURCE RESISTANCE (W) A , GAIN MARGIN (dB) M O M , PHASE MARGIN (DEGREES) 70 15 Gain Margin Figure 20. Gain and Phase Margin versus Temperature VCC = +6.0 V VEE = -6.0 V RL = 600 W AV = 100 TA = 25°C 45 30 TA, AMBIENT TEMPERATURE (°C) 80 75 Phase Margin A , GAIN MARGIN (dB) M 70 Phase Margin 50 5.0 VCC = +6.0 V VEE = -6.0 V TA = 25°C 40 30 3.0 Noise Voltage 20 10 2.0 1.0 Noise Current 0 10 f, FREQUENCY (Hz) 100 1.0 k 10 k f, FREQUENCY (Hz) Figure 24. Total Harmonic Distortion versus Frequency Figure 25. Equivalent Input Noise Voltage and Current versus Frequency www.onsemi.com 8 4.0 0 100 k i n , INPUT REFERRED NOISE CURRENT (pA/ Hz) 70 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 DETAILED OPERATING DESCRIPTION Circuit Information The MC33201/2/4 family of operational amplifiers are unique in their ability to swing rail−to−rail on both the input and the output with a completely bipolar design. This offers low noise, high output current capability and a wide common mode input voltage range even with low supply voltages. Operation is guaranteed over an extended temperature range and at supply voltages of 2.0 V, 3.3 V and 5.0 V and ground. Since the common mode input voltage range extends from VCC to VEE, it can be operated with either single or split voltage supplies. The MC33201/2/4 are guaranteed not to latch or phase reverse over the entire common mode range, however, the inputs should not be allowed to exceed maximum ratings. Rail−to−rail performance is achieved at the input of the amplifiers by using parallel NPN−PNP differential input stages. When the inputs are within 800 mV of the negative rail, the PNP stage is on. When the inputs are more than 800 mV greater than VEE, the NPN stage is on. This switching of input pairs will cause a reversal of input bias currents (see Figure 6). Also, slight differences in offset voltage may be noted between the NPN and PNP pairs. Cross−coupling techniques have been used to keep this change to a minimum. In addition to its rail−to−rail performance, the output stage is current boosted to provide 80 mA of output current, enabling the op amp to drive 600 W loads. Because of this high output current capability, care should be taken not to exceed the 150°C maximum junction temperature. VCC = +6.0 V VEE = -6.0 V RL = 600 W CL = 100 pF TA = 25°C VCC = +6.0 V VEE = -6.0 V RL = 600 W CL = 100 pF TA = 25°C V , OUTPUT VOLTAGE (50 mV/DIV) O V , OUTPUT VOLTAGE (2.0 mV/DIV) O General Information t, TIME (10 ms/DIV) t, TIME (5.0 ms/DIV) V , OUTPUT VOLTAGE (2.0 V/DIV) O Figure 26. Noninverting Amplifier Slew Rate Figure 27. Small Signal Transient Response VCC = +6.0 V VEE = -6.0 V RL = 600 W CL = 100 pF AV = 1.0 TA = 25°C t, TIME (10 ms/DIV) Figure 28. Large Signal Transient Response Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self−align when subjected to a solder reflow process. www.onsemi.com 9 MC33201, MC33202, MC33204, NCV33201, NCV33202, NCV33204 ORDERING INFORMATION Operational Amplifier Function Single Device Operating Temperature Range Package MC33201DR2G TA= −40° to +105°C SOIC−8 (Pb−Free) MC33201VDR2G TA = −55° to 125°C Shipping† 2500 / Tape & Reel 2500 / Tape & Reel NCV33201VDR2G 2500 / Tape & Reel TA= −40 ° to +105°C MC33202DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Micro−8 (Pb−Free) 4000 / Tape & Reel TA = −55° to 125°C SOIC−8 (Pb−Free) 2500 / Tape & Reel TA= −40 ° to +105°C SO−14 (Pb−Free) 2500 Units / Tape & Reel TSSOP−14 (Pb−Free) 2500 Units / Tape & Reel SO−14 (Pb−Free) 2500 Units / Tape & Reel TSSOP−14 (Pb−Free) 2500 Units / Tape & Reel MC33202DMR2G Dual NCV33202DMR2G* MC33202VDR2G NCV33202VDR2G* MC33204DR2G Quad MC33204DTBR2G TA = −55° to 125°C NCV33204DR2G* NCV33204DTBR2G* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. MARKING DIAGRAMS SOIC−8 D SUFFIX CASE 751 8 1 14 8 3320x ALYW G TSSOP−14 DTB SUFFIX CASE 948G 14 SOIC−8 VD SUFFIX CASE 751 1 320xV ALYW G Micro−8 DM SUFFIX CASE 846A 8 * MC33 204 ALYWG G MC33 204V ALYWG G * ** 1 SO−14 VD SUFFIX CASE 751A 14 MC33204VDG AWLYWW * 1 x = 1 or 2 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb−Free Package G = Pb−Free Package (Note: Microdot may be in either location) *This marking diagram applies to NCV3320xV **This marking diagram applies to NCV33202DMR2G www.onsemi.com 10 14 3202 AYWG G 1 1 SO−14 D SUFFIX CASE 751A MC33204DG AWLYWW 1 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS Micro8 CASE 846A−02 ISSUE K DATE 16 JUL 2020 SCALE 2:1 GENERIC MARKING DIAGRAM* 8 XXXX AYWG G 1 XXXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98ASB14087C MICRO8 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. N-SOURCE N-GATE P-SOURCE P-GATE P-DRAIN P-DRAIN N-DRAIN N-DRAIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−14 WB CASE 948G ISSUE C 14 DATE 17 FEB 2016 1 SCALE 2:1 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S DETAIL E K A −V− K1 J J1 ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE H G D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS INCHES MIN MAX MIN MAX 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 −−− 1.20 −−− 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 BSC 0.026 BSC 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 BSC 0.252 BSC 0_ 8_ 0_ 8_ GENERIC MARKING DIAGRAM* 14 SOLDERING FOOTPRINT XXXX XXXX ALYWG G 7.06 1 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: 98ASH70246A DESCRIPTION: TSSOP−14 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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