MC74AC4040N

MC74AC4040 12-Stage Binary Ripple Counter The MC74AC4040 consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half that of the preceding one. The state of the counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the MC74AC4040 for some designs. www.onsemi.com MARKING DIAGRAM 16 SOIC−16 D SUFFIX CASE 751B 16 Features • • • • • 1 140 MHz Typ. Clock Outputs Source/Sink 24 mA Operating Voltage Range: 2.0 to 6.0 V High Noise Immunity These are Pb−Free Devices VCC Q11 Q10 Q8 Q9 16 15 14 13 12 11 1 A WL Y WW G RESET CLK 10 AC4040G AWLYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package Q1 9 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 1 2 3 4 5 6 7 8 Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND Figure 1. Pinout: 16−Lead Packages Conductors (Top View) FUNCTION TABLE Clock X Reset Output State L No Change L Advance to next state H All Outputs are low © Semiconductor Components Industries, LLC, 2015 March, 2015 − Rev. 8 1 Publication Order Number: MC74AC4040/D MC74AC4040 9 7 6 5 CLOCK 10 3 2 4 13 12 14 15 1 RESET 11 PIN 16 = VCC PIN 8 = GND Figure 2. Logic Diagram www.onsemi.com 2 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 MC74AC4040 MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V DC Input Voltage *0.5 ≤ VCC +0.5 V VO DC Output Voltage (Note 1) *0.5 ≤ VCC +0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±50 mA IO DC Output Sink/Source Current ±50 mA ICC DC Supply Current per Output Pin ±50 mA IGND DC Ground Current per Output Pin ±50 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction temperature under Bias +150 °C qJA Thermal Resistance (Note 2) 69.1 °C/W PD Power Dissipation in Still Air at 65°C (Note 3) 500 mW MSL Moisture Sensitivity FR Flammability Rating VESD ESD Withstand Voltage Human Body Model (Note 4) Machine Model (Note 5) Charged Device Model (Note 6) ILatch−Up Latch−Up Performance Above VCC and Below GND at 85°C (Note 7) VCC DC Supply Voltage VI Level 1 Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in > 2000 > 200 > 1000 V ±100 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. The package thermal impedance is calculated in accordance with JESD51−7. 3. 500 mW at 65°C; derate to 300 mW by 10 mW/ from 65°C to 85°C. 4. Tested to EIA/JESD22−A114−A. 5. Tested to EIA/JESD22−A115−A. 6. Tested to JESD22−C101−A. 7. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VCC DC Supply Voltage (Referenced to GND) VIN/VOUT Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr/tf Input Rise/Fall Time (Figure 1) VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V Min Max Unit 2.0 6.0 V 0 VCC − −40 +85 °C 0 0 0 150 40 25 ns/V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 3 MC74AC4040 DC CHARACTERISTICS (unless otherwise specified) Symbol Parameter Value Unit ICC Maximum Quiescent Supply Voltage 80 mA Vin = VCC or GND VCC = 5.5 V, TA = Worst Case ICC Maximum Quiescent Supply Current 8.0 mA Vin = VCC or GND VCC = 5.5 V, TA = 25°C DC CHARACTERISTICS 74AC 74AC VCC TA = +25°C TA = −40°C to +85°C Symbol Parameter (V) Typ VIH Minimum High Level Input Voltage 3.0 4.5 5.5 − − − 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT = 0.1 V or VCC − 0.1 V 3.0 4.5 5.5 − − − 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT = 0.1 V or VCC − 0.1 V 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 3.0 4.5 5.5 − − − 2.56 3.86 4.86 2.46 3.76 4.76 3.0 4.5 5.5 0.002 0.001 0.001 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 5.5 − − − 0.36 0.36 0.36 0.44 0.44 0.44 5.5 − ±0.1 5.5 − 5.5 − VIL VOH VOL IIN IOLD IOHD Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Output Voltage Maximum Input Leakage Current Minimum Dynamic Output Current{ Guaranteed Limits Conditions IOUT = −50 mA V *VIN = VIL or VIH −12 mA IOH −24 mA −24 mA IOUT = 50 mA V V *VIN = VIL or VIH 12 mA IOL 24 mA 24 mA ±1.0 mA VI = VCC, GND − 75 mA VOLD = 1.65 V Max − −75 mA VOHD = 3.85 V Min *All outputs loaded; thresholds on input associated with output under test. †Maximum test duration 2.0 ms, one output loaded at a time. www.onsemi.com 4 Unit MC74AC4040 AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) VCC* 74AC 74AC TA = +25°C TA = −40°C to +85°C CL = 50 pF CL = 50 pF (V) Min Typ Max Min Max Unit Fig. No. fmax Maximum Clock Frequency 3.3 5.0 110 130 120 140 − − 100 120 − − MHz − nCP to Q1 Propagation Delay nCP to Q1 3.3 5.0 2.0 2.0 − − 11 8.0 2.0 2.0 14 10 ns − Qn to Qn +1 Propagation Delay Qn to Qn +1 3.3 5.0 0 0 − − 5.5 3.5 0 0 6.5 4.5 ns − MR to Q tHL Propagation Delay MR to Q 3.3 5.0 3.0 3.0 − − 12 10 3.0 3.0 15 12 ns − trec nCP to MR Recovery Time 3.3 5.0 0 0 −2.5 −1.5 − − 0 0 − − ns − tw nCP Minimum Pulse Width Clock Pin 3.3 5.0 4.0 3.0 3.5 2.5 − − 4.5 3.5 − − ns − tw MR Minimum Pulse Width Master Reset 3.3 3.0 4.0 3.0 3.5 2.5 − − 4.5 3.5 − − ns − Symbol Parameter *Voltage Range 3.3 V is 3.3 V ±0.3 V. *Voltage Range 5.0 V is 5.0 V ±0.5 V. CAPACITANCE Symbol Parameter Value Typ Unit Test Conditions CIN Input Capacitance 4.5 pF VCC = 5.0 V CPD Power Dissipation Capacitance 50 pF VCC = 5.0 V ORDERING INFORMATION Package Shipping† MC74AC4040DG SOIC−16 (Pb−Free) 48 Units / Rail MC74AC4040DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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