MC74HC160ADTG

MC74HC160A Presettable Counters High−Performance Silicon−Gate CMOS The MC74HC160A is identical in pinout to the LS160. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC160A is a programmable BCD counters with asynchronous Reset input. http://onsemi.com 16 Features • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 234 FETs or 58.5 Equivalent Gates These are Pb−Free Devices P0 PRESENT DATA INPUTS P1 P2 P3 CLOCK COUNT ENABLES 3 14 4 13 5 12 6 11 2 15 Q0 Q1 Q2 MARKING DIAGRAMS SOIC−16 D SUFFIX CASE 751B 16 1 HC160AG AWLYWW 1 16 TSSOP−16 DT SUFFIX CASE 948F 16 1 HC 160A ALYWG G 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) BCD OUTPUTS PIN ASSIGNMENT Q3 RIPPLE CARRY OUT RESET 1 16 CLOCK 2 15 P0 3 14 VCC RIPPLE CARRY OUT Q0 P1 4 13 Q1 P2 5 12 Q2 RESET P3 6 11 Q3 LOAD ENABLE P 7 10 ENABLE T ENABLE P GND 8 9 PIN 16 = VCC PIN 8 = GND ENABLE T ORDERING INFORMATION Figure 1. Logic Diagram Device Count Mode Reset Mode HC160 BCD Asynchronous © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 2 LOAD See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. 1 Publication Order Number: MC74HC160A/D MC74HC160A FUNCTION TABLE Inputs Clock Outputs Reset* Load Enable P Enable T Q L X X X Reset H L X X Load Preset Data H H H H Count H H L X No Count H H X L No Count *HC160 is an Asynchronous Reset Device. H = High Level L = Low Level X = Don’t Care MAXIMUM RATINGS Symbol Parameter Value Unit −0.5 to +7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) −0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) −0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ±20 mA Iout DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature −65 to +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating − SOIC Package: − 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V −55 +125 °C 0 0 0 1000 500 400 ns http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC160A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V − 55 to 25°C v 85°C v 125°C Unit VIH Minimum High−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC − 0.1 V |Iout| v 20 mA 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Vin = VIH or VIL VOL Maximum Low−Level Output Voltage |Iout| v 2.4 m |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 2.4 m |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 mA 6.0 4 40 160 mA http://onsemi.com 3 MC74HC160A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Parameter Symbol VCC V − 55 to 25°C v 85°C v 125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle)* (Figures 3 and 8) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH Maximum Propagation Delay, Clock to Q (Figures 3 and 8) 2.0 4.5 6.0 170 34 29 215 43 37 255 51 43 ns 2.0 4.5 6.0 205 41 35 255 51 43 310 62 53 tPHL tPHL Maximum Propagation Delay, Reset to Q (HC160A Only) (Figures 4 and 8) 2.0 4.5 6.0 210 42 36 265 53 45 315 63 54 ns tPLH Maximum Propagation Delay, Enable T to Ripple Carry Out (Figures 5 and 8) 2.0 4.5 6.0 160 32 27 200 40 34 240 48 41 ns 2.0 4.5 6.0 195 39 33 245 49 42 295 59 50 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 2.0 4.5 6.0 215 43 37 270 54 46 325 65 55 tPHL tPLH Maximum Propagation Delay, Clock to Ripple Carry Out (Figures 3 and 8) tPHL ns tPHL Maximum Propagation Delay, Reset to Ripple Carry Out (HC160A Only) (Figures 4 and 8) 2.0 4.5 6.0 220 44 37 275 55 47 330 66 56 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 3 and 8) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns − 10 10 10 pF Cin Maximum Input Capacitance *Applies to noncascaded/nonsynchronously clocked configurations only. With synchronously cascaded counters, (1) Clock to Ripple Carry Out propagation delays, (2) Enable T or Enable P to Clock setup times, and (3) Clock to Enable T or Enable P hold times determine fmax. However, if Ripple Carry Out of each stage is tied to the Clock of the next stage (nonsynchronously clocked), the fmax in the table above is applicable. See Applications Information in this data sheet. Typical @ 25°C, VCC = 5.0 V CPD 60 Power Dissipation Capacitance (Per Package)* *Used to determine the no−load dynamic power consumption: PD = CPD VCC 2f + ICC VCC . http://onsemi.com 4 pF MC74HC160A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V − 55 to 25°C v 85°C v 125°C Unit tsu Minimum Setup Time, Preset Data Inputs to Clock (Figure 6) 2.0 4.5 6.0 150 30 26 190 38 33 225 45 38 ns tsu Minimum Setup Time, Load to Clock (Figure 6) 2.0 4.5 6.0 135 27 23 170 34 29 205 41 35 ns tsu Minimum Setup Time, Enable T or Enable P to Clock (Figure 7) 2.0 4.5 6.0 200 40 34 250 50 43 300 60 51 ns th Minimum Hold Time, Clock to Preset Data Inputs (Figure 6) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to Load (Figure 6) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns th Minimum Hold Time, Clock to Enable T or Enable P (Figure 7) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 4) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns trec Minimum Recovery Time, Load Inactive to Clock (Figure 6) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tw Minimum Pulse Width, Clock (Figure 3) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Reset (Figure 4) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times (Figure 3) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tr, tf http://onsemi.com 5 MC74HC160A FUNCTION DESCRIPTION Loading The HC160A is a programmable 4−bit synchronous counters that feature parallel Load, synchronous or asynchronous Reset, a Carry Output for cascading, and count−enable controls. The HC160A is a BCD counter with asynchronous Reset. With the rising edge of the Clock, a low level on Load (pin 9) loads the data from the Preset Data Input pins (P0, P1, P2, P3) into the internal flip−flops and onto the output pins, Q0 through Q3. The count function is disabled as long as Load is low. Although the HC160A is a BCD counters, they may be programmed to any state. If they are loaded with a state disallowed in BCD code, they will return to their normal count sequence within two clock pulses (see the Output State Diagram). INPUTS Clock (Pin 2) The internal flip−flops toggle and the output count advances with the rising edge of the Clock input. In addition, control functions, such as loading occur with the rising edge of the Clock input. Count Enable/Disable Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6) These devices have two count−enable control pins: Enable P (pin 7) and Enable T (pin 10). The devices count when these two pins and the Load pin are high. The logic equation is: Count Enable = Enable P  Enable T  Load The count is either enabled or disabled by the control inputs according to Table 1. In general, Enable P is a count−enable control; Enable T is both a count−enable and a Ripple−Carry Output control. These are the data inputs for programmable counting. Data on these pins may be synchronously loaded into the internal flip−flops and appear at the counter outputs. P0 (pin 3) is the least−significant bit and P3 (pin 6) is the most−significant bit. OUTPUTS Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11) These are the counter outputs (BCD or binary). Q0 (pin 14) is the least−significant bit and Q3 (pin 11) is the most−significant bit. Table 1. COUNT ENABLE/DISABLE Control Inputs Ripple Carry Out (Pin 15) When the counter is in its maximum state (1001 for the BCD counters or 1111 for the binary counters), this output goes high, providing an external look−ahead carry pulse that may be used to enable successive cascaded counters. Ripple Carry Out remains high only during the maximum count state. The logic equation for this output is: Ripple Carry Out = Enable T  Q0  Q1  Q2  Q3 for BCD counters Result at Outputs Load Enable P Enable T Q0 − Q3 Ripple Carry Out H H H Count L H H No Count High when Q0 −Q3 are maximum* X L H No Count High when Q0 −Q3 are maximum* X X L No Count L *Q0 through Q3 are maximum for the HC160A when Q3 Q2 Q1 Q0 = 1001. CONTROL FUNCTIONS Resetting A low level on the Reset pin (pin 1) resets the internal flip−flops and sets the outputs (Q0 through Q3) to a low level. The HC160A resets asynchronously. 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 Figure 2. Output State Diagrams HC160A BCD Counters http://onsemi.com 6 MC74HC160A SWITCHING WAVEFORMS tr tw tf VCC 90% 50% 10% CLOCK VCC 50% RESET GND GND tPHL tw 1/fmax tPHL tPLH ANY OUTPUT 50% ANY OUTPUT 90% 50% 10% trec VCC tTHL tTLH 50% CLOCK GND Figure 3. Figure 4. tr tf ENABLE T RIPPLE CARRY OUT VALID VCC 90% 50% 10% tPLH 90% 50% 10% GND tPHL INPUTS P0, P1, P2, P3 VCC 50% GND tsu tTLH th VCC tTHL LOAD 50% GND Figure 5. tsu trec th VCC CLOCK 50% GND Figure 6. TEST CIRCUIT VALID ENABLE T OR ENABLE P TEST POINT VCC 50% OUTPUT GND tsu DEVICE UNDER TEST th VCC CLOCK CL* 50% GND Figure 7. *Includes all probe and jig capacitance Figure 8. http://onsemi.com 7 3 http://onsemi.com 8 LOAD CLOCK RESET ENABLE T ENABLE P P3 P2 3 2 1 10 7 6 5 P1 4 P0 LOAD LOAD C C R Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 VCC = PIN 16 GND = PIN 8 Q3 Q2 Q1 Q0 15 RIPPLE CARRY OUT 11 12 13 14 The flip−flops shown in the circuit diagrams are Toggle−Enable flip−flops. A Toggle− Enable flip−flop is a combination of a D flip−flop and a T flip−flop. When loading data from Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of the flip−flop. The logic level at the Pn input is then clocked to the Q output of the flip−flop on the next rising edge of the clock. A logic zero on the Reset device input forces the internal clock (C) high and resets the Q output of the flip−flop low. T3 R C C LOAD LOAD P3 T2 R C C LOAD LOAD P2 T1 R C C LOAD LOAD P1 T0 R C C LOAD LOAD P0 MC74HC160A BCD Counter with Asynchronous Reset MC74HC160A MC74HC160A Sequence illustrated in waveforms: 1. Reset outputs to zero. 2. Preset to BCD seven. 3. Count to eight, nine, zero, one, two, and three. 4. Inhibit. RESET (HC160A) (ASYNCHRONOUS) LOAD P0 PRESET DATA INPUTS P1 P2 P3 CLOCK (HC160A) CLOCK (HC162A) COUNT ENABLES ENABLE P ENABLE T Q0 Q1 OUTPUTS Q2 Q3 RIPPLE CARRY OUT 7 8 9 0 1 2 3 COUNT RESET LOAD Figure 9. MC74HC160A Timing Diagram http://onsemi.com 9 INHIBIT MC74HC160A TYPICAL APPLICATIONS CASCADING LOAD INPUTS INPUTS LOAD H = COUNT L = DISABLE H = COUNT L = DISABLE P0 P1 P2 P3 ENABLE P LOAD P0 P1 P2 P3 ENABLE T LOAD P0 P1 P2 P3 ENABLE P ENABLE P RIPPLE CARRY OUT INPUTS RIPPLE CARRY OUT ENABLE T CLOCK CLOCK CLOCK R R R Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 RIPPLE CARRY OUT ENABLE T TO MORE SIGNIFICANT STAGES Q0 Q1 Q2 Q3 RESET OUTPUTS OUTPUTS OUTPUTS CLOCK NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on number of stages. This limitation is due to set up times between Enable (Port) and Clock. Figure 10. N−Bit Synchronous Counters INPUTS INPUTS INPUTS LOAD ENABLE P ENABLE T LOAD P0 P1 P2 P3 ENABLE P P0 P1 P2 P3 ENABLE P RIPPLE CARRY OUT ENABLE T CLOCK LOAD ENABLE T LOAD P0 P1 P2 P3 ENABLE P RIPPLE CARRY OUT ENABLE T CLOCK CLOCK CLOCK R R R Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 RIPPLE CARRY OUT TO MORE SIGNIFICANT STAGES Q0 Q1 Q2 Q3 RESET OUTPUTS OUTPUTS OUTPUTS Figure 11. Nibble Ripple Counter ORDERING INFORMATION Package Shipping† MC74HC160ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC160ADR2G SOIC−16 (Pb−Free) 2500 Tape & Reel Device MC74HC160ADTG TSSOP−16* 96 Units / Rail MC74HC160ADTR2G TSSOP−16* 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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