DATA SHEET
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Single 2-Input AND Gate
MARKING
DIAGRAMS
MC74HC1G08
Features
•
•
•
•
•
•
•
•
High Speed: tPD = 7 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
High Noise Immunity
Balanced Propagation Delays (tpLH = tpHL)
Symmetrical Output Impedance (IOH = IOL = 2 mA)
Chip Complexity: < 100 FETs
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
B
1
A
2
GND
3
5
5
TSOP−5
DT SUFFIX
CASE 483
XX
M
A
Y
W
G
5
XXXAYWG
G
XX MG
G
1
1
= Device Code
= Date Code*
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
5
1
SC−74A
DBV SUFFIX
CASE 318BQ
XXX
M
G
VCC
XXX MG
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
4
FUNCTION TABLE
Y
Figure 1. Pinout
&
Y
Figure 2. Logic Symbol
PIN ASSIGNMENT
1
A
3
GND
4
Y
5
VCC
© Semiconductor Components Industries, LLC, 2012
Output
A
B
Y
L
L
H
H
L
H
L
H
L
L
L
H
ORDERING INFORMATION
B
2
April, 2022 − Rev. 19
XX MG
G
1
Inputs
A
B
M
The MC74HC1G08 is a high speed CMOS 2−input AND gate
fabricated with silicon gate CMOS technology.
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The MC74HC1G08 output drive current is 1/2 compared to
MC74HC series.
5
SC−88A
DF SUFFIX
CASE 419A
See detailed ordering, marking and shipping information in
the package dimensions section on page 6 of this data
sheet.
1
Publication Order Number:
MC74HC1G08/D
MC74HC1G08
MAXIMUM RATINGS
Symbol
Parameter
Unit
*0.5 to )7.0
*0.5 to +6.5
V
VCC
DC Supply Voltage
VIN
DC Input Voltage
*0.5 to VCC )0.5
V
DC Output Voltage
*0.5 to VCC )0.5
V
VOUT
SC−88A (NLV), TSOP−5
SC−88A, SC−74A
Value
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$20
mA
IOUT
DC Output Source/Sink Current
$12.5
mA
ICC or IGND
TSTG
DC Supply Current per Supply Pin or Ground Pin
Storage Temperature Range
$25
mA
−65 to )150
°C
260
°C
)150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance (Note 1)
SC−88A
SC−74A
377
320
°C/W
PD
Power Dissipation in Still Air at 85°C
SC−88A
SC−74A
332
390
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
ESD Withstand Voltage (Note 2)
Human Body Model
Charged Device Model
2000
1000
V
SC−88A (NLV), TSOP−5
SC−88A, SC−74A
$500
$100
mA
VESD
ILATCHUP
Level 1
Latchup Performance (Note 3)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow per JESD51−7.
2. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115A (Machine Model) be discontinued per JEDEC/JEP172A.
3. Tested to EIA/JESD78 Class II.
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2
MC74HC1G08
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
6.0
V
VIN
DC Input Voltage
0.0
VCC
V
DC Output Voltage
0.0
VCC
V
*55
)125
°C
VOUT
TA
tr , tf
Operating Temperature Range
Input Rise and Fall Time
SC−88A (NLV), TSOP−5
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
Input Rise and Fall Time
SC−88A, SC−74A
VCC = 2.0 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 6.0 V
0
0
0
0
20
20
10
5
ns
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
TA = 255C
VCC
Symbol
Parameter
Test Conditions
−40°C ≤ TA ≤ 85°C
−55°C ≤ TA ≤ 125°C
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
VIH
High−Level Input
Voltage
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.20
−
−
−
−
−
−
−
−
1.5
2.1
3.15
4.20
−
−
−
−
1.5
2.1
3.15
4.20
−
−
−
−
V
VIL
Low−Level Input
Voltage
2.0
3.0
4.5
6.0
−
−
−
−
−
−
−
−
0.5
0.9
1.35
1.80
−
−
−
−
0.5
0.9
1.35
1.80
−
−
−
−
0.5
0.9
1.35
1.80
V
VOH
High−Level Output
Voltage
2.0
3.0
4.5
6.0
1.9
2.9
4.4
5.9
2.0
3.0
4.5
6.0
−
−
−
−
1.9
2.9
4.4
5.9
−
−
−
−
1.9
2.9
4.4
5.9
−
−
−
−
V
4.5
6.0
4.18
5.68
4.31
5.80
−
−
4.13
5.63
−
−
4.08
5.58
−
−
2.0
3.0
4.5
6.0
−
−
−
−
0.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
−
−
−
−
0.1
0.1
0.1
0.1
−
−
−
−
0.1
0.1
0.1
0.1
4.5
6.0
−
−
0.17
0.18
0.26
0.26
−
−
0.33
0.33
−
−
0.40
0.40
VIN = VIH or VIL
IOH = −20 mA
VIN = VIH or VIL
IOH = −2 mA
IOH = −2.6 mA
VOL
Low−Level Output
Voltage
VIN = VIH or VIL
IOL = 20 mA
VIN = VIH or VIL
IOL = 2 mA
IOL = 2.6 mA
V
IIN
Input Leakage
Current
VIN = 6.0 V or
GND
6.0
−
−
$0.1
−
$1.0
−
$1.0
mA
ICC
Quiescent Supply
Current
VIN = VCC or
GND
6.0
−
−
1.0
−
10
−
40
mA
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3
MC74HC1G08
AC ELECTRICAL CHARACTERISTICS
TA = 255C
Symbol
Parameter
Test Conditions
Min
Typ
−40°C ≤ TA ≤ 85°C
Max
Min
−55°C ≤ TA ≤ 125°C
Max
Min
Max
Unit
ns
tPLH,
tPHL
Propagation Delay,
(A or B) to Y
VCC = 5.0 V
CL = 15 pF
−
3.5
15
−
20
−
25
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
CL = 50 pF
−
−
−
−
20
11
8
7
100
27
20
17
−
−
−
−
125
35
25
21
−
−
−
−
155
90
35
26
tTLH,
tTHL
Output Transition
Time
VCC = 5.0 V
CL = 15 pF
−
3
10
−
15
−
20
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
CL = 50 pF
−
−
−
−
25
16
11
9
125
35
25
21
−
−
−
−
155
45
31
26
−
−
−
−
200
60
38
32
CIN
Input Capacitance
−
5
10
−
10
−
10
CPD
Power Dissipation Capacitance (Note 4)
ns
pF
Typical @ 255C, VCC = 5.0 V
10
pF
4. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
MC74HC1G08
OPEN
VCC
Test
Switch
Position
tPLH / tPHL
Open
tTLH / tTHL
(Note 5)
Open
tPLZ / tPZL
VCC
tPHZ / tPZH
GND
GND
RL
DUT
OUTPUT
RT
CL, pF
RL, W
X
See AC Characteristics
Table
X
1k
1k
X − Don’t Care
CL*
*CL includes probe and jig capacitance
RT is ZOUT of pulse generator (typically 50 W)
f = 1 MHz
Figure 3. Test Circuit
tr = 6 ns
tf = 6 ns
90%
90%
VCC
INPUT
Vmi
Vmi
Vmi
Vmi
INPUT
VCC
GND
10%
10%
tPHL
OUTPUT
tPLH
tTLH
VH
VH
VL
VL
tPLH
VH
OUTPUT
VOH
OUTPUT
tPLZ
VOL + VY
VOL
Vmo
tPZH
VOH
VH
~ VCC
Vmo
VOL
tPHL
tTLH
tPZL
Vmo
Vmo
tTHL
GND
OUTPUT
tPHZ
VOH
VOH - VY
Vmo
Vmo
VL
VL
tTHL
~0 V
VOL
Figure 4. Switching Waveforms
Vmo, V
VCC, V
Vmi, V
tPLH, tPHL
tPZL, tPLZ, tPZH, tPHZ
VL, V
VH, V
VY, V
3.0 to 3.6
VCC/2
VCC/2
VCC/2
VOL + 0.1 (VOH − VOL)
VOL + 0.9 (VOH − VOL)
0.3
4.5 to 5.5
VCC/2
VCC/2
VCC/2
VOL + 0.1 (VOH − VOL)
VOL + 0.9 (VOH − VOL)
0.3
5. tTLH and tTHL are measured from 10% to 90% of (VOH − VOL), and 90% to 10% of (VOH − VOL), respectively.
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5
MC74HC1G08
ORDERING INFORMATION
Packages
Specific Device Code
Pin 1 Orientation
(See below)
Shipping†
MC74HC1G08DFT1G
SC−88A
H2
Q2
3000 / Tape & Reel
NLVHC1G08DFT1G*
SC−88A
H2
Q2
3000 / Tape & Reel
MC74HC1G08DFT2G
SC−88A
H2
Q4
3000 / Tape & Reel
MC74HC1G08DFT2G−L22038**
SC−88A
H2
Q4
3000 / Tape & Reel
NLVHC1G08DFT2G*
SC−88A
H2
Q4
3000 / Tape & Reel
MC74HC1G08DTT1G**
TSOP−5
H2
Q4
3000 / Tape & Reel
NLVHC1G08DTT1G*
TSOP−5
H2
Q4
3000 / Tape & Reel
MC74HC1G08DBVT1G
SC−74A
H2
Q4
3000 / Tape & Reel
Device
†For complete information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**Please refer to NLV specifications for this device.
Pin 1 Orientation in Tape and Reel
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−74A
CASE 318BQ
ISSUE B
5
1
SCALE 2:1
5X
DATE 18 JAN 2018
b
0.20 C A B
E1
5
M
4
1
2
E
3
B
0.05
A1
e
D
A
L
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE.
DIM
A
A1
b
c
D
E
E1
e
L
M
TOP VIEW
A
SIDE VIEW
DETAIL A
C
c
SEATING
PLANE
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
0.90
1.10
0.01
0.10
0.25
0.50
0.10
0.26
2.85
3.15
2.50
3.00
1.35
1.65
0.95 BSC
0.20
0.60
0_
10 _
GENERIC
MARKING DIAGRAM*
0.95
PITCH
XXX MG
G
XXX
M
G
2.40
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
5X
1.00
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
5X
0.70
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON66279G
SC−74A
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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