MC74HC4094ADTG

MC74HC4094A 8-Bit Shift and Store Register High−Performance Silicon−Gate CMOS The MC74HC4094A is a high speed CMOS 8−bit serial shift and storage register. This device consists of an 8−bit shift register and latch with 3−state output buffers. Data is shifted on positive clock (CP) transitions. The data in the shift register is transferred to the storage register when the Strobe (STR) input is high. The output buffers are enabled when the Output Enable (OE) input is set high. Two serial outputs (QS1, QS2) are available for cascading multiple devices. www.onsemi.com MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 16 Features 1 • Wide Operating Voltage Range: 2.0 to 6.0 V • Low Power Dissipation: ICC = < 10 mA • In Compliance with the Requirements Defined by JEDEC • • HC4094AG AWLYWW 1 16 Standard No. 7A NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices 16 1 1 A WL, L YY, Y WW, W G, G Typical Applications • Serial−to−Parallel Conversion • Remote Control Storage Register HC 4094A ALYWG G TSSOP−16 DT SUFFIX CASE 948F = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2015 February, 2015 − Rev. 2 1 Publication Order Number: MC74HC4094A/D MC74HC4094A 3 1 1 C2 15 CP EN3 STR QS1 SRG8 3 9 C1/ STR 1 16 VCC QS2 10 D 2 15 OE QP0 4 CP 3 14 QP4 QP1 5 5 QP0 4 13 QP5 5 12 QP6 QP2 6 6 QP1 QP2 6 11 QP7 QP3 7 7 QP3 7 10 QS2 QP4 14 14 GND 8 9 QS1 QP5 13 13 QP6 12 12 QP7 11 11 2 D Figure 1. Pin Assignment 2 4 1D 2D 3 OE 9 10 15 Figure 2. Logic Symbol 2 D 3 CP 1 STR 15 OE Figure 3. IEC Logic Symbol 8 – Stage Shift Register 8 – Bit Storage Register 3 – Stage Outputs QP0 4 QP1 5 QP2 6 QP3 7 QP4 14 QP5 13 Figure 4. Functional Diagram www.onsemi.com 2 QP6 12 QP7 11 QS2 10 QS1 9 MC74HC4094A STAGE 0 D STAGES 1 TO 6 Q D Q D STAGE 7 D Q QS1 CP FF7 CP FF0 Q D CP CP CP latch D D Q Q CP latch CP latch STR OE QP0 QP1 QP2 QP3 QP4 QP5 QP6 Figure 5. Logic Diagram www.onsemi.com 3 QP7 QS2 MC74HC4094A MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 °C SOIC Package† TSSOP Package† Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. †Derating − SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: − 6.1 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V –55 +125 °C 0 0 0 1000 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V www.onsemi.com 4 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC4094A FUNCTIONAL TABLE INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS CP OE STR D QP0 QPn QS1 QS2 ↑ L X X Z Z Q’6 NC ↓ L X X Z Z NC QP7 ↑ H L X NC NC Q’6 NC ↑ H H L L QPn−1 Q’6 NC ↑ H H H H QPn−1 Q’6 NC ↓ H H H NC NC NC QP7 Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF−state NC = no change ↑ = LOW−to−HIGH CP transition ↓ = HIGH−to−LOW CP transition Q’6 = the information in the seventh register stage is transferred to the 8th register stage and QSn output at the positive clock edge CLOCK INPUT CP DATA INPUT D STROBE INPUT STR OUTPUT ENABLE INPUT OE INTERNAL Q’0 FF0 OUTPUT QP0 INTERNAL Q’6 FF6 OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 Z−state Z−state Figure 6. Timing Diagram www.onsemi.com 5 MC74HC4094A DC CHARACTERISTICS Guaranteed Limits Symbol VIH VIL VOH VOL Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage Maximum Low−Level Output Voltage VCC (V) −555C to 255C ≤ 855C ≤ 1255C Unit 2.0 1.5 1.5 1.5 V 3.0 2.1 2.1 2.1 4.5 3.15 3.15 3.15 6.0 4.2 4.2 4.2 2.0 0.5 0.5 0.5 3.0 0.9 0.9 0.9 4.5 1.35 1.35 1.35 6.0 1.8 1.8 1.8 2.0 1.9 1.9 1.9 3.0 2.9 2.9 2.9 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 VIN = VIH or VIL, ⎟IOUT⎟ = 2.4 mA 3.0 2.75 2.7 2.6 VIN = VIH or VIL, ⎟IOUT⎟ = 4 mA 4.5 4.25 4.2 4.1 VIN = VIH or VIL, ⎟IOUT⎟ = 5.2 mA 6.0 5.75 5.7 5.6 VIN = VIH or VIL, ⎟IOUT⎟ ≤ 20 mA 2.0 0.1 0.1 0.1 3.0 0.1 0.1 0.1 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 VIN = VIH or VIL, ⎟IOUT⎟ = 2.4 mA 3.0 0.25 0.3 0.4 VIN = VIH or VIL, ⎟IOUT⎟ = 4 mA 4.5 0.25 0.3 0.4 VIN = VIH or VIL, ⎟IOUT⎟ = 5.2 mA 6.0 0.25 0.3 0.4 Test Conditions VOUT = 0.1 V or VCC – 0.1 V ⎟IOUT⎟ ≤ 20 mA VOUT = 0.1 V or VCC – 0.1 V ⎟IOUT⎟ ≤ 20 mA VIN = VIH or VIL ⎟IOUT⎟ ≤ 20 mA V V V IIN Maximum Input Leakage Current VIN = VCC or GND 6.0 ±0.1 ±1 ±1 mA IOZ Maximum Tri−State Output Leakage Current VIN = VCC or GND VOUT = VCC or GND 6.0 ±0.5 ±5 ±10 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 6.0 4.0 40 80 mA www.onsemi.com 6 MC74HC4094A AC CHARACTERISTICS (tf = tr = 6 ns, CL = 50 pF) Guaranteed Limits Symbol Parameter tPHL, tPLH Maximum Propagation Delay CP to QS1 tPHL, tPLH Maximum Propagation Delay CP to QS2 tPHL, tPLH Maximum Propagation Delay CP to QPn tPHL, tPLH Maximum Propagation Delay STR to QPn tPZH, tPZL Maximum 3−State Output Enable Time OE to QPn tPHZ, tPLZ Maximum 3−State Output Enable Time OE to QPn tTHL, tTLH tW tW tSU Maximum Output Transition Time Minimum Clock Pulse Width High or Low Minimum Strobe Pulse Width High Minimum Set−up Time D to CP ≤ 855C ≤ 1255C Unit ns Test Conditions VCC (V) −555C to 255C Figure 7 2.0 120 150 170 3.0 90 100 110 4.5 30 38 45 6.0 26 33 38 2.0 120 150 170 3.0 90 100 110 4.5 27 34 41 6.0 23 29 35 2.0 120 150 170 3.0 90 100 110 4.5 39 49 59 6.0 33 42 50 2.0 120 150 170 3.0 90 100 110 4.5 36 45 54 6.0 31 38 46 2.0 120 140 160 3.0 80 100 120 4.5 35 44 53 6.0 30 37 45 2.0 100 120 140 3.0 70 90 110 4.5 25 31 38 6.0 21 26 32 2.0 70 90 110 3.0 40 60 80 4.5 18 22 25 6.0 16 19 22 2.0 80 100 120 3.0 50 60 80 4.5 16 20 24 6.0 14 17 20 2.0 80 100 120 3.0 50 60 80 4.5 16 20 24 6.0 14 17 20 2.0 50 65 75 3.0 30 35 45 4.5 10 13 15 6.0 9 11 13 Figure 7 Figure 7 Figure 8 Figure 9 Figure 9 Figure 7 Figure 7 Figure 8 Figure 10 www.onsemi.com 7 ns ns ns ns ns ns ns ns ns MC74HC4094A AC CHARACTERISTICS (tf = tr = 6 ns, CL = 50 pF) Guaranteed Limits Symbol tSU th th fMAX Parameter Minimum Set−up Time CP to STR Minimum Hold Time D to CP Minimum Hold Time CP to STR Minimum Clock Pulse Frequency Test Conditions VCC (V) −555C to 255C Figure 8 Figure 10 Figure 8 Figure 7 ≤ 855C ≤ 1255C Unit ns 2.0 100 125 150 3.0 60 75 90 4.5 20 25 30 6.0 17 21 26 2.0 3 3 3 3.0 3 3 3 4.5 3 3 3 6.0 3 3 3 2.0 0 0 0 3.0 0 0 0 4.5 0 0 0 6.0 0 0 0 2.0 6 5 4 3.0 18 14 12 4.5 30 24 20 6.0 35 28 24 ns ns MHz Cin Maximum Input Capacitance − 10 10 10 pF Cout Maximum Output Capacitance − 15 15 15 pF CPD Power Dissipation Capacitance (Note 2) − 140 140 140 pF 2. CPD is defined as the value of the IC’s equivalent capacitance from which the operating current can be calculated from: ICC(operating) ≈ CPD x VCC x fIN x NSW where NSW = total number of outputs switching and fIN = switching frequency. www.onsemi.com 8 MC74HC4094A AC WAVEFORMS 1/fMAX CP Input CP Input 50% tw tPLH QPn, QS1 Output tsu tPHL STR Input 50% 50% tPHL tPLH tPLH QPn Output 50% tTLH tPHL 50% tTHL Figure 8. Waveforms showing the strobe (STR) to output (QPn) propagation delays, the strobe pulse width, the clock set−up and hold times for the strobe input. Figure 7. Waveforms showing the clock (CP) to output (QPn, QS1, QS2) propagation delays, the clock pulse width and the maximum clock frequency. tf th tW tTHL tTLH QS2 Output 50% tr 90% OE Input 50% 10% ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ tsu tPZL tPLZ QPn Output: Low − to − Off Off − to − Low D Input 50% 10% tPZH tPHZ 90% QPn Output: High − to − Off Off − to − High Outputs Disabled Outputs Enabled tsu th th 50% QPn, QS1, QS2 Output 50% Outputs Enabled 50% CP Input 50% The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 9. Waveforms showing the 3−state enable and disable times for input OE. Figure 10. Waveforms showing the data set−up and hold times for the data input. www.onsemi.com 9 MC74HC4094A TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kW CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 11. AC Characteristics Load Circuits ORDERING INFORMATION Package Shipping† MC74HC4094ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HC4094ADR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel MC74HC4094ADTG TSSOP−16 (Pb−Free) 96 Units / Rail MC74HC4094ADTR2G TSSOP−16 (Pb−Free) 2500 / Tape & Reel NLVHC4094BDTR2G* TSSOP−16 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE B 16 DATE 19 OCT 2006 1 SCALE 2:1 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 16 XXXX XXXX ALYW 1 1 0.65 PITCH 16X 0.36 DOCUMENT NUMBER: DESCRIPTION: 16X 1.26 98ASH70247A TSSOP−16 DIMENSIONS: MILLIMETERS XXXX A L Y W G or G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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