MC74HC4316AN

MC74HC4316A Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HC4316A utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF−channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power−supply range (from VCC to VEE). The HC4316A is similar in function to the metal−gate CMOS MC14016 and MC14066, and to the High−Speed CMOS HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal−gate CMOS analog switches. Logic−level translators are provided so that the On/Off Control and Enable logic−level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active−low) is high, all four analog switches are turned off. SOIC−16 D SUFFIX CASE 751B PIN ASSIGNMENT XA 1 16 YA 2 15 YB 3 14 XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE 4 13 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD 5 12 YD 6 11 YC 7 10 XC GND 8 9 VEE Features • • • • • • • • • • Logic−Level Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog Power−Supply Voltage Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power−Supply Voltage Range (VCC − GND) = 2.0 V to 6.0 V, Independent of VEE Improved Linearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable* These Devices are Pb−Free, Halogen Free and are RoHS Compliant MARKING DIAGRAM 16 HC4316AG AWLYWW 1 A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping† MC74HC4316ADR2G SOIC−16 (Pb−Free) 2500/ Tape&Reel NLV74HC4316ADR2G* SOIC−16 (Pb−Free) 2500/ Tape&Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev. 9 1 Publication Order Number: MC74HC4316A/D MC74HC4316A FUNCTION TABLE Inputs Enable On/Off Control State of Analog Switch L L H H L X On Off Off X = Don’t Care. XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL ENABLE 1 15 ANALOG SWITCH 2 ANALOG SWITCH 3 YA LEVEL TRANSLATOR 4 5 YB ANALOG OUTPUTS/INPUTS LEVEL TRANSLATOR 10 6 ANALOG SWITCH 11 ANALOG SWITCH 12 YC LEVEL TRANSLATOR 13 14 PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND ≥ VEE YD LEVEL TRANSLATOR 7 ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD Figure 1. Logic Diagram PLOTTER PROGRAMMABLE POWER SUPPLY - MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE Figure 2. On Resistance Test Set−Up http://onsemi.com 2 MC74HC4316A MAXIMUM RATINGS Symbol Parameter Value Unit –0.5 to +7.0 –0.5 to +14.0 V Negative DC Supply Voltage (Ref. to GND) –7.0 to +0.5 V Analog Input Voltage VEE – 0.5 to VCC + 0.5 V VCC Positive DC Supply Voltage VEE VIS Vin DC Input Voltage (Ref. to GND) I (Ref. to GND) (Ref. to VEE) –0.5 to VCC + 0.5 V ±25 mA 500 mW – 65 to + 150 °C 260 °C DC Current Into or Out of Any Pin PD Power Dissipation in Still Air SOIC Package* Tstg Storage Temperature TL Lead Temperature, 1 mm from Case for 10 Seconds) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *Derating − SOIC Package: –7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Min Max Unit VCC Positive DC Supply Voltage (Ref. to GND) 2.0 6.0 V VEE Negative DC Supply Voltage (Ref. to GND) –6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Ref. to GND) GND VCC V − 1.2 V –55 +125 °C 0 0 0 0 1000 600 500 400 ns VIO* Parameter Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted Guaranteed Limit VCC V –55 to 25°C ≤ 85°C ≤ 125°C Unit VIH Minimum High−Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Control or Enable Inputs Vin = VCC or GND VEE = –6.0 V 6.0 ±0.1 ±1.0 ±1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V VEE = GND VEE = –6.0 6.0 6.0 2 4 20 40 40 160 Symbol Parameter Test Conditions http://onsemi.com 3 mA MC74HC4316A DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) Guaranteed Limit VCC V VEE V –55 to 25°C Vin = VIH VIS = VCC to VEE IS ≤ 2.0 mA (Figure 2) 2.0* 45 4.5 6.0 0.0 0.0 −4.5 −6.0 − 160 90 90 − 200 110 110 − 240 130 130 Vin = VIH VIS = VCC or VEE (Endpoints) IS ≤ 2.0 mA (Figure 2) 2.0 4.5 4.5 6.0 0.0 0.0 −4.5 −6.0 − 90 70 70 − 115 90 90 − 140 105 105 Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC − VEE) IS ≤ 2.0 mA 2.0 4.5 4.5 6.0 0.0 0.0 –4.5 –6.0 − 20 15 15 − 25 20 20 − 30 25 25 W Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) 6.0 –6.0 0.1 0.5 1.0 mA Ion Maximum On−Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or VEE (Figure 4) 6.0 –6.0 0.1 0.5 1.0 mA Symbol Ron DRon Parameter Maximum “ON” Resistance Test Conditions ≤ 85°C ≤ 125°C Unit W *At supply voltage (VCC − VEE) approaching 2.0 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage operation, it is recommended that these devices only be used to control digital signals. AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) VCC V –55 to 25°C ≤ 85°C ≤ 125°C 2.0 4.5 6.0 40 6 5 50 8 7 60 9 8 Unit ns tPLZ, tPHZ Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 130 40 30 160 50 40 200 60 50 ns tPZL, tPZH Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 140 40 30 175 50 40 250 60 50 ns − 10 10 10 pF − − 35 1.0 35 1.0 35 1.0 C Maximum Capacitance ON/OFF Control and Enable Inputs Control Input = GND Analog I/O Feedthrough Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* *Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . http://onsemi.com 4 15 pF MC74HC4316A ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V VEE V Limit* 25°C fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads –3 dB RL = 50 W, CL = 10 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 150 160 160 MHz fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 dB fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –40 –40 –40 Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 30 65 100 RL = 10 kW, CL = 10 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 60 130 200 fin  Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –70 –70 –70 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –80 –80 –80 Symbol Parameter Test Conditions BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 5) Off–Channel Feedthrough Isolation (Figure 6) − − − THD Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured − THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 Unit mVPP dB % 2.25 4.50 6.00 –2.25 –4.50 –6.00 0.10 0.06 0.04 MC74HC4316A VCC 16 VEE VCC VCC 16 A A VCC OFF VCC N/C ON O/I VEE VIL VIH 7 8 9 SELECTED CONTROL INPUT 7 8 9 SELECTED CONTROL INPUT VEE VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 4. Maximum On Channel Leakage Current, Test Set−Up VIS VCC VCC 16 fin VCC RL 16 TO dB METER ON 0.1 mF VCC RL RL 7 8 9 SELECTED CONTROL INPUT VEE TO dB METER OFF 0.1 mF CL* RL 7 8 9 fin CL* SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On−Channel Bandwidth Test Set−Up Figure 6. Off−Channel Feedthrough Isolation, Test Set−Up VCC 16 TEST POINT ON/OFF RL 7 8 9 VEE RL VCC CL* ANALOG IN SELECTED CONTROL INPUT 50% GND tPLH CONTROL ANALOG OUT tPHL 50% *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, Control to Analog Out, Test Set−Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 6 MC74HC4316A VCC 16 ANALOG I/O tr ANALOG O/I TEST POINT ON tf VCC ENABLE 50% GND CONTROL 50 pF* tPZL 7 8 9 SELECTED CONTROL INPUT VCC tPLZ HIGH IMPEDANCE 50% ANALOG OUT tPZH tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE *Includes all probe and jig capacitance. Figure 9. Propagation Delay Test Set−Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS 1 POSITIONWHEN TESTING tPHZ AND tPZH 2 POSITIONWHEN TESTING tPLZ AND tPZL 1 VCC RL 2 VCC 0.1 mF 1 kW 16 1 RL ON CL* TEST POINT ON/OFF 2 16 fin VCC ANALOG I/O 50 pF* TEST POINT OFF CONTROL OR ENABLE 7 8 9 8 9 VEE *Includes all probe and jig capacitance. RL CL* VCC SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set−Up Figure 12. Crosstalk Between Any Two Switches, Test Set−Up (Adjacent Channels Used) VCC A VIS VCC 16 N/C ON/OFF 10 mF N/C VOS 16 fin ON RL 7 8 9 VEE SELECTED CONTROL INPUT 7 8 9 VEE CONTROL SELECTED CONTROL INPUT CL* TO DISTORTION METER VCC *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set−Up Figure 14. Total Harmonic Distortion, Test Set−Up http://onsemi.com 7 MC74HC4316A APPLICATIONS INFORMATION 0 -10 FUNDAMENTAL FREQUENCY -20 dBm -30 -40 -50 DEVICE -60 SOURCE -70 -80 -90 - 100 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak−to−peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn−on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORBs (MOSORB® is an acronym for high current surge protectors). MOSORBs are fast turn−on devices ideally suited for precise dc protection with no inherent wear out mechanism. The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is 12 V. VCC VCC = 6 V 16 +6V ANALOG I/O ON ANALOG O/I +6V SELECTED CONTROL INPUT VEE 8 16 Dx SELECTED CONTROL INPUT Dx Dx +6V ON -6 V -6 V VCC VCC Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) VEE VEE ENABLE CONTROL INPUTS (VCC OR GND) -6 V Figure 16. Figure 17. Transient Suppressor Application http://onsemi.com 8 MC74HC4316A VCC = 5 V +5 V 16 ANALOG SIGNALS 16 ANALOG SIGNALS ANALOG SIGNALS ANALOG SIGNALS R* R* R* R* R* HC4316A 7 5 6 14 15 TTL HCT BUFFER VEE = 0 TO -6 V 5 LSTTL/ NMOS ENABLE AND CONTROL 9 INPUTS 8 HC4016A 6 14 VEE = 0 TO -6 V CONTROL INPUTS 9 15 7 R* = 2 TO 10 kW a. Using Pull−Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VCC = 12 V R1 12 V POWER SUPPLY GND = 6 V R2 VEE = 0 V R1 = R2 VCC 12 VPP ANALOG INPUT SIGNAL R3 C 1 OF 4 SWITCHES ANALOG OUTPUT SIGNAL 12 V 0 R4 R1 = R2 R3 = R4 VEE Figure 19. Switching a 0−to−12 V Signal Using a Single Power Supply (GND ≠ 0 V) CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 mF 1 2 3 4 CONTROL INPUTS Figure 20. 4−Input Multiplexer Figure 21. Sample/Hold Amplifier MOSORB is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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