MC74HCT241ADWG

MC74HCT241A Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HCT241A is identical in pinout to the LS241. This device may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line driver/line receiver designed to be used with 3−state memory address drivers, clock drivers, and other bus−oriented systems. The device has non−inverted outputs and two output enables. Enable A is active−low and Enable B is active−high. The HCT241A is similar in function to the HCT244. See also HCT240. Features • • • • • • • • Output Drive Capability: 15 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 118 FETs or 29.5 Equivalent Gates Pb−Free Packages are Available* PDIP−20 N SUFFIX CASE 738 1 1 SOIC−20W DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E 1 ORDERING INFORMATION See detailed ordering, shipping information, and marking information in the package dimensions section on page 6 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 8 1 Publication Order Number: MC74HCT241A/D MC74HCT241A LOGIC DIAGRAM A1 A2 A3 A4 2 PIN ASSIGNMENT 18 4 16 6 14 8 12 YA1 YA2 YA3 YA4 DATA INPUTS B1 B2 B3 B4 11 9 13 7 15 5 17 3 1 OUTPUT ENABLE A ENABLES ENABLE B 19 YB1 NONINVERTING OUTPUTS YB2 YB3 YB4 PIN 20 = VCC PIN 10 = GND ENABLE A 1 20 VCC A1 2 19 ENABLE B YB4 3 18 YA1 A2 4 17 B4 YB3 5 16 YA2 A3 6 15 B3 YB2 7 14 YA3 A4 8 13 B2 YB1 9 12 YA4 GND 10 11 B1 FUNCTION TABLE Inputs Enable A L L H Output A YA L H X L H Z Inputs Enable B H H L Output B YB L H X L H Z Z = high impedance X = don’t care http://onsemi.com 2 MC74HCT241A MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 V V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 35 mA ICC DC Supply Current, VCC and GND Pins ± 75 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† 750 500 mW Tstg Storage Temperature – 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 300 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) Min Max Unit 4.5 5.5 V 0 VCC V – 55 + 125 _C 0 500 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C 4.5 5.5 2 2 2 2 2 2 Symbol VIH Parameter Minimum High−Level Input Voltage Test Conditions Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA VIL Maximum Low−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA 4.5 5.5 0.8 0.8 0.8 0.8 08 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH or VIL |Iout| v 20 μA 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 V Vin = VIH or VIL |Iout| v 6 mA 4.5 3.98 3.84 3.7 Vin = VIH or VIL |Iout| v 20 μA 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| v 6 mA 4.5 0.26 0.33 0.4 VOL Maximum Low−Level Output Voltage Unit V V Iin Maximum Input Leakage Current Vin = VCC or GND 5.5 ± 0.1 ± 1.0 ± 1.0 μA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 5.5 ± 0.5 ± 5.0 ± 10 μA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 μA 5.5 4 40 160 μA ΔICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 μA 1. Total Supply Current = ICC + ΣΔICC. http://onsemi.com 3 5.5 ≥ −55_C 25_C to 125_C 2.9 2.4 mA MC74HCT241A AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter – 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) 23 29 35 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 30 38 45 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) 26 33 39 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 12 15 18 ns Cin Maximum Input Capacitance 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD 55 Power Dissipation Capacitance (Per Enabled Output)* pF * Used to determine the no−load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . SWITCHING WAVEFORMS 3V ENABLE A 1.3 V GND 3V tr tf INPUT A OR B ENABLE B GND 3V 2.7 V 1.3 V 0.3 V tPZL OUTPUT Y tPHL 90% 1.3 V 10% HIGH IMPEDANCE 1.3 V tPZH tTLH tTHL OUTPUT Y 10% VOL 90% VOH tPHZ 1.3 V Figure 1. HIGH IMPEDANCE Figure 2. TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST tPLZ GND tPLH OUTPUT YA OR YB 1.3 V OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance 1 kΩ CL* CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. *Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit http://onsemi.com 4 MC74HCT241A LOGIC DETAIL TO THREE OTHER “A” BUFFERS TO THREE OTHER “B” BUFFERS TWO OF 8 BUFFERS VCC INPUT A YA VCC INPUT B YB ENABLE A OUTPUT ENABLES ENABLE B http://onsemi.com 5 MC74HCT241A ORDERING INFORMATION Package Shipping† MC74HCT241ANG PDIP−20 (Pb−Free) 18 Units / Rail MC74HCT241ADWG SOIC−20 (Pb−Free) 38 Units / Rail MC74HCT241ADWR2G SOIC−20 (Pb−Free) 1000 / Tape & Reel MC74HCT241ADTG TSSOP−20* 75 Units / Rail MC74HCT241ADTR2G TSSOP−20* 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb−Free. MARKING DIAGRAMS PDIP−20 SOIC−20W 20 20 TSSOP−20 20 HCT 241A ALYWG G HCT241A AWLYYWWG MC74HCT241AN AWLYYWWG 1 1 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−20 WB CASE 751D−05 ISSUE H DATE 22 APR 2015 SCALE 1:1 A 20 q X 45 _ M E h 0.25 H NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 1 10 20X B b 0.25 M T A S B DIM A A1 b c D E e H h L q S L A 18X e SEATING PLANE A1 c T GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 20 20X 20X 1.30 0.52 20 XXXXXXXXXXX XXXXXXXXXXX AWLYYWWG 11 1 11.00 1 XXXXX A WL YY WW G 10 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ 98ASB42343B SOIC−20 WB = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP−20 WB CASE 948E ISSUE D DATE 17 FEB 2016 SCALE 2:1 20X 0.15 (0.006) T U 2X L K REF 0.10 (0.004) S L/2 20 M T U S V ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ K K1 S J J1 11 B SECTION N−N −U− PIN 1 IDENT 0.25 (0.010) N 1 10 M 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. N F DETAIL E −W− C G D H DETAIL E 0.100 (0.004) −T− SEATING PLANE DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 7.06 XXXX XXXX ALYWG G 1 0.65 PITCH 16X 0.36 16X 1.26 DOCUMENT NUMBER: 98ASH70169A DESCRIPTION: TSSOP−20 WB A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DIMENSIONS: MILLIMETERS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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