MC74HCT573A

MC74HCT573A Octal 3−State Noninverting Transparent Latch with LSTTL Compatible Inputs High−Performance Silicon−Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High−Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high−impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT573A is identical in function to the HCT373A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout. http://onsemi.com MARKING DIAGRAMS 20 PDIP−20 N SUFFIX CASE 738 1 20 MC74HCT573AN AWLYYWW 1 20 20 1 SOIC WIDE−20 DW SUFFIX CASE 751D 1 TSSOP−20 DT SUFFIX CASE 948E HCT573A AWLYYWW 20 HCT 573A ALYW 1 • • • • • • • w Output Drive Capability: 15 LSTTL Loads TTL/NMOS−Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 10 μA In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 234 FETs or 58.5 Equivalent Gates — Improved Propagation Delays — 50% Lower Quiescent Power These devices are available in Pb−free package(s). Specifications herein apply to both standard and Pb−free devices. Please see our website at www.onsemi.com for specific Pb−free orderable part numbers, or contact your local ON Semiconductor sales office or representative. 20 1 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC74HCT573AN MC74HCT573ADW MC74HCT573ADT MC74HCT573ADTR2 Package PDIP−20 SOIC−WIDE TSSOP−20 TSSOP−20 Shipping 1440 / Box 38 / Rail 1000 / Reel 75 / Rail 2500 / Reel MC74HCT573ADWR2 SOIC−WIDE © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 11 1 Publication Order Number: MC74HCT573A/D MC74HCT573A LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS PIN ASSIGNMENT OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LATCH ENABLE FUNCTION TABLE Inputs Output Enable L L L H Latch Enable H H L X D H L X X Output Q H L No Change Z X = Don’t Care Z = High Impedance ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Design Criteria Value 58.5 1.5 5.0 Units ea ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product μW pJ 0.0075 *Equivalent to a two−input NAND gate. http://onsemi.com 2 MC74HCT573A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î ÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎ Î ÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î ÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎ Î Î Î ÎÎ Î Î Î ÎÎ Î Î ÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î ÎÎ Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î ÎÎ Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Î Î Î Î ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎ Î Î Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎ Î Î ÎÎ Î Î ÎÎ Î Î Î ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Î ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎ Î ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* Symbol VCC Vin Iin Vout Iout PD Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) – 0.5 to + 7.0 – 0.5 to VCC + 0.5 – 0.5 to VCC + 0.5 ± 20 ± 25 ± 50 750 500 450 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP† SOIC Package† TSSOP Package† mW Tstg TL Storage Temperature – 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, TSSOP or SOIC Package) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: −6.1 mW/°C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎ Î Î Î Î ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î VCC TA DC Supply Voltage (Referenced to GND) 4.5 0 5.5 V V Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC 500 – 55 0 + 125 _C ns Symbol Parameter Min Max Unit DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit v 85_C 2.0 2.0 0.8 0.8 4.4 5.4 Symbol VIH VIL Parameter Test Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 – 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4 v 125_C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 Unit V V V Minimum High−Level Input Voltage Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA Vout = 0.1 V or VCC – 0.1 V |Iout| v 20 μA Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 6.0 mA Vin = VIH or VIL |Iout| v 20 μA Vin = VIH or VIL |Iout| v 6.0 mA Maximum Low−Level Input Voltage VOH Minimum High−Level Output Voltage 3.98 0.1 0.1 3.84 0.1 0.1 VOL Maximum Low−Level Output Voltage V 0.26 0.33 Iin Maximum Input Leakage Current Maximum Three−State Leakage Current Vin = VCC or GND ± 0.1 ± 0.5 ± 1.0 ± 5.0 ± 1.0 ± 10 μA μA IOZ Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout v 0 μA ICC Maximum Quiescent Supply Current (per Package) 5.5 4.0 40 160 μA ΔICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 μA ≥ – 55_C 2.9 25_C to 125_C 2.4 5.5 mA NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). http://onsemi.com 3 ÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î Î Î ÎÎÎ ÎÎ Î Î Î Î Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î Î ÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ Î Î Î Î Î ÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ * Used to determine the no −load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎ Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ Î Î ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î ÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ Î Î ÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î Î ÎÎÎ ÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Î ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Symbol TPLZ, TPHZ tPLH, tPHL tTLH, tTHL tTZL, tTZH Cout tPLH tPHL Cin Maximum Three−State Output Capacitance (Output in High−Impedance State) Maximum Input Capacitance Maximum Output Transition Time, any Output (Figures 1 and 5) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay, Input D to Output Q (Figures 1 and 5) Parameter TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Symbol tr, tf tsu CPD tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Latch Enable Minimum Hold Time, Latch Enable to Input D Minimum Setup Time, Input D to Latch Enable Power Dissipation Capacitance (Per Enabled Output)* Parameter http://onsemi.com MC74HCT573A 4 Fig. 1 2 4 4 – 55 to 25_C Min 5.0 15 10 Max 500 – 55 to 25_C 15 10 12 28 28 30 30 Guaranteed Limit Typical @ 25°C, VCC = 5.0 V Min 5.0 Guaranteed Limit 19 13 v 85_C v 85_C Max 500 15 10 15 35 35 38 38 48 Min 5.0 22 15 v 125_C v 125_C 15 10 18 42 42 45 45 Max 500 Unit Unit pF pF pF ns ns ns ns ns ns ns ns ns MC74HCT573A SWITCHING WAVEFORMS 3.0 V tr INPUT D tPLH Q tTLH 2.7 V 1.3 V 0.3 V 90% 1.3 V 10% tPHL tf 3.0 V GND LATCH ENABLE 1.3 V GND tw tPLH tTHL Q 1.3 V tPHL Figure 1. Figure 2. OUTPUT ENABLE 3.0 V 1.3 V tPZL tPLZ 10% 90% GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE INPUT D 1.3 V tSU LATCH ENABLE VALID 3.0 V GND th 3.0 V GND Q 1.3 V tPZH tPHZ 1.3 V Q 1.3 V Figure 3. Figure 4. TEST POINT OUTPUT DEVICE UNDER TEST C L* D0 D1 D2 *Includes all probe and jig capacitance D3 D4 D5 CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. D6 D7 2 3 4 5 6 7 8 9 EXPANDED LOGIC DIAGRAM D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE 11 1 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Figure 5. Test Circuit TEST POINT OUTPUT DEVICE UNDER TEST 1 kΩ C L* *Includes all probe and jig capacitance LATCH ENABLE OUTPUT ENABLE Figure 6. Test Circuit http://onsemi.com 5 MC74HCT573A PACKAGE DIMENSIONS PDIP−20 N SUFFIX PLASTIC DIP PACKAGE CASE 738−03 ISSUE E 11 − A− 20 1 B 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15_ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 −T− SEATING PLANE K E G F D 20 PL N J 0.25 (0.010) M 20 PL M 0.25 (0.010) TA M M TB M SO−20 DW SUFFIX CASE 751D−05 ISSUE F D A 11 X 45 _ q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H M B M 20 10X 0.25 E 1 10 20X B 0.25 M B TA S B S A e SEATING PLANE h 18X A1 T C http://onsemi.com 6 L MC74HCT573A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE A M 20X K REF TU 0.15 (0.006) T U S 0.10 (0.004) S V S 2X L/2 20 11 L PIN 1 IDENT 1 10 B − U− J J1 N 0.15 (0.006) T U S A −V− N F C D 0.100 (0.004) −T− SEATING PLANE G H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 7 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SECTION N−N M DETAIL E DETAIL E K K1 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ −W− MC74HCT573A/D