MC74LVXT4066
Quad Analog Switch/
Multiplexer/Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVXT4066 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
OFF−channel leakage current. This bilateral switch/multiplexer/
demultiplexer controls analog and digital voltages that may vary
across the full power−supply range (from VCC to GND).
The LVXT4066 is identical in pinout to the metal−gate CMOS
MC14066 and the high−speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
resistances (RON) are much more linear over input voltage than RON
of metal−gate CMOS analog switches.
The ON/OFF control inputs are compatible with standard LSTTL
outputs. The input protection circuitry on this device allows
overvoltage tolerance on the ON/OFF control inputs, allowing the
device to be used as a logic−level translator from 3.0 V CMOS logic to
5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic
while operating at the higher−voltage power supply.
The MC74LVXT4066 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVXT4066 to be used to interface 5.0 V circuits to
3.0 V circuits.
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SOIC−14 NB
D SUFFIX
CASE 751A
PIN ASSIGNMENT
XA
1
14
YA
2
13
3
12
4
11
VCC
A ON/OFF
CONTROL
D ON/OFF
CONTROL
XD
5
10
YD
6
9
YC
7
8
XC
YB
XB
B ON/OFF
CONTROL
C ON/OFF
CONTROL
GND
(Top View)
Features
•
•
•
•
•
•
•
•
•
TSSOP−14
DT SUFFIX
CASE 948G
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 6.0 V
Analog Input Voltage Range (VCC − GND) = 2.0 to 6.0 V
Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
Low Noise
These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
14
LVXT4066G
AWLYWW
1
SOIC−14 NB
14
LVXT
4066
ALYWG
G
1
TSSOP−14
LVXT4066
A
WL, L
Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2017 − Rev. 5
1
Publication Order Number:
MC74LVXT4066/D
MC74LVXT4066
LOGIC DIAGRAM
XA
A ON/OFF CONTROL
XB
B ON/OFF CONTROL
XC
C ON/OFF CONTROL
XD
D ON/OFF CONTROL
1
2
FUNCTION TABLE
YA
On/Off Control
Input
State of
Analog Switch
L
H
Off
On
13
4
3
YB
5
ANALOG
OUTPUTS/INPUTS
8
9
YC
6
11
10
YD
12
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14 = VCC
PIN 7 = GND
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
VCC
Positive DC Supply Voltage (Referenced to GND)
VIS
Analog Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
Vin
Digital Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
−20
mA
500
450
mW
–65 to +150
_C
260
_C
I
DC Current Into or Out of Any Pin
PD
Power Dissipation in Still Air,
Tstg
Storage Temperature
SOIC Package†
TSSOP Package†
TL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any
of these limits are exceeded, device functionality should not be assumed, damage may occur
and reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance
circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
I/O pins must be connected to
a properly terminated line or bus.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
Positive DC Supply Voltage (Referenced to GND)
2.0
5.5
V
VIS
Analog Input Voltage (Referenced to GND)
GND
VCC
V
Vin
Digital Input Voltage (Referenced to GND)
GND
VCC
V
VIO*
Static or Dynamic Voltage Across Switch
−
1.2
V
–55
+85
_C
0
0
100
20
ns/V
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10)
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may
contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
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2
MC74LVXT4066
DC ELECTRICAL CHARACTERISTIC − Digital Section (Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
Guaranteed Limit
VCC
V
–55 to 25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Voltage
ON/OFF Control Inputs
(Note 1)
Ron = Per Spec
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
VIL
Maximum Low−Level Voltage
ON/OFF Control Inputs
(Note 1)
Ron = Per Spec
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
Iin
Maximum Input Leakage Current
ON/OFF Control Inputs
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND VIO = 0 V
5.5
4.0
40
160
mA
1. Specifications are for design target only. Not final specification limits.
DC ELECTRICAL CHARACTERISTICS − Analog Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Ron
Parameter
Maximum “ON” Resistance
VCC
V
–55 to
25_C
v 85_C
v 125_C
Unit
Vin = VIH
VIS = VCC to GND
IS v 2.0 mA (Figures 1, 2)
2.0†
3.0
4.5
5.5
−
40
25
20
−
45
28
25
−
50
35
30
W
Vin = VIH
VIS = VCC or GND (Endpoints)
IS v 2.0 mA (Figures 1, 2)
2.0
3.0
4.5
5.5
−
30
25
20
−
35
28
25
−
40
35
30
Test Conditions
DRon
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC − GND)
IS v 2.0 mA
3.0
4.5
5.5
15
10
10
20
12
12
25
15
15
W
Ioff
Maximum Off−Channel Leakage
Current, Any One Channel
Vin = VIL
VIO = VCC or GND
Switch Off (Figure 3)
5.5
0.1
0.5
1.0
mA
Ion
Maximum On−Channel Leakage
Current, Any One Channel
Vin = VIH
VIS = VCC or GND
(Figure 4)
5.5
0.1
0.5
1.0
mA
†At supply voltage (VCC) approaching 2 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage
operation, it is recommended that these devices only be used to control digital signals.
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3
MC74LVXT4066
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Parameter
Symbol
Guaranteed Limit
VCC
V
–55 to 25_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
3.0
4.5
5.5
4.0
3.0
1.0
1.0
6.0
5.0
2.0
2.0
8.0
6.0
2.0
2.0
ns
tPLZ,
tPHZ
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)
2.0
3.0
4.5
5.5
30
20
15
15
35
25
18
18
40
30
22
20
ns
tPZL,
tPZH
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)
2.0
3.0
4.5
5.5
20
12
8.0
8.0
25
14
10
10
30
15
12
12
ns
ON/OFF Control Input
−
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
−
−
35
1.0
35
1.0
35
1.0
C
Maximum Capacitance
Typical @ 25°C, VCC = 5.0 V
CPD
15
Power Dissipation Capacitance (Per Switch) (Figure 13)*
pF
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol
BW
−
−
−
THD
Parameter
Test Conditions
VCC
V
Limit*
25_C
Unit
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 5)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter Reads –3 dB
RL = 50 W, CL = 10 pF
4.5
5.5
150
160
MHz
Off−Channel Feedthrough Isolation
(Figure 6)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
4.5
5.5
−50
−50
dB
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
4.5
5.5
−37
−37
Vin v 1 MHz Square Wave (tr = tf = 3 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 W, CL = 50 pF
4.5
5.5
100
200
RL = 10 kW, CL = 10 pF
4.5
5.5
50
100
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
4.5
5.5
–70
–70
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
4.5
5.5
–80
–80
Feedthrough Noise, Control to Switch
(Figure 7)
Crosstalk Between Any Two Switches
(Figure 12)
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kW, CL = 50 pF
THD = THDMeasured − THDSource
VIS = 4.0 VPP sine wave
VIS = 5.0 VPP sine wave
*Guaranteed limits not tested. Determined by design and verified by qualification.
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4
mVPP
dB
%
4.5
5.5
0.10
0.06
MC74LVXT4066
400
250
350
Is = 1mA
200
-55°C
300
Ron (Ohms)
Ron (Ohms)
25°C
150
Is = 5mA
100
Is = 9mA
250
200
85°C
150
125°C
100
50
50
0
Is = 15mA
0
0.5
1.5
1
2
0
2.5
0
0.5
1.5
1
Vin (Volts)
2
2.5
Vin (Volts)
Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C
Figure 1b. Typical On Resistance, VCC = 2.0 V
35
25
30
20
20
Ron (Ohms)
Ron (Ohms)
25
125°C
85°C
25°C
-55°C
15
10
125°C
85°C
25°C
-55°C
15
10
5
5
0
0
2
1
3
0
4
0
1
Vin (Volts)
3
2
4
Vin (Volts)
Figure 1c. Typical On Resistance, VCC = 3.0 V
Figure 1d. Typical On Resistance, VCC = 4.5 V
18
PLOTTER
16
125°C
85°C
25°C
14
Ron (Ohms)
12
10
-55°C
8
PROGRAMMABLE
POWER
SUPPLY
-
MINI COMPUTER
+
DC ANALYZER
VCC
DEVICE
UNDER TEST
6
4
2
ANALOG IN
COMMON OUT
0
0
1
2
3
4
5
6
GND
Vin (Volts)
Figure 2. On Resistance Test Set−Up
Figure 1e. Typical On Resistance, VCC = 5.5 V
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5
5
MC74LVXT4066
VCC
VCC
VCC
VCC
14
GND
14
A
A
VCC
OFF
7
SELECTED
CONTROL
INPUT
VIL
7
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
VCC
VIS
14
VIH
VOS
14
ON
0.1mF
CL*
7
SELECTED
CONTROL
INPUT
Figure 4. Maximum On Channel Leakage Current,
Test Set−Up
VOS
VCC
fin
N/C
ON
GND
SELECTED
CONTROL
INPUT
fin
dB
METER
OFF
0.1mF
CL*
RL
dB
METER
SELECTED
CONTROL
INPUT
VCC
7
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On−Channel Bandwidth
Test Set−Up
VCC
VCC/2
Figure 6. Off−Channel Feedthrough Isolation,
Test Set−Up
VCC/2
14
RL
RL
OFF/ON
VOS
IS
VCC
CL*
VIH
VIL
Vin ≤ 1 MHz
tr = tf = 3 ns
7
ANALOG IN
SELECTED
CONTROL
INPUT
50%
GND
tPHL
tPLH
CONTROL
50%
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
Figure 8. Propagation Delays, Analog In to
Analog Out
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6
MC74LVXT4066
VCC
tr
tf
14
ANALOG IN
ANALOG OUT
ON
TEST
POINT
VCC
90%
50%
10%
CONTROL
GND
CL*
7
SELECTED
CONTROL
INPUT
tPZL
tPLZ
HIGH
IMPEDANCE
50%
VIH
ANALOG
OUT
tPZH
10%
VOL
90%
VOH
tPHZ
50%
HIGH
IMPEDANCE
*Includes all probe and jig capacitance.
Figure 9. Propagation Delay Test Set−Up
Figure 10. Propagation Delay, ON/OFF Control
to Analog Out
VIS
1
POSITIONWHEN
TESTING tPHZ AND tPZH
VCC
2
POSITIONWHEN
TESTING tPLZ AND tPZL
1
14
RL
2
VCC
VCC
fin
1
TEST
POINT
ON/OFF
2
0.1 mF
1 kW
14
OFF
VIH OR VIL
CL*
RL
RL
VIH
VIL
VOS
ON
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
CL*
VCC/2
RL
CL*
VCC/2
7
7
VCC/2
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set−Up
Figure 12. Crosstalk Between Any Two Switches,
Test Set−Up
VCC
A
VIS
VCC
14
N/C
OFF/ON
VOS
0.1 mF
N/C
fin
ON
RL
7
VIH
VIL
CL*
TO
DISTORTION
METER
VCC/2
SELECTED
CONTROL
INPUT
7
SELECTED
CONTROL
INPUT
VIH
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance
Test Set−Up
Figure 14. Total Harmonic Distortion, Test Set−Up
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7
MC74LVXT4066
0
-10
FUNDAMENTAL FREQUENCY
-20
dBm
-30
-40
-50
DEVICE
-60
SOURCE
-70
-80
-90
1.0
3.0
2.0
FREQUENCY (kHz)
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION
The ON/OFF Control pins should be at VIH or VIL logic
levels, VIH being recognized as logic high and VIL being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
advisable to tie unused analog inputs and outputs to VCC or
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked−up by the unused
I/O pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and GND. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below GND. In the example
below, the difference between VCC and GND is six volts.
Therefore, using the configuration in Figure 16, a maximum
analog signal of six volts peak−to−peak can be controlled.
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external diodes (Dx)
are recommended as shown in Figure 17. These diodes
should be small signal, fast turn−on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
Mosorbs (Mosorb™ is an acronym for high current surge
protectors). Mosorbs are fast turn−on devices ideally suited
for precise DC protection with no inherent wear out
mechanism.
VCC
VCC = 6.0 V
+ 6.0 V
14
ANALOG I/O
ON
ANALOG O/I
Dx
+ 6.0 V
VIH
SELECTED
CONTROL
INPUT
7
16
Dx
ON
0V
0V
VCC
Dx
VIH
OTHER CONTROL
INPUTS
(VIH OR VIL)
Dx
SELECTED
CONTROL
INPUT
7
Figure 16. 6.0 V Application
OTHER CONTROL
INPUTS
(VIH OR VIL)
Figure 17. Transient Suppressor Application
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8
MC74LVXT4066
+3 V
+3V
GND
+5 V
14
ANALOG
SIGNALS
+3V
ANALOG
SIGNALS
GND
LVXT4066
6
14
15
CONTROL
INPUTS
ANALOG
SIGNALS
LVXT4066
LSTTL/
NMOS/
ABT/
ALS
5
1.8 - 2.5V
CIRCUITRY
14
ANALOG
SIGNALS
5
6
CONTROL
INPUTS
14
15
7
7
R* = 2 TO 10 kW
a. Low Voltage Logic Level Shifting Control
b. Using LVXT4066
Figure 18. Low Voltage CMOS Interface
CHANNEL 4
1 OF 4
SWITCHES
CHANNEL 3
1 OF 4
SWITCHES
CHANNEL 2
1 OF 4
SWITCHES
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
INPUT
1 OF 4
SWITCHES
+
OUTPUT
LF356 OR
EQUIVALENT
0.01 mF
1
2
3 4
CONTROL INPUTS
Figure 19. 4−Input Multiplexer
Figure 20. Sample/Hold Amplifier
ORDERING INFORMATION
Package
Shipping†
MC74LVXT4066DR2G
SOIC−14 NB
(Pb−Free)
2500 Tape & Reel
MC74LVXT4066DTRG
TSSOP−14
(Pb−Free)
2500 Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
SCALE 1:1
D
DATE 03 FEB 2016
A
B
14
8
A3
E
H
L
1
0.25
B
M
DETAIL A
7
13X
M
b
0.25
M
C A
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
1.27
PITCH
XXXXX
A
WL
Y
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 2:
CANCELLED
STYLE 3:
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 6:
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
STYLE 7:
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
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