MC74VHC245
Octal Bus Buffer/Line Driver
The MC74VHC245 is an advanced high speed CMOS octal bus
transceiver fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
It is intended for two−way asynchronous communication between
data buses. The direction of data transmission is determined by the
level of the DIR input. The output enable pin (OE) can be used to
disable the device, so that the buses are effectively isolated.
All inputs are equipped with protection circuits against static
discharge.
• High Speed: tPD = 4.0 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: VOLP = 1.2 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 308 FETs or 77 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
APPLICATION NOTES
• Do not force a signal on an I/O pin when it is an active output,
•
•
damage may occur.
All floating (high impedance) input or I/O pins must be fixed by
means of pull up or pull down resistors or bus terminator ICs.
A parasitic diode is formed between the bus and VCC terminals.
Therefore, the VHC245 cannot be used to interface 5 V to 3 V
systems directly.
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MARKING
DIAGRAMS
20
20
1
SOIC−20
DW SUFFIX
CASE 751D
VHC245
AWLYYWWG
1
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
VHC245
A
WL, L
Y
WW, W
G or G
1
VHC
245
ALYWG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
MC74VHC245DWG
SOIC−20
38 Units/Rail
MC74VHC245DTG
TSSOP−20
75 Units/Rail
Device
MC74VHC245DWR2G SOIC−20 1000 Units/Reel
MC74VHC245DTR2G TSSOP−20 2500 Units/T&R
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1
Publication Order Number:
MC74VHC245/D
MC74VHC245
A1
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
DIR
OE
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
B1
DIR
1
20
VCC
B2
A1
2
19
OE
B3
A2
3
18
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
B
DATA
PORT
B4
B5
B6
B7
B8
1
19
GND
Figure 1. LOGIC
DIAGRAM
Figure 2. PIN ASSIGNMENT
FUNCTION TABLE
Control Inputs
OE
DIR
L
L
Data Transmitted from Bus B to Bus A
L
H
Data Transmitted from Bus A to Bus B
H
X
Buses Isolated (High−Impedance State)
Operation
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2
MC74VHC245
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MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
− 40
+ 85
_C
0
0
100
20
ns/V
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 3.3V ±0.3V
VCC =5.0V ±0.5V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50μA
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50μA
Maximum Input
Leakage Current
Vin = 5.5 V or GND
(DIR, OE)
Min
Typ
TA = − 40 to 85°C
Max
1.50
VCC x 0.7
Min
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
Iin
TA = 25°C
2.0
3.0
4.5
V
0.50
VCC x 0.3
2.48
3.80
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
0 to 5.5
± 0.1
± 1.0
3
V
V
1.9
2.9
4.4
0.1
0.1
0.1
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Unit
0.0
0.0
0.0
V
μA
MC74VHC245
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS
VCC
V
Symbol
Parameter
Test Conditions
IOZ
Maximum
Three−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
TA = 25°C
Min
Typ
TA = − 40 to 85°C
Max
Min
Max
Unit
± 0.25
± 2.5
μA
4.0
40.0
μA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation Delay,
A to B or B to A
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Output Enable Time
OE to A or B
Output Disable Time
OE to A or B
Output to Output Skew
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
5.8
8.3
8.4
11.9
1.0
1.0
10.0
13.5
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
4.0
5.5
5.5
7.5
1.0
1.0
6.5
8.5
VCC = 3.3 ± 0.3V
RL = 1 kΩ
CL = 15pF
CL = 50pF
8.5
11.0
13.2
16.7
1.0
1.0
15.5
19.0
VCC = 5.0 ± 0.5V
RL = 1 kΩ
CL = 15pF
CL = 50pF
5.8
7.3
8.5
10.6
1.0
1.0
10.0
12.0
VCC = 3.3 ± 0.3V
RL = 1 kΩ
CL = 50pF
11.5
15.8
1.0
18.0
VCC = 5.0 ± 0.5V
RL = 1 kΩ
CL = 50pF
7.0
9.7
1.0
11.0
VCC = 3.3 ± 0.3V
(Note 1)
CL = 50pF
1.5
1.5
ns
VCC = 5.0 ± 0.5V
(Note 1)
CL = 50pF
1.0
1.0
ns
10
10
pF
Cin
Maximum Input Capacitance
DIR, OE
4
CI/O
Maximum Three−State
I/O Capacitance
8
ns
ns
pF
Typical @ 25°C, VCC = 5.0V
21
CPD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.9
1.2
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.9
−1.2
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
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4
MC74VHC245
SWITCHING WAVEFORMS
VCC
DIR
50%
GND
VCC
OE
GND
VCC
A or B
tPZL
50%
GND
tPLH
50% VCC
50% VCC
tPHL
A or B
B or A
A or B
HIGH
IMPEDANCE
50% VCC
tPZH
50% VCC
tPLZ
VOL +0.3V
tPHZ
VOH -0.3V
50% VCC
Figure 3.
HIGH
IMPEDANCE
Figure 4.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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5
MC74VHC245
A1
2
18
A2
3
17
A3
OE
B7
9
11
DIR
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A4
B1
B8
1
19
Figure 7. EXPANDED LOGIC DIAGRAM
DIR, OE
A, B
INPUT
I/O
Figure 9. BUS TERMINAL EQUIVALENT CIRCUIT
Figure 8. INPUT EQUIVALENT CIRCUIT
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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