MC74VHC574
Octal D-Type Flip-Flop
with 3-State Output
The MC74VHC574 is an advanced high speed CMOS octal
flip−flip with 3−state output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
•
•
•
•
•
•
•
•
•
•
•
•
High Speed: fmax = 180 MHz (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: VOLP = 1.2 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING DIAGRAMS
20
SOIC−20
DW SUFFIX
CASE 751D
20
1
VHC574
AWLYYWWG
1
20
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
VHC
574
ALYWG
G
VHC574 = Specific Device Code
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
MC74VHC574DWR2G
SOIC−20
1000 / T&R
MC74VHC574DWG
SOIC−20
38 / Rail
MC74VHC574DTR2G
TSSOP−20
2500 / T&R
MC74VHC574DTG
TSSOP−20
75 / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 6
1
Publication Order Number:
MC74VHC574/D
MC74VHC574
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CP
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
Q0
Q1
OE
1
20
VCC
Q2
D0
2
19
Q0
Q3
D1
3
18
Q1
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
Q7
10
11
CP
Q4
NONINVERTING
OUTPUTS
Q5
Q6
Q7
11
GND
OE
1
Figure 1. LOGIC DIAGRAM
Figure 2. PIN ASSIGNMENT
FUNCTION TABLE
INPUTS
OE
L
L
L
H
OUTPUT
CP
D
Q
L, H,
X
H
L
X
X
H
L
No Change
Z
http://onsemi.com
2
MC74VHC574
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MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
− 20
mA
IOK
Output Diode Current
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
5.5
V
VCC
DC Supply Voltage
Vin
DC Input Voltage
0
5.5
V
Vout
DC Output Voltage
0
VCC
V
− 40
+ 85
_C
0
0
100
20
ns/V
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 3.3V
VCC = 5.0V
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VIH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
VIL
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50μA
Vin = VIH or VIL
IOH = − 4mA
IOH = − 8mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50μA
TA = 25°C
Min
Min
1.9
2.9
4.4
3.0
4.5
2.58
3.94
3.0
4.5
http://onsemi.com
Max
1.50
VCC x 0.7
0.50
VCC x 0.3
2.0
3.0
4.5
3
Max
1.50
VCC x 0.7
2.0
3.0
4.5
Vin = VIH or VIL
IOL = 4mA
IOL = 8mA
Typ
TA = − 40 to 85°C
2.0
3.0
4.5
Unit
V
0.50
VCC x 0.3
V
V
1.9
2.9
4.4
2.48
3.80
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.36
0.36
0.44
0.44
V
MC74VHC574
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
TA = 25°C
Min
Typ
TA = − 40 to 85°C
Max
Min
Max
Unit
Iin
Maximum Input
Leakage Current
Vin = 5.5V or GND
0 to 5.5
± 0.1
± 1.0
μA
IOZ
Maximum
Three−State Leakage
Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.25
± 2.5
μA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
40.0
μA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
fmax
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSLH,
tOSHL
Parameter
Maximum Clock Frequency
(50% Duty Cycle)
Maximum Propagation Delay,
CP to Q
Output Enable Time,
OE to Q
Output Disable Time,
OE to Q
Output to Output Skew
Test Conditions
TA = − 40 to 85°C
Min
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
80
50
125
75
—
—
65
45
—
—
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
130
85
180
115
—
—
110
75
—
—
VCC = 3.3 ± 0.3
CL = 15pF
CL = 50pF
—
—
8.5
11.0
13.2
16.7
1.0
1.0
15.5
19.0
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
—
—
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 15pF
CL = 50pF
—
—
8.2
10.7
12.8
16.3
1.0
1.0
15.0
18.5
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 15pF
CL = 50pF
—
—
5.9
7.4
9.0
11.0
1.0
1.0
10.5
12.5
VCC = 3.3 ± 0.3V
RL = 1kΩ
CL = 50pF
—
11.0
15.0
1.0
17.0
VCC = 5.0 ± 0.5V
RL = 1kΩ
CL = 50pF
—
7.1
10.1
1.0
11.5
VCC = 3.3 ± 0.3V
(Note 1)
CL = 50pF
—
—
1.5
—
1.5
ns
VCC = 5.0 ± 0.5V
(Note 1)
CL = 50pF
—
—
1.0
—
1.0
ns
ns
ns
ns
Cin
Maximum Input Capacitance
—
4
10
—
10
pF
Cout
Maximum Three−State Output
Capacitance, Output in
High−Impedance State
—
6
—
—
—
pF
Typical @ 25°C, VCC = 5.0V
28
CPD
Power Dissipation Capacitance (Note 2)
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per flip−flop). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
http://onsemi.com
4
MC74VHC574
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.9
1.2
V
VOLV
Quiet Output Minimum Dynamic VOL
− 0.9
− 1.2
V
VIHD
Minimum High Level Dynamic Input Voltage
—
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
—
1.5
V
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
TA = − 40
to 85°C
TA = 25°C
Symbol
Parameter
Test Conditions
Typ
Limit
Limit
Unit
tsu
Minimum Setup Time, D to CP
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
—
—
3.5
3.5
3.5
3.5
ns
th
Minimum Hold Time, CP to D
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
—
—
1.5
1.5
1.5
1.5
ns
tw
Minimum Pulse Width, CP
VCC = 3.3 ± 0.3 V
VCC = 5.0 ± 0.5 V
—
—
5.0
5.0
5.5
5.0
ns
VCC
VCC
CP
50%
OE
GND
tw
50%
GND
tPZL
1/fmax
tPLH
tPHL
Q
tPLZ
tPZH
Q
50% VCC
Q
HIGH
IMPEDANCE
50% VCC
VOL +0.3V
tPHZ
VOH -0.3V
HIGH
IMPEDANCE
50% VCC
Figure 3. Switching Waveforms
TEST POINT
VALID
VCC
D
50%
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
VCC
CP
50%
CL*
GND
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
http://onsemi.com
5
MC74VHC574
D0
D1
D2
D3
D4
D5
D6
D7
2
C
Q
D
19
3
C
Q
D
18
4
C
Q
D
17
5
C
Q
D
16
6
C
Q
D
15
7
C
Q
D
14
8
C
Q
D
13
9
C
Q
D
12
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
Figure 6. Expanded Logic Diagram
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
INPUT
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. INPUT EQUIVALENT CIRCUIT
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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