MC74VHCT244A
Octal Bus Buffer/Line Driver
with 3-State Outputs
The MC74VHCT244A is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT244A is a noninverting 3−state buffer, and has two
active−low output enables. This device is designed to be used with
3−state memory address drivers, etc.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT244A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply voltage−input/
output voltage mismatch, battery backup, hot insertion, etc.
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MARKING
DIAGRAMS
20
1
SOIC−20WB
SUFFIX DW
CASE 751D
•
•
•
High Speed: tPD = 5.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4.0 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.1 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 112 FETs or 28 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 9
1
20
Features
•
•
•
•
•
•
•
•
•
•
VHCT244A
AWLYYWWG
1
1
TSSOP−20
SUFFIX DT
CASE 948E
VHCT
244A
ALYWG
G
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Publication Order Number:
MC74VHCT244A/D
MC74VHCT244A
A1
A2
A3
A4
DATA
INPUTS
B1
B2
B3
B4
2
18
4
16
6
14
8
12
11
9
13
7
15
5
17
3
YA1
YA2
YA3
YA4
YB1
NONINVERTING
OUTPUTS
YB2
YB3
YB4
1
OEA
19
OEB
OUTPUT
ENABLES
Figure 1. Logic Diagram
FUNCTION TABLE
OEA
1
20
VCC
A1
2
19
OEB
YB4
3
18
YA1
OEA, OEB
A, B
YA, YB
A2
4
17
B4
YB3
5
16
YA2
L
L
H
LL
HH
XZ
LL
HH
ZZ
A3
6
15
B3
YB2
7
14
YA3
A4
8
13
B2
YB1
9
12
YA4
GND
10
11
B1
Inputs
Figure 2. Pin Assignment
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2
Outputs
MC74VHCT244A
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ÎÎÎÎ
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to +7.0
–0.5 to VCC + 0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
–65 to +150
°C
Output in 3−State
High or Low State
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating − SOIC Packages: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
Output in 3−State
High or Low State
VCC = 5.0 V ± 0.5 V
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
−40
+125
°C
0
20
ns/V
DC ELECTRICAL CHARACTERISTICS
TA = 25°C
Min
Symbol
Parameter
VIH
Minimum High−Level
Input Voltage
4.5 to
5.5
VIL
Maximum Low−Level
Input Voltage
4.5 to
5.5
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = −50 mA
4.5
4.4
IOH = −8 mA
4.5
3.94
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50 mA
4.5
IOL = 8 mA
VOL
Test Conditions
VCC
V
Typ
TA = − 40 to 85°C
Max
2.0
Min
Max
2.0
0.8
4.5
0.0
TA = 85 to 125°C
Min
Max
2.0
0.8
V
0.8
4.4
4.4
3.80
3.66
Unit
V
V
0.1
0.1
0.1
4.5
0.36
0.44
0.52
V
Iin
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
IOZ
Maximum 3−State
Leakage Current
Vin = VIL or VIH
Vout = VCC or GND
5.5
±0.25
±2.5
2.5
mA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
4.0
40.0
40.0
mA
ICCT
Quiescent Supply
Current
Per Input: VIN =3.4 V
Other Input: VCC or
GND
5.5
1.35
1.50
1.65
mA
IOPD
Output Leakage
Current
VOUT = 5.5 V
0
0.5
5.0
10
mA
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3
MC74VHCT244A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Symbol
Parameter
Min
Test Conditions
TA = − 40 to 85°C
TA = 85 to 125°C
Typ
Max
Min
Max
Min
Max
Unit
tPLH,
tPHL
Maximum
Propagation Delay
A to YA or B to YB
VCC = 5.0 ± 0.5 V CL = 15 pF
CL = 50 pF
5.4
5.9
7.4
8.4
1.0
1.0
8.5
9.5
11.0
1.0
9.5
10.5
ns
tPZL,
tPZH
Output Enable Time
OEA to YA or OEB to
YB
VCC = 5.0 ± 0.5 V CL = 15 pF
RL = 1 kW
CL = 50 pF
7.7
8.2
10.4
11.4
1.0
1.0
12.0
13.0
1.0
1.0
13.5
14.5
ns
tPLZ,
tPHZ
Output Disable Time
OEA to YA or OEB to
YB
VCC = 5.0 ± 0.5 V CL = 50 pF
RL = 1 kW
8.8
11.4
1.0
13.0
1.0
14.5
ns
Output to Output
Skew
VCC = 5.0 ± 0.5 V CL = 50 pF
(Note 1)
1.0
ns
tOSLH,
tOSHL
1.0
1.0
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Typical @ 25°C, VCC = 5.0 V
Symbol
Min
Parameter
Typ
Max
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CPD
Power Dissipation Capacitance (Note 2)
18
Cin
Maximum Input Capacitance
4
Cout
Maximum Three−State Output Capacitance (Output in High−Impedance State)
9
pF
10
pF
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Symbol
Parameter
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.9
1.1
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.9
−1.1
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
ORDERING INFORMATION
Device
MC74VHCT244ADWRG
Package
Shipping†
SOIC−20WB
(Pb−Free)
1000 / Tape & Reel
MC74VHCT244ADTG
MC74VHCT244ADTRG
75 Units / Rail
TSSOP−20
(Pb−Free)
NLV74VHCT244ADTRG*
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHCT244A
3V
A or B
1.5 V
GND
tPHL
tPLH
YA or YB
VOH
1.5 V
VOL
Figure 3. Switching Waveform
3V
OEA or OEB
1.5 V
tPZL
YA or YB
HIGH
IMPEDANCE
1.5 V
tPZH
YA or YB
GND
tPLZ
VOL +0.3 V
tPHZ
VOH -0.3 V
1.5 V
HIGH
IMPEDANCE
Figure 4. Switching Waveform
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 5. Test Circuit
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
A
20
q
X 45 _
M
E
h
0.25
H
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
b
0.25
M
T A
S
B
DIM
A
A1
b
c
D
E
e
H
h
L
q
S
L
A
18X
e
SEATING
PLANE
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
20
20X
20X
1.30
0.52
20
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
11
1
11.00
1
XXXXX
A
WL
YY
WW
G
10
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
98ASB42343B
SOIC−20 WB
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
0.65
PITCH
16X
0.36
16X
1.26
DOCUMENT NUMBER:
98ASH70169A
DESCRIPTION:
TSSOP−20 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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