MC74VHCT50ADT

MC74VHCT50A Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs The MC74VHCT50A is a hex noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The device input is compatible with TTL−type input thresholds and the output has a full 5 V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic−level translator from 3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high−voltage power supply. The MC74VHCT50A input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHCT50A to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage − input/output voltage mismatch, battery backup, hot insertion, etc. http://onsemi.com 14−LEAD SOIC D SUFFIX CASE 751A 14−LEAD TSSOP DT SUFFIX CASE 948G 14−LEAD SOIC EIAJ M SUFFIX CASE 965 PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8 • • • • • • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Pb−Free Packages are Available 1 A1 2 Y1 3 A2 4 Y2 5 A3 6 Y3 7 GND For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. LOGIC DIAGRAM A1 1 2 Y1 A1 A2 3 4 Y2 A2 A3 5 6 Y3 Y=A A4 9 8 Y4 A4 A5 Y5 A6 A6 13 12 Y6 A3 LOGIC SYMBOL FUNCTION TABLE 1 1 1 1 1 1 Y1 Y2 Y3 Y4 Y5 Y6 A Input L H Y Output L H ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. A5 11 10 © Semiconductor Components Industries, LLC, 2007 1 January, 2007− Rev. 6 Publication Order Number: MC74VHCT50A/D MC74VHCT50A MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance SOIC TSSOP PD Power Dissipation in Still Air SOIC TSSOP VESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) 500 450 > 2000 > 200 2000 $300 V 125 170 mW Output in HIGH or LOW State (Note 1) Parameter Value *0.5 to )7.0 *0.5 v VI v )7.0 *0.5 v VO v )7.0 *20 $20 $25 $50 $50 *65 to )150 260 )150 Unit V V V mA mA mA mA mA _C _C _C _C/W ILatch−Up Latch−Up Performance mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Characteristics DC Supply Voltage DC Input Voltage DC Output Voltage VCC = 0 High or Low State Symbol VCC VIN VOUT TA tr , tf Min 2.0 0.0 0.0 0.0 −55 0 0 Max 5.5 5.5 5.5 VCC +125 100 20 TEST POINT 3.0V A 50% GND tPLH 50% VCC tPHL VOH Y VOL *Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT C L* Unit V V V °C ns/V Operating Temperature Range Input Rise and Fall Time VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Figure 1. Switching Waveforms Figure 2. Test Circuit http://onsemi.com 2 MC74VHCT50A DC ELECTRICAL CHARACTERISTICS VCC Symbol VIH Parameter Minimum High−Level Input Voltage Maximum Low−Level Input Voltage Minimum High−Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOH = −50 mA VIN = VIH or VIL IOH = −4 mA IOH = −8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = −4 mA IOL = 8 mA VIN = 5.5 V or GND VIN = VCC or GND Input: VIN = 3.4 V VOUT = 5.5 V Test Conditions (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 0 to 5.5 5.5 5.5 0.0 2.9 4.4 2.58 3.94 0.0 0.0 0.1 0.1 0.36 0.36 ±0.1 2.0 1.35 0.5 3.0 4.5 Min 1.2 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.48 3.80 0.1 0.1 0.44 0.44 ±1.0 20 1.50 5.0 TA = 25°C Typ Max TA ≤ 85°C Min 1.2 2.0 2.0 0.53 0.8 0.8 2.9 4.4 2.34 3.66 0.1 0.1 0.52 0.52 ±1.0 40 1.65 10 μA μA mA μA V V Max TA ≤ 125°C Min 1.2 2.0 2.0 0.53 0.8 0.8 Max Unit V VIL V VOH V V VOL Maximum Low−Level Output Voltage VIN = VIH or VIL IIN ICC ICCT IOFF Maximum Input Leakage Current Maximum Quiescent Supply Current Quiescent Supply Current Output Leakage Current ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns) Symbol Parameter Test Conditions Min TA = 25°C Typ 5.5 8.0 6.2 7.0 5 TA ≤ 85°C TA ≤ 125°C Max 7.9 11.4 7.5 8.5 10 Min 1.0 1.0 Max Min Max Unit ns tPLH, tPHL Maximum Propogation Delay, Input A to Y VCC = 3.3 ± 0.3 V VCC = 5.0 ± 0.5 V CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF 9.5 13.0 8.5 9.5 10 9.5 10.5 10 pF CIN Maximum Input Capacitance Typical @ 25°C, VCC = 5.0 V 15 CPD Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Symbol VOLP VOLV VIHD VILD Characteristic Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage Typ 0.8 −0.8 Max 1.0 −1.0 2.0 0.8 Unit V V V V http://onsemi.com 3 MC74VHCT50A ORDERING INFORMATION Device MC74VHCT50AD MC74VHCT50ADG MC74VHCT50ADR2 MC74VHCT50ADR2G MC74VHCT50ADT MC74VHCT50ADTG MC74VHCT50ADTR2 MC74VHCT50ADTR2G MC74VHCT50AM MC74VHCT50AMG MC74VHCT50AMEL MC74VHCT50AMELG Package SOIC−14 SOIC−14 (Pb−Free) SOIC−14 SOIC−14 (Pb−Free) TSSOP−14 TSSOP−14 (Pb−Free) TSSOP−14 TSSOP−14 (Pb−Free) SOIC EIAJ SOIC EIAJ (Pb−Free) SOIC EIAJ SOIC EIAJ (Pb−Free) Shipping † 55 Units / Rail 55 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 96 Units / Rail 96 Units / Rail 2500 / Tape & Reel 2500 / Tape & Reel 50 Units / Rail 50 Units / Rail 2000 / Tape & Reel 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 8 14 13 12 11 10 VHCT 50A ALYWG G 5 6 7 1 2 3 4 5 6 7 9 8 VHCT50AG AWLYWW* 1 2 3 4 14−LEAD SOIC D SUFFIX CASE 751A 14 13 12 11 10 9 8 14−LEAD TSSOP DT SUFFIX CASE 948G 74VHCT50A ALYWG* 1 2 3 4 5 6 7 14−LEAD SOIC EIAJ M SUFFIX CASE 965 A WL, L Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *See Applications Note #AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHCT50A PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A−03 ISSUE G −A− 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −B− 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 _ F −T− SEATING PLANE D 14 PL 0.25 (0.010) K M M S J TB A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 SOLDERING FOOTPRINT 7X 7.04 1 14X 14X 1.52 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 5 MC74VHCT50A PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G−01 ISSUE B 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C −−− 1.20 −−− 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B −U− N F DETAIL E K K1 J J1 0.15 (0.006) T U S A −V− SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D G H DETAIL E SOLDERING FOOTPRINT 7.06 1 14X 0.36 14X 1.26 http://onsemi.com 6 ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ 0.65 PITCH DIMENSIONS: MILLIMETERS MC74VHCT50A PACKAGE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965−01 ISSUE A 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.056 c b 0.13 (0.005) M A1 0.10 (0.004) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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