MJD3055

MJD2955(PNP), MJD3055(NPN) Complementary Power Transistors DPAK for Surface Mount Applications http://onsemi.com Designed for general purpose amplifier and low speed switching applications. Features • Lead Formed for Surface Mount Applications in Plastic Sleeves • • • • • • (No Suffix) Straight Lead Version in Plastic Sleeves (“−1” Suffix) Electrically Similar to MJE2955 and MJE3055 High Current Gain−Bandwidth Product Epoxy Meets UL 94 V−0 @ 0.125 in NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant SILICON POWER TRANSISTORS 10 AMPERES 60 VOLTS, 20 WATTS COMPLEMENTARY COLLECTOR 2, 4 1 BASE 1 BASE 3 EMITTER MAXIMUM RATINGS Rating Symbol Max Unit VCEO 60 Vdc Collector−Base Voltage VCB 70 Vdc Emitter−Base Voltage VEB 5 Vdc IC 10 Adc IB 6 Adc 20 0.16 W W/°C 1.75 0.014 W W/°C Collector−Emitter Voltage Collector Current Base Current COLLECTOR 2, 4 Total Power Dissipation @ TC = 25°C Derate above 25°C PD{ Total Power Dissipation (Note 1) @ TA = 25°C Derate above 25°C PD Operating and Storage Junction Temperature Range TJ, Tstg −55 to +150 °C ESD − Human Body Model HBM 3B V ESD − Machine Model MM C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Safe Area Curves are indicated by Figure 1. Both limits are applicable and must be observed. 1. These ratings are applicable when surface mounted on the minimum pad sizes recommended. 3 EMITTER 4 4 1 2 1 3 DPAK CASE 369C STYLE 1 2 3 IPAK CASE 369D STYLE 1 MARKING DIAGRAMS AYWW J xx55G DPAK A Y WW Jxx55 G AYWW J xx55G IPAK = Assembly Location = Year = Work Week = Device Code x = 29 or 30 = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2013 August, 2013 − Rev. 13 1 Publication Order Number: MJD2955/D MJD2955 (PNP), MJD3055 (NPN) THERMAL CHARACTERISTICS Characteristic Symbol Max Unit Thermal Resistance, Junction−to−Case RqJC 6.25 °C/W Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 71.4 °C/W ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 2. These ratings are applicable when surface mounted on the minimum pad sizes recommended. ELECTRICAL CHARACTERISTICS (TC = 25_C unless otherwise noted) Characteristic Symbol Min Max 60 − − 50 − − 0.02 2 − − 0.02 2 − 0.5 20 5 100 − − − 1.1 8 − 1.8 2 − Unit OFF CHARACTERISTICS Collector−Emitter Sustaining Voltage (Note 3) (IC = 30 mAdc, IB = 0) VCEO(sus) Collector Cutoff Current (VCE = 30 Vdc, IB = 0) ICEO Collector Cutoff Current (VCE = 70 Vdc, VEB(off) = 1.5 Vdc) (VCE = 70 Vdc, VEB(off) = 1.5 Vdc, TC = 150_C) ICEX Collector Cutoff Current (VCB = 70 Vdc, IE = 0) (VCB = 70 Vdc, IE = 0, TC = 150_C) ICBO Emitter Cutoff Current (VBE = 5 Vdc, IC = 0) IEBO Vdc mAdc mAdc mAdc mAdc ON CHARACTERISTICS hFE DC Current Gain (Note 3) (IC = 4 Adc, VCE = 4 Vdc) (IC = 10 Adc, VCE = 4 Vdc) Collector−Emitter Saturation Voltage (Note 3) (IC = 4 Adc, IB = 0.4 Adc) (IC = 10 Adc, IB = 3.3 Adc) VCE(sat) Base−Emitter On Voltage (Note 3) (IC = 4 Adc, VCE = 4 Vdc) VBE(on) − Vdc Vdc DYNAMIC CHARACTERISTICS fT Current−Gain − Bandwidth Product (IC = 500 mAdc, VCE = 10 Vdc, f = 500 kHz) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. http://onsemi.com 2 MHz MJD2955 (PNP), MJD3055 (NPN) TYPICAL CHARACTERISTICS PD, POWER DISSIPATION (WATTS) TA TC 2.5 25 2 20 TC 1.5 15 TA SURFACE MOUNT 1 10 0.5 5 0 0 25 50 75 100 125 150 T, TEMPERATURE (°C) Figure 1. Power Derating 2 500 100 VCE = 2 V 0.7 0.5 25°C -55°C 50 30 20 0.02 0.05 0.1 0.5 0.2 1 2 5 10 0 0.1 0.2 0.4 0.6 1 2 Figure 2. DC Current Gain Figure 3. Turn−On Time 4 6 5 TJ = 25°C VCC = 30 V IC/IB = 10 IB1 = IB2 3 2 TJ = 25°C 1 VBE(sat) @ IC/IB = 10 VBE @ VCE = 2 V 0.4 0.2 0.06 0.1 IC, COLLECTOR CURRENT (AMP) t, TIME (s) μ V, VOLTAGE (VOLTS) 0.6 td @ VBE(off) ≈ 5 V IC, COLLECTOR CURRENT (AMP) 1 0.8 0.1 0.03 0.02 1.4 1.2 tr 0.3 0.2 0.07 0.05 10 5 0.01 TJ = 25°C VCC = 30 V IC/IB = 10 1 TJ = 150°C t, TIME (s) μ hFE , DC CURRENT GAIN 300 200 ts 0.7 0.5 0.3 0.2 tf 0.1 VCE(sat) @ IC/IB = 10 0.2 0.3 0.5 1 2 3 5 0.07 0.05 0.06 0.1 10 0.2 0.4 0.6 1 IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP) Figure 4. “On” Voltages, MJD3055 Figure 5. Turn−Off Time http://onsemi.com 3 2 4 6 MJD2955 (PNP), MJD3055 (NPN) 2 TJ = 25°C 1.6 V, VOLTAGE (VOLTS) VCC +30 V 25 ms RC +11 V 0 1.2 SCOPE RB -9 V VBE(sat) @ IC/IB = 10 0.8 VBE @ VCE = 3 V D1 51 tr, tf ≤ 10 ns DUTY CYCLE = 1% -4 V 0.4 RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS VCE(sat) @ IC/IB = 10 0 0.1 0.2 0.3 0.5 1 2 3 IC, COLLECTOR CURRENT (AMP) D1 MUST BE FAST RECOVERY TYPE, eg: 1N5825 USED ABOVE IB ≈ 100 mA MSD6100 USED BELOW IB ≈ 100 mA 10 5 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Figure 6. “On” Voltages, MJD2955 1 0.7 0.5 Figure 7. Switching Time Test Circuit D = 0.5 0.3 0.2 0.2 0.1 0.07 0.05 0.05 0.02 0.01 0.03 0.02 P(pk) RqJC(t) = r(t) RqJC RqJC = 6.25°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) qJC(t) 0.1 t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 t, TIME (ms) 10 20 30 50 100 200 300 500 1k Figure 8. Thermal Response Forward Bias Safe Operating Area Information IC, COLLECTOR CURRENT (AMP) 10 5 3 2 100ms 1 1ms 0.5 0.3 5ms 0.1 dc WIRE BOND LIMIT THERMAL LIMIT TC = 25°C (D = 0.1) SECOND BREAKDOWN LIMIT 0.05 0.03 0.02 0.01 0.6 There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 9 is based on TJ(pk) = 150_C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) ≤ 150_C. TJ(pk) may be calculated from the data in Figure 8. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. 500ms TJ = 150°C 1 2 20 4 6 10 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) 40 60 Figure 9. Maximum Forward Bias Safe Operating Area http://onsemi.com 4 MJD2955 (PNP), MJD3055 (NPN) ORDERING INFORMATION Package Type Package Shipping† MJD2955G DPAK (Pb−Free) 369C 75 Units / Rail MJD2955−1G IPAK (Pb−Free) 369D 75 Units / Rail MJD2955T4G DPAK (Pb−Free) 369C 2,500 / Tape & Reel NJVMJD2955T4G* DPAK (Pb−Free) 369C 2,500 / Tape & Reel MJD3055G DPAK (Pb−Free) 369C 75 Units / Rail MJD3055T4G DPAK (Pb−Free) 369C 2,500 / Tape & Reel NJVMJD3055T4G* DPAK (Pb−Free) 369C 2,500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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