MJD45H11RLG

DATA SHEET www.onsemi.com Complementary Power Transistors SILICON POWER TRANSISTORS 8 AMPERES 80 VOLTS, 20 WATTS DPAK for Surface Mount Applications MJD44H11(NPN), MJD45H11(PNP) COMPLEMENTARY Designed for general purpose power and switching such as output or driver stages in applications such as switching regulators, converters, and power amplifiers. COLLECTOR 2, 4 1 BASE 1 BASE Features 3 EMITTER • Lead Formed for Surface Mount Application in Plastic Sleeves • • • • • • • • (No Suffix) Straight Lead Version in Plastic Sleeves (“−1” Suffix) Electrically Similar to Popular D44H/D45H Series Low Collector Emitter Saturation Voltage Fast Switching Speeds Complementary Pairs Simplifies Designs Epoxy Meets UL 94 V−0 @ 0.125 in NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MAXIMUM RATINGS (TA = 25_C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted) Rating Collector−Emitter Voltage Emitter−Base Voltage 4 1 2 3 DPAK CASE 369C STYLE 1 Unit Vdc DPAK A Y WW J4xH11 Vdc Adc Collector Current − Peak ICM 16 Adc Total Power Dissipation @ TC = 25°C Derate above 25°C PD 20 0.16 W W/°C Total Power Dissipation (Note 1) @ TA = 25°C Derate above 25°C PD 1.75 0.014 W W/°C Operating and Storage Junction Temperature Range TJ, Tstg −55 to +150 °C ESD − Human Body Model HBM 3B V ESD − Machine Model MM C V DPAK CASE 369G STYLE 1 2 3 IPAK CASE 369D STYLE 1 AYWW J4 xH11G AYWW J4 xH11G 80 8 1 2 3 MARKING DIAGRAMS Max 5 4 1 VCEO IC 3 EMITTER 4 Symbol VEB Collector Current − Continuous COLLECTOR 2, 4 G IPAK = = = = Assembly Location Year Work Week Device Code x = 4 or 5 = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. These ratings are applicable when surface mounted on the minimum pad sizes recommended. © Semiconductor Components Industries, LLC, 2016 August, 2021 − Rev. 21 1 Publication Order Number: MJD44H11/D MJD44H11 (NPN), MJD45H11 (PNP) THERMAL CHARACTERISTICS Symbol Max Unit Thermal Resistance, Junction−to−Case Characteristic RqJC 6.25 °C/W Thermal Resistance, Junction−to−Ambient (Note 2) RqJA 71.4 °C/W TL 260 °C Unit Lead Temperature for Soldering 2. These ratings are applicable when surface mounted on the minimum pad sizes recommended. ELECTRICAL CHARACTERISTICS (TA = 25_C, common for NPN and PNP, minus sign, “−”, for PNP omitted, unless otherwise noted) Characteristic Symbol Min Typ Max 80 − − − − 1.0 − − 1.0 − − 1 − − 1.5 60 40 − − − − OFF CHARACTERISTICS Collector−Emitter Sustaining Voltage (IC = 30 mA, IB = 0) VCEO(sus) Collector Cutoff Current (VCE = Rated VCEO, VBE = 0) ICES Emitter Cutoff Current (VEB = 5 Vdc) IEBO Vdc mA mA ON CHARACTERISTICS Collector−Emitter Saturation Voltage (IC = 8 Adc, IB = 0.4 Adc) VCE(sat) Base−Emitter Saturation Voltage (IC = 8 Adc, IB = 0.8 Adc) VBE(sat) DC Current Gain (VCE = 1 Vdc, IC = 2 Adc) (VCE = 1 Vdc, IC = 4 Adc) hFE Vdc Vdc − DYNAMIC CHARACTERISTICS Collector Capacitance (VCB = 10 Vdc, ftest = 1 Mhz) MJD44H11 MJD45H11 Gain Bandwidth Product (IC = 0.5 Adc, VCE = 10 Vdc, f = 20 Mhz) MJD44H11 MJD45H11 Ccb pF − − 45 130 − − fT MHz − − 85 90 − − SWITCHING TIMES Delay and Rise Times (IC = 5 Adc, IB1 = 0.5 Adc) MJD44H11 MJD45H11 td + tr ns − − Storage Time (IC = 5 Adc, IB1 = IB2 = 0.5 Adc) MJD44H11 MJD45H11 ts Fall Time (IC = 5 Adc, IB1 = IB2 = 0.5 Adc) MJD44H11 MJD45H11 tf 300 135 − − ns − − 500 500 − − ns − − 140 100 − − Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) MJD44H11 (NPN), MJD45H11 (PNP) 1 0.7 0.5 D = 0.5 0.3 0.2 0.2 RqJC(t) = r(t) RqJC RqJC = 6.25°C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) qJC(t) 0.1 0.1 0.07 0.05 0.05 0.02 0.01 0.03 0.02 P(pk) t1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 t, TIME (ms) 10 20 30 50 100 200 300 500 1k Figure 1. Thermal Response There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 2 is based on TJ(pk) = 150_C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) ≤ 150_C. TJ(pk) may be calculated from the data in Figure 1. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. IC, COLLECTOR CURRENT (AMP) 20 10 500ms 5 3 2 dc 100ms 1ms 5ms 1 THERMAL LIMIT @ TC = 25°C WIRE BOND LIMIT 0.5 0.3 0.1 0.05 1 50 3 5 7 10 20 30 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) 70 100 Figure 2. Maximum Forward Bias Safe Operating Area TA TC 2.5 25 PD, POWER DISSIPATION (WATTS) 0.02 2 20 TC 1.5 15 TA SURFACE MOUNT 1 10 0.5 5 0 0 25 50 75 100 T, TEMPERATURE (°C) Figure 3. Power Derating www.onsemi.com 3 125 150 MJD44H11 (NPN), MJD45H11 (PNP) 1000 VCE = 1 V VCE = 1 V hFE, DC CURRENT GAIN hFE, DC CURRENT GAIN 1000 150°C 25°C 100 10 −55°C 0.01 0.1 1 150°C 25°C 10 10 −55°C 100 0.01 0.1 1 IC, COLLECTOR CURRENT (A) Figure 4. MJD44H11 DC Current Gain Figure 5. MJD45H11 DC Current Gain 1000 1000 hFE, DC CURRENT GAIN 150°C 25°C 10 VCE(sat), COLL−EMIT SATURATION VOLTAGE (V) VCE = 4 V −55°C 0.01 0.1 1 0.01 0.1 1 10 Figure 6. MJD44H11 DC Current Gain Figure 7. MJD45H11 DC Current Gain IC/IB = 20 150°C 0.5 0.4 25°C 0.3 0.2 −55°C 0.1 0.01 −55°C 100 IC, COLLECTOR CURRENT (A) 0.6 0 25°C IC, COLLECTOR CURRENT (A) 0.8 0.7 150°C 10 10 VCE(sat), COLL−EMIT SATURATION VOLTAGE (V) hFE, DC CURRENT GAIN VCE = 4 V 100 10 IC, COLLECTOR CURRENT (A) 0.1 1 10 0.8 IC/IB = 20 0.7 −55°C 0.6 0.5 0.4 25°C 0.3 150°C 0.2 0.1 0 0.01 0.1 1 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 8. MJD44H11 Saturation Voltage VCE(sat) Figure 9. MJD45H11 Saturation Voltage VCE(sat) www.onsemi.com 4 10 MJD44H11 (NPN), MJD45H11 (PNP) 1.4 1.0 0.8 −55°C 25°C 0.6 0.4 150°C IC/IB = 20 0.2 0 VCE, COLLECTOR−EMITTER VOLTAGE (V) VBE(sat), BASE−EMIT SATURATION VOLTAGE (V) 1.2 0.01 0.1 1 −55°C 0.8 25°C 0.6 150°C 0.4 IC/IB = 20 0.2 0.01 0.1 1 10 IC, COLLECTOR CURRENT (A) Figure 10. MJD44H11 Saturation Voltage VBE(sat) Figure 11. MJD45H11 Saturation Voltage VBE(sat) 1.8 TA = 25°C 1.6 1.4 1.2 1.0 0.8 0.6 IC = 8 A 0.4 1A 0.2 IC = 0.1 A 0.5 A 0 0.1 1 10 IC = 3 A 100 1000 10,000 2.0 1.8 TA = 25°C 1.6 1.4 1.2 1.0 0.8 IC = 8 A 0.6 IC = 3 A 0.4 0.2 I = 0.1 A 0.5 A C 0 0.1 1 1A 10 100 1000 10,000 IB, BASE CURRENT (mA) IB, BASE CURRENT (mA) Figure 12. MJD44H11 Collector Saturation Region Figure 13. MJD45H11 Collector Saturation Region 1000 C, CAPACITANCE (pF) 1000 C, CAPACITANCE (pF) 1.0 IC, COLLECTOR CURRENT (A) 2.0 Cob 100 10 1.2 0 10 VCE, COLLECTOR−EMITTER VOLTAGE (V) VBE(sat), BASE−EMIT SATURATION VOLTAGE (V) 1.4 0.1 1 10 Cob 100 10 100 0.1 1 10 VR, REVERSE VOLTAGE (V) VR, REVERSE VOLTAGE (V) Figure 14. MJD44H11 Capacitance Figure 15. MJD45H11 Capacitance www.onsemi.com 5 100 MJD44H11 (NPN), MJD45H11 (PNP) 10 0.01 100 VCE = 2 V fTau, CURRENT−GAIN−BANDWIDTH PRODUCT fTau, CURRENT−GAIN−BANDWIDTH PRODUCT 100 0.1 1 10 10 VCE = 2 V 0.01 0.1 1 IC, COLLECTOR CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 16. MJD44H11 Current−Gain−Bandwidth Product Figure 17. MJD45H11 Current−Gain−Bandwidth Product www.onsemi.com 6 10 MJD44H11 (NPN), MJD45H11 (PNP) ORDERING INFORMATION Package Type Package Shipping† MJD44H11G DPAK (Pb−Free) 369C 75 Units / Rail NJVMJD44H11G DPAK (Pb−Free) 369C 75 Units / Rail MJD44H11−1G DPAK−3 (Pb−Free) 369D 75 Units / Rail MJD44H11RLG DPAK (Pb−Free) 369C 1,800 / Tape & Reel NJVMJD44H11RLG* DPAK (Pb−Free) 369C 1,800 / Tape & Reel MJD44H11T4G DPAK (Pb−Free) 369C 2,500 / Tape & Reel NJVMJD44H11T4G* DPAK (Pb−Free) 369C 2,500 / Tape & Reel MJD44H11T5G DPAK (Pb−Free) 369C 2,500 / Tape & Reel MJD45H11G DPAK (Pb−Free) 369C 75 Units / Rail NJVMJD45H11G* DPAK (Pb−Free) 369C 75 Units / Rail MJD45H11−1G DPAK−3 (Pb−Free) 369D 75 Units / Rail MJD45H11RLG DPAK (Pb−Free) 369C 1,800 / Tape & Reel NJVMJD45H11RLG* DPAK (Pb−Free) 369C 1,800 / Tape & Reel MJD45H11T4G DPAK (Pb−Free) 369C 2,500 / Tape & Reel NJVMJD45H11T4G* DPAK (Pb−Free) 369C 2,500 / Tape & Reel NJVMJD44H11D3T4G* DPAK (Pb−Free) 369G 2,500 / Tape & Reel NJVMJD45H11D3T4G* DPAK (Pb−Free) 369G 2,500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GAUGE) CASE 369C ISSUE F 4 1 2 DATE 21 JUL 2015 3 SCALE 1:1 A E b3 C A B c2 4 L3 Z D 1 L4 2 3 NOTE 7 b2 e c SIDE VIEW b 0.005 (0.13) TOP VIEW H DETAIL A M BOTTOM VIEW C Z H L2 GAUGE PLANE C L L1 DETAIL A Z SEATING PLANE BOTTOM VIEW A1 ALTERNATE CONSTRUCTIONS ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 8: PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 9: STYLE 10: PIN 1. ANODE PIN 1. CATHODE 2. CATHODE 2. ANODE 3. RESISTOR ADJUST 3. CATHODE 4. CATHODE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.102 5.80 0.228 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.028 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.114 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.72 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.90 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW AYWW XXX XXXXXG IC Discrete = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 6.17 0.243 SCALE 3:1 DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z XXXXXX A L Y WW G 3.00 0.118 1.60 0.063 STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. 7. OPTIONAL MOLD FEATURE. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON10527D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK−3, SURFACE MOUNT CASE 369G−01 ISSUE O 4 1 DATE 23 DEC 2003 2 3 SCALE 1:1 −T− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B V SEATING PLANE E R 4 Z A 1 2 3 U K F L J G D H 2 PL 0.13 (0.005) T DIM A B C D E F G H J K L R U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.51 −−− 0.89 1.27 3.93 −−− GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR YWW xxxxxxxx xxxxxxxxx = Device Code Y = Year WW = Work Week *This information is generic. Please refer to device data sheet for actual part marking. DOCUMENT NUMBER: DESCRIPTION: 98AON13702D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DPAK−3, SURFACE MOUNT PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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