MM74C373N

Revised January 2004 MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop General Description Features The MM74C373 and MM74C374 are integrated, complementary MOS (CMOS), 8-bit storage elements with 3STATE outputs. These outputs have been specially designed to drive high capacitive loads, such as one might find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to the OUTPUT DISABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. ■ Wide supply voltage range: The MM74C373 is an 8-bit latch. When LATCH ENABLE is high, the Q outputs will follow the D inputs. When LATCH ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the outputs until LATCH ENABLE returns high again. 3V to 15V ■ High noise immunity: 0.45 VCC (typ.) ■ Low power consumption ■ TTL compatibility: Fan out of 1driving standard TTL ■ Bus driving capability ■ 3-STATE outputs ■ Eight storage elements in one package ■ Single CLOCK/LATCH ENABLE and OUTPUT DISABLE control inputs ■ 20-pin dual-in-line package with 0.300” centers takes half the board space of a 24-pin package The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on positive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assembled in 20-pin dual-in-line packages with 0.300” pin centers. Ordering Code: Order Number Package Number Package Description MM74C373M (Note 1) M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 Fairchild Semiconductor Corporation DS005906 www.fairchildsemi.com MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop October 1987 MM74C373 • MM74C374 Connection Diagrams MM74C373 MM74C374 Top View Top View Truth Tables MM74C373 Output LATCH Disable ENABLE L H L H MM74C374 Clock D Q Disable   H H L L Q D Q H H L L L L L X L H X Q H X X Hi-Z L L L X Q H X X Hi-Z L = LOW logic level H = HIGH logic level X = Irrelevant www.fairchildsemi.com Output  = LOW-to-HIGH logic level transition Q = Preexisting output level Hi-Z = High impedance output state 2 MM74C373 • MM74C374 Block Diagrams MM74C373 (1 of 8 Latches) MM74C374 (1 of 8 Flip-Flops) 3 www.fairchildsemi.com MM74C373 • MM74C374 Absolute Maximum Ratings(Note 2) Voltage at Any Pin −0.3V to VCC + 0.3V Operating Temperature Range (TA) MM74C373 Storage Temperature Range (TS) −55°C to +125 °C −65°C to +150 °C Power Dissipation Dual-In-Line 700 mW Small Outline 500 mW Operating VCC Range Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. 3V to 15V Absolute Maximum VCC 18V Lead Temperature (TL) 260 °C (Soldering, 10 seconds) DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) Logical “1” Input Voltage Logical “0” Input Voltage Logical “1” Output Voltage Logical “0” Output Voltage VCC = 5V 3.5 VCC = 10V 8.0 VCC = 5V 1.5 VCC = 10V 2.0 VCC = 5V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 0.5 VCC = 10V, IO = 10 µA 1.0 Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V IOZ 3-STATE Leakage Current VCC = 15V, VO = 15V VCC = 15V, VO = 0V Supply Current 0.005 −1.0 VCC = 15V 1.0 −0.005 0.005 −1.0 V V VCC = 5V, IO = 10 µA IIN(1) ICC V µA µA 1.0 −0.005 0.05 V µA 300 µA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VCC − 0.4 VCC = 4.75V, IO = −1.6 mA 2.4 VOUT(0) Logical “0” Output Voltage VCC − 1.5 V V VCC = 4.75V, IO = 1.6 mA 0.4 V OUTPUT DRIVE (Short Circuit Current) ISOURCE Output Source Current VCC = 5V, VOUT = 0V −12 −24 mA −24 −48 mA 6 12 mA 24 48 mA TA = 25°C (Note 3) ISOURCE Output Source Current VCC = 10V, VOUT = 0V TA = 25°C (Note 3) ISINK ISINK Output Sink Current VCC = 5V, VOUT = VCC (N-Channel) TA = 25°C (Note 3) Output Sink Current VCC = 10V, VOUT = VCC (N-Channel) TA = 25°C (Note 3) Note 3: These are peak output current capabilities. Continuous output current is rated at 12 mA max. www.fairchildsemi.com 4 (Note 4) MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Symbol tpd0, tpd1 tpd0, tpd1 tSET-UP Parameter tPWH tr, tf t1H, t0H tH1, tH0 tTHL, tTLH Min Typ Max 165 330 VCC = 5V, CL = 50 pF LATCH ENABLE to Output VCC = 10V, CL = 50 pF 70 140 VCC = 5V, CL = 150 pF 195 390 VCC = 10V, CL = 150 pF 85 170 310 Propagation Delay Data LATCH ENABLE = VCC In to Output VCC = 5V, CL = 50 pF 155 VCC = 10V, CL = 50 pF 70 140 VCC = 5V, CL = 150 pF 185 370 VCC = 10V, CL = 150 pF 85 170 VCC = 5V 70 140 VCC = 10V 35 70 Minimum Set-Up Time Data In to CLOCK/LATCH ENABLE fMAX Conditions Propagation Delay, Units ns ns tHOLD = 0 ns Maximum LATCH ENABLE VCC = 5V 3.5 6.7 Frequency VCC = 10V 4.5 9.0 Minimum LATCH ENABLE VCC 5V 75 150 Pulse Width VCC = 10V 55 110 Maximum LATCH ENABLE VCC = 5V NA Rise and Fall Time VCC = 10V NA ns MHz ns µs Propagation Delay OUTPUT RL = 10k, CL = 5 pF DISABLE to High Impedance VCC = 5V 105 210 State (from a Logic Level) VCC = 10V 60 120 Propagation Delay OUTPUT RL = 10k, CL = 50 pF DISABLE to Logic Level VCC = 5V 105 210 (from High Impedance State) VCC = 10V 45 90 Transition Time VCC = 5V, CL = 50 pF 65 130 VCC = 10V, CL = 50 pF 35 70 VCC = 5V, CL = 150 pF 110 220 VCC = 10V, CL = 150 pF 70 140 ns ns ns CLE Input Capacitance LE Input (Note 5) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE 7.5 10 pF CIN Input Capacitance Any Other Input (Note 5) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pF Input (Note 5) State (Note 5) CPD Power Dissipation Capacitance Per Package (Note 6) 200 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Capacitance is guaranteed by periodic testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. 5 www.fairchildsemi.com MM74C373 • MM74C374 AC Electrical Characteristics MM74C373 • MM74C374 AC Electrical Characteristics (Note 7) MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted Symbol tpd0, tpd1 Parameter Propagation Delay, CLOCK to Output tSET-UP Conditions Min VCC = 5V, CL = 50 pF Typ Max 150 300 VCC = 10V, CL = 50 pF 65 130 VCC = 5V, CL = 150 pF 180 360 VCC = 10V, CL = 150 pF 80 160 140 Minimum Set-Up Time Data In tHOLD = 0 ns to CLOCK/LATCH ENABLE VCC = 5V 70 VCC = 10V 35 70 VCC = 5V 70 140 50 100 tPWH, tPWL Minimum CLOCK Pulse Width fMAX Maximum CLOCK Frequency t1H, t0H Propagation Delay OUTPUT RL = 10k, CL = 50 pF DISABLE to High Impedance VCC = 5V 105 210 State (from a Logic Level) VCC = 10V 60 120 210 VCC = 10V tH1, tH0 tTHL, tTLH VCC = 5V 3.5 7.0 VCC = 10V 5 10 Propagation Delay OUTPUT RL = 10k, CL = 50 pF VCC = 5V 105 (from High Impedance State) VCC = 10V 45 90 Transition Time VCC = 5V, CL = 50 pF 65 130 VCC = 10V, CL = 50 pF 35 70 VCC = 5V, CL = 150 pF 110 220 70 140 Maximum CLOCK Rise VCC = 5V 15 >2000 5 >2000 ns ns ns MHz DISABLE to Logic Level VCC = 10V, CL = 150 pF tr, tf Units ns ns ns µs and Fall Time VCC = 10V CCLK Input Capacitance CLOCK Input (Note 8) 7.5 10 pF COD Input Capacitance OUTPUT DISABLE 7.5 10 pF Input (Note 8) CIN Input Capacitance Any Other Input (Note 8) 5 7.5 pF COUT Output Capacitance High Impedance 10 15 pF State (Note 8) CPD Power Dissipation Capacitance Per Package (Note 9) 250 pF Note 7: AC Parameters are guaranteed by DC correlated testing. Note 8: Capacitance is guaranteed by periodic testing. Note 9: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note AN-90. www.fairchildsemi.com 6 MM74C373 Propagation Delay, LATCH ENABLE to Output vs Load Capacitance MM74C373, MM74C374 Change in Propagation Delay per pF of Load Capacitance (∆tPD/pF) vs Power Supply Voltage MM74C373 Propagation Delay, Data In to Output vs Load Capacitance MM74C373, MM74C374 Output Sink Current vs VOUT MM74C373 Propagation Delay, CLOCK to Output vs Load Capacitance MM74C373, MM74C374 Source Current vs VCC − VOUT 7 www.fairchildsemi.com MM74C373 • MM74C374 Typical Performance Characteristics MM74C373 • MM74C374 Typical Applications Data Bus Interfacing Element Simple, Latching, Octal, LED Indicator Driver with Blanking for Use as Data Display, Bus Monitor, µP Front Panel Display, Etc. 3-STATE Test Circuits and Switching Time Waveforms t1H, tH1 t0H , tH0 t1H, CL = 5 pF t0H, CL = 5 pF tH1, CL = 50 pF www.fairchildsemi.com tH0, CL = 50 pF 8 MM74C373 • MM74C374 Switching Time Waveforms MM74C373 Output Disable = GND MM74C374 Output Disable = GND 9 www.fairchildsemi.com MM74C373 • MM74C374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B www.fairchildsemi.com 10 MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 11 www.fairchildsemi.com