MM74HC139N

Revised December 2003 MM74HC139 Dual 2-To-4 Line Decoder General Description Features The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. ■ Typical propagation delays — The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input (G1, or G2). Data on the select inputs (A1, and B1 or A2, and B2) cause one of the four normally high outputs to go LOW. ■ Fanout of 10 LS-TTL devices Select to outputs (4 delays): 18 ns Select to output (5 delays): 28 ns Enable to output: 20 ns ■ Low power: 40 µW quiescent supply power ■ Input current maximum 1 µA, typical 10 pA The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally as well as pin equivalent to the 74LS139. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number MM74HC139M (Note 1) MM74HC139SJ MM74HC139MTC (Note 1) MM74HC139N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Enable Outputs Select G B A Y0 Y1 Y2 Y3 H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L H = HIGH Level L = LOW Level X = Don't Care © 2003 Fairchild Semiconductor Corporation DS005311 www.fairchildsemi.com MM74HC139 Dual 2-To-4 Line Decoder September 1983 MM74HC139 Logic Diagram (1 of 2) www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA Storage Temperature Range (TSTG) Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V −40 +85 °C (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times −65°C to +150°C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Power Dissipation (PD) (Note 4) 600 mW S.O. Package only 500 mW Note 2: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Note 3: Unless otherwise specified all voltages are referenced to ground. 260°C (Soldering 10 seconds) Note 4: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 5) Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 6.0V 4.2 4.2 4.2 Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 6.0V 1.8 1.8 1.8 Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT | ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 4.5V 4.5 4.4 4.4 4.4 6.0V 6.0 5.9 5.9 5.9 |IOUT | ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 |IOUT | ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 Units V V V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT | ≤ 20 µA 2.0V 0 0.1 0.1 0.1 4.5V 0 0.1 0.1 0.1 6.0V 0 0.1 0.1 0.1 0.4 V VIN = VIH or VIL IIN |IOUT | ≤ 4.0 mA 4.5V 0.2 0.26 0.33 |IOUT | ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA Supply Current IOUT = 0 µA Maximum Input Current ICC Note 5: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC139 Absolute Maximum Ratings(Note 2) MM74HC139 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter tPHL, tPLH Conditions Typ Maximum Propagation Guaranteed Limit Units 18 30 ns 28 38 ns 19 30 ns Delay, Binary Select to any Output 4 levels of delay tPHL, tPLH Maximum Propagation Delay, Binary Select to any Output 5 levels of delay tPHL, tPLH Maximum Propagation Delay, Enable to any Output AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter tPHL, tPLH Maximum Propagation Conditions (Note 6) Delay Binary Select to any Output 4 levels of delay tPHL, tPLH Maximum Propagation (Note 7) TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C 2.0V 110 175 219 4.5V 22 35 44 254 51 6.0V 18 30 38 44 2.0V 165 220 275 320 4.5V 33 44 55 64 Output 5 levels of delay 6.0V 28 38 47 54 2.0V 115 175 219 254 Delay Enable to any 4.5V 23 35 44 51 Output 6.0V 19 30 38 44 110 tTLH, tTLH Maximum Output Rise and Fall Time 2.0V 30 75 95 4.5V 8 15 19 22 6.0V 7 13 16 19 3 10 10 10 Maximum Input Units Guaranteed Limits Delay Binary Select to any tPHL, tPLH Maximum Propagation CIN VCC ns ns ns ns pF Capacitance CPD Power Dissipation (Note 8) 75 Capacitance (Note 8) Note 6: 4 levels of delay are A to Y1, Y3 and B to Y2, Y3. Note 7: 5 levels of delay are A to Y0, Y2 and B to Y0, Y1. Note 8: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF MM74HC139 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com MM74HC139 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 6 MM74HC139 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 7 www.fairchildsemi.com MM74HC139 Dual 2-To-4 Line Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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