MM74HC174MTC

Revised February 1999 MM74HC174 Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state. Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC174 is functionally as well as pin compatible to the 74LS174. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■ Typical propagation delay: 16 ns ■ Wide operating voltage range: 2–6V ■ Low input current: 1 µA maximum ■ Low quiescent current: 80 µA (74HC Series) ■ Output drive: 10 LSTTL loads Ordering Code: Order Number MM74HC174M MM74HC174SJ MM74HC174MTC MM74HC174N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table (Each Flip-Flop) Inputs Pin Assignments for DIP, SOIC, SOP and TSSOP Outputs Clear Clock D L X X Q L H ↑ H H H ↑ L L H L X Q0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care ↑ = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady state input conditions were established. © 1999 Fairchild Semiconductor Corporation DS005318.prf www.fairchildsemi.com MM74HC174 Hex D-Type Flip-Flops with Clear September 1983 MM74HC174 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA (VIN, VOUT) Operating Temperature Range (TA) 600 mW 500 mW Symbol VIH VIL VOH Parameter Conditions 0 VCC V −40 +85 °C 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Note 2: Unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units 6 (tr, tf) VCC = 2.0V Power Dissipation (PD) S.O. Package only Max 2 Input Rise or Fall Times −65°C to +150°C (Note 3) Min DC Input or Output Voltage ±50 mA DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 Input Voltage 4.5V 3.15 3.15 3.15 V V 6.0V 4.2 4.2 4.2 V V Maximum LOW Level 2.0V 0.5 0.5 0.5 Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V 8.0 80 160 µA VIN = VIH or VIL IIN Maximum Input ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Current Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC174 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC174 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6 ns Symbol fMAX Parameter Conditions Guaranteed Typ Maximum Operating Units Limit 50 30 MHz 16 30 ns −2 5 ns 10 20 ns 0 5 ns 10 16 ns Frequency tPHL, tPLH Maximum Propagation Delay, Clock or Clear to Output tREM Minimum Removal Time, Clear to Clock tS Minimum Setup Time Data to Clock tH Minimum Hold Time Clock to Data tW Minimum Pulse Width Clock or Clear AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions VCC TA = 25°C 5 4 3 MHz Frequency 4.5V 27 21 18 MHz MHz Delay Clock or Clear to Output Minimum Removal Time 20 165 206 248 ns 4.5V 18 33 41 49 ns 6.0V 16 28 35 42 ns 2.0V 1 5 5 5 ns 1 5 5 5 ns 6.0V 1 5 5 5 ns Minimum Setup Time 2.0V 42 100 125 150 ns ns Minimum Hold Time 4.5V 12 20 25 30 6.0V 10 17 21 25 ns 2.0V 1 5 5 5 ns 4.5V 1 5 5 5 ns 6.0V 1 5 5 5 ns Minimum Pulse Width 2.0V 35 80 106 120 ns Clock or Clear 4.5V 10 16 20 24 ns 6.0V 8 14 18 20 ns 2.0V 30 75 95 110 ns 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns tTLH, tTHL Maximum Output Rise and Fall Time tr, tf 24 55 4.5V Clock to Data tW 31 2.0V Clear to Clock Data to Clock tH Maximum Input Rise and 2.0V 1000 1000 1000 ns Fall Time 4.5V 500 500 500 ns 400 400 400 6.0V CPD Units 2.0V 6.0V tS Guaranteed Limits Maximum Operating tPHL, tPLH Maximum Propagation tREM TA = −40 to 85°C TA = −55 to 125°C Typ Power Dissipation (per package) 136 ns pF Capacitance (Note 5) CIN Maximum Input 5 10 10 10 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. www.fairchildsemi.com 4 pF MM74HC174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com MM74HC174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 6 16-Lead Plastic Dual-In Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. MM74HC174 Hex D-Type Flip-Flops with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued)