MMSF7P03HD

MMSF7P03HD Preferred Device Power MOSFET 7 A, 30 V, P−Channel SO−8 These miniature surface mount devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are DC−DC converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. Features http://onsemi.com 7 A, 30 V − RDS(on) = 35 mW D P−Channel • • • • • • • • Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive − Can Be Driven by Logic ICs Miniature SO−8 Surface Mount Package − Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Mounting Information for SO−8 Package Provided Pb−Free Package is Available 8 G S MARKING DIAGRAM 8 SO−8 CASE 751 STYLE 12 1 S7P03 AYWWG G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage Drain Current Continuous Symbol VDSS VGS ID IDM IS PD TJ, Tstg EAS Value 30 ± 20 7.0 50 2.3 2.5 − 55 to 150 500 Unit Vdc Vdc Adc Apk Adc W °C mJ 1 Continuous @ TA = 25°C Single Pulse (tp ≤ 10 ms) Source Current − Continuous @ TA = 25°C Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 32 Vdc, IL = 10 Apk, L = 10 mH, RG = 25 W) Thermal Resistance, Junction−to−Ambient Maximum Temperature for Soldering S7P03 = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT Source Source Source Gate 1 2 3 4 8 7 6 5 Drain Drain Drain Drain RqJA T 50 260 °C/W °C Top View ORDERING INFORMATION Device MMSF7P03HDR2 MMSF7P03HDR2G Package SO−8 Shipping† 2500 / Tape&Reel Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When mounted on 1 in square FR−4 or G−10 (VGS = 10 V @ 10 seconds) SO−8 2500 / Tape&Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 1 February, 2006 − Rev. 7 Publication Order Number: MMSF7P03HD/D MMSF7P03HD ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 2) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 5.3 Adc) (VGS = 4.5 Vdc, ID = 2.0 Adc) Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 10 Vdc, ID = 4.9 Adc, VGS = 6.0 Vdc) (VDD = 15 Vdc, ID = 1.0 Adc, VGS = 10 Vdc, RG = 6.0 W) (VDD = 15 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 10 W) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 2.3 Adc, VGS = 0 Vdc) (IS = 2.3 Adc, VGS = 0 Vdc, TJ = 125°C) VSD − − − − − − 0.76 0.61 47.9 27 21 0.052 1.2 − − − − − mC Vdc − − − − − − − − − − − − 23.5 42.7 57.4 53.6 16 15.2 99.7 55.2 37.9 4.2 11.5 7.6 47 85.4 114.8 107.2 32 30.6 199.4 110.4 75.8 − − − nC ns (VDS = 24 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss Coss Crss − − − 1200 580 160 1680 810 220 pF VGS(th) 1.0 RDS(on) − − gFS − 26 42 12 35 50 − Mhos − − mW Vdc V(BR)DSS 30 IDSS − − IGSS − − − − 1.0 25 100 nAdc − − mAdc Vdc Symbol Min Typ Max Unit Reverse Recovery Time (IS = 4.9 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 2. Negative sign for P−Channel device omitted for clarity. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. trr ta tb QRR ns http://onsemi.com 2 MMSF7P03HD TYPICAL ELECTRICAL CHARACTERISTICS 12 I D, DRAIN CURRENT (AMPS) 10 V 6.0 V 10 4.5 V 8.0 6.0 4.0 2.0 0 0 RDS(on) DRAIN−TO−SOURCE RESISTANCE (OHMS) , 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 RDS(on) DRAIN−TO−SOURCE RESISTANCE (OHMS) , VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 4.3 V 4.1 V 12 I D, DRAIN CURRENT (AMPS) 10 8.0 6.0 4.0 2.0 0 1.5 2.0 2.5 3.0 3.5 4.0 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 25°C TJ = − 55°C 100°C VDS . 10 V 3.9 V 3.7 V TJ = 25°C 3.5 V VGS = 3.3 V 3.1 V 2.9 V 2.7 V 2.5 V Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.30 0.25 0.20 0.15 0.10 0.05 0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C ID = 7.0 A 0.050 TJ = 25°C 0.045 0.040 0.035 0.030 0.025 0.020 1.0 VGS = 4.5 V 10 V 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage RDS(on) DRAIN−TO−SOURCE RESISTANCE , (NORMALIZED) Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.6 1.4 VGS = 10 V I DSS LEAKAGE (nA) , 1000 VGS = 0 V TJ = 125°C 100 1.2 1.0 0.8 0.6 100°C 10 0.4 0.2 0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 1.0 0 5.0 10 15 20 25 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 MMSF7P03HD POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 3500 C, CAPACITANCE (pF) 3000 2500 2000 1500 1000 Coss 500 0 −10 VGS 0 VDS 10 20 Crss 30 Ciss TJ = 25°C The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. VGS GATE−TO−SOURCE VOLTAGE (VOLTS) , 7.0 QT 6.0 30 5.0 Q1 Q2 VGS 4.0 20 3.0 10 TJ = 25°C ID = 7.0 A 0 20 25 30 35 40 2.0 Q3 0 5.0 10 1.0 0 VD 15 S VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge http://onsemi.com 4 V , DRAIN−TO−SOURCE VOLTAGE (VOLTS) MMSF7P03HD 100 0 TJ = 25°C ID = 7.0 A VDD = 15 V VGS = 10 V td(off) t, TIME (ns) 100 tf tr 10 td(on) 1.0 1.0 10 RG, GATE RESISTANCE (W) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 6.0 IS, SOURCE CURRENT (AMPS) 5.0 4.0 3.0 2.0 1.0 0 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) t, TIME I S , SOURCE CURRENT high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. di/dt = 300 A/ms TJ = 25°C VGS = 0 V Standard Cell Density trr High Cell Density trr tb ta Figure 10. Diode Forward Voltage versus Current Figure 11. Reverse Recovery Time (trr) http://onsemi.com 5 MMSF7P03HD SAFE OPERATING AREA The Forward Biased Safe Operating Area curve (Figure 12) defines the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 100 I D, DRAIN CURRENT (AMPS) VGS = 12 V SINGLE PULSE TA = 25°C 10 ms 1.0 dc 1 ms E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 25 45 65 85 105 125 145 ID = 7.0 A 10 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.0 1 0.1 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 MMSF7P03HD TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t)EFFECTIVE TRANSIENT , THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 0.0 5 0.02 0.01 0.0 1 Chip Junction SINGLE PULSE 0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W 0.0253 F 0.1406 F 0.00 1.0E−05 1 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 0.5064 F 2.9468 F 177.14 F Ambient 1.0E+01 1.0E+02 1.0E+03 Figure 14. Thermal Response trr tb tp Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 7 MMSF7P03HD PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AG −X− A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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