MTD20N06HDLT4G

MTD20N06HDL Preferred Device Power MOSFET 20 Amps, 60 Volts, Logic Level N−Channel DPAK This advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain−to−source diode with a fast recovery time. Designed for low−voltage, high−speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits, and inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. Features http://onsemi.com 20 AMPERES, 60 VOLTS RDS(on) = 45 mW N−Channel D • Avalanche Energy Specified • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Pb−Free Package is Available Rating Drain−Source Voltage Drain−Gate Voltage (RGS = 1.0 MW) Gate−Source Voltage − Continuous − Non−Repetitive (tp ≤ 10 ms) Drain Current − Continuous @ 25°C Drain Current − Continuous @ 100°C Drain Current − Single Pulse (tp ≤ 10 ms) Total Power Dissipation Derate above 25°C Total Power Dissipation @ TC = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGSM ID ID G S MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Value 60 60 ± 15 ± 20 20 12 60 40 0.32 1.75 − 55 to 150 200 Unit Vdc Vdc Vdc Vpk Adc Apk W W/°C W °C mJ MARKING DIAGRAM & PIN ASSIGNMENTS Gate 1 Drain 2 3 DPAK CASE 369C STYLE 2 Source 3 YWW 20N 06HLG 4 Drain 4 12 IDM PD TJ, Tstg EAS Y WW 20N06HL G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION Device Package DPAK DPAK Shipping† 75 Units/Rail 2500 Tape & Reel RJC RJA RJA TL 3.13 100 71.4 260 °C/W MTD20N06HDL MTD20N06HDLT4 °C MTD20N06HDLT4G DPAK 2500 Tape & Reel (Pb−Free) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR−4 board using the minimum recommended pad size. 2. When surface mounted to an FR−4 board using the 0.5 sq.in. drain pad size. †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Preferred devices are recommended choices for future use and best overall value. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 6 1 Publication Order Number: MTD20N06HDL/D MTD20N06HDL ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0) ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−Source On−Resistance (VGS = 4.0 Vdc, ID = 10 Adc) (VGS = 5.0 Vdc, ID = 10 Adc) Drain−Source On−Voltage (VGS = 5.0 Vdc) (ID = 20 Adc) (ID = 10 Adc, TJ = 125°C) Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 20 Adc, VGS = 5.0 Vdc) (VDS = 30 Vdc, ID = 20 Adc, VGS = 5.0 Vdc, RG = 9.1 W) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C) VSD − − − − − − 0.95 0.88 22 12 34 0.049 1.1 − − − − − mC nH nH Vdc − − − − − − − − 11 151 34 75 14.6 3.25 7.75 7.0 15 190 35 98 22 − − − nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss − − − 863 216 53 1232 300 73 pF VGS(th) 1.0 − − − − − 6.0 1.5 6.0 0.045 0.037 0.76 − 12 2.0 − 0.070 0.045 1.2 1.1 − Vdc mV/°C W V(BR)DSS 60 − − − − − 25 − − − − − 10 100 100 Vdc mV/°C mAdc Symbol Min Typ Max Unit IDSS IGSS nAdc RDS(on) VDS(on) Vdc gFS mhos Reverse Recovery Time (IS = 20 Adc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25″ from package to center of die) Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. trr ta tb QRR LD LS ns − − 4.5 7.5 − − http://onsemi.com 2 MTD20N06HDL TYPICAL ELECTRICAL CHARACTERISTICS 40 I D , DRAIN CURRENT (AMPS) 40 VDS ≥ 10 V I D , DRAIN CURRENT (AMPS) 4V 30 TJ = 25°C 8V 6V 5V 4.5 V VGS = 10 V 30 20 3.5 V 20 10 3V 2.5 V 10 100°C 25°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 1.5 TJ = − 55°C 2 2.5 3 3.5 4 4.5 VGS, GATE−TO−SOURCE VOLTAGE (Volts) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0.07 VGS = 5 V 0.06 0.05 0.04 0.03 0.02 0.01 0 0 10 20 ID, DRAIN CURRENT (Amps) 30 40 25°C − 55°C TJ = 100°C 0.05 Figure 2. Transfer Characteristics TJ = 25°C 0.045 0.04 5V 0.035 VGS = 10 V 0.03 0.025 0 10 20 ID, DRAIN CURRENT (Amps) 30 40 Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage R DS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 VGS = 5 V ID = 10 A I DSS , LEAKAGE (nA) 1000 VGS = 0 V 1.4 100 TJ = 125°C 100°C 1.2 1.0 10 25°C 0.8 0.6 − 50 − 25 0 25 50 75 100 125 150 1 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature http://onsemi.com 3 Figure 6. Drain−to−Source Leakage Current versus Voltage MTD20N06HDL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 3000 2500 Ciss C, CAPACITANCE (pF) 2000 1500 C rss 1000 500 0 10 Coss Crss 5 VGS 0 VDS 5 10 15 20 25 Ciss VDS = 0 V VGS = 0 V The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. TJ = 25°C GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts) Figure 7. Capacitance Variation http://onsemi.com 4 MTD20N06HDL VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 12 10 8 6 Q1 4 2 0 Q3 0 2 4 6 8 10 12 14 Q2 ID = 20 A TJ = 25°C VDS VGS QT 60 50 40 30 20 10 0 16 VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 VDD = 30 V ID = 20 A VGS = 5 V TJ = 25°C 100 t, TIME (ns) tr tf td(off) 10 td(on) 1 1 10 RG, GATE RESISTANCE (Ohms) 100 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 10. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by 20 I S , SOURCE CURRENT (AMPS) VGS = 0 V TJ = 25°C high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. 16 12 8 4 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.9 0.95 VSD, SOURCE−TO−DRAIN VOLTAGE (Volts) Figure 10. Diode Forward Voltage versus Current http://onsemi.com 5 MTD20N06HDL di/dt = 300 A/ms Standard Cell Density trr High Cell Density trr tb ta I S , SOURCE CURRENT t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 100 VGS = 20 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 10 ms 200 ID = 20 A 150 I D , DRAIN CURRENT (AMPS) 100 ms 10 1 ms 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1.0 dc 10 100 100 50 1.0 0.1 0 25 50 75 100 125 150 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 6 MTD20N06HDL TYPICAL ELECTRICAL CHARACTERISTICS r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 0.00001 t1 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) P(pk) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 0.0001 0.1 1.0 10 Figure 14. Thermal Response di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 7 MTD20N06HDL PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− C E S A 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) T M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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